Makefile template for executable

Makefile

# Makefile template for executable

CC = gcc # C compiler
CFLAGS = -Wall -Wextra -O2 -g # C flags
LDFLAGS =  # linking flags
RM = rm -f # rm command
TARGET = program # target lib

SRCS = main.c \
	   src1.c \
	   src2.c	 # source files
OBJS = $(SRCS:.c=.o)

.PHONY: all
all: ${TARGET}

$(TARGET): $(OBJS)
	$(CC) ${LDFLAGS} -o $@ $^

$(SRCS:.c=.d):%.d:%.c
	$(CC) $(CFLAGS) -MM $< >$@

include $(SRCS:.c=.d)

.PHONY: clean
clean:
	-${RM} ${TARGET} ${OBJS} $(SRCS:.c=.d)