Created
June 9, 2022 12:12
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Lenovo Xiaoxin Pad Pro 2021 downstream DTS
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| /dts-v1/; | |
| / { | |
| #address-cells = <0x02>; | |
| model = "Qualcomm Technologies, Inc. kona standalone MTP"; | |
| qcom,board-id = <0x2010008 0x00>; | |
| #size-cells = <0x02>; | |
| interrupt-parent = <0x01>; | |
| compatible = "qcom,kona-mtp\0qcom,kona\0qcom,mtp"; | |
| qcom,msm-id = <0x164 0x20001>; | |
| mem-offline { | |
| offline-sizes = <0x01 0x40000000 0x00 0x40000000 0x01 0xc0000000 0x00 0x80000000 0x02 0xc0000000 0x01 0x40000000>; | |
| granule = <0x400>; | |
| compatible = "qcom,mem-offline"; | |
| mboxes = <0x02 0x00>; | |
| }; | |
| vendor { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| compatible = "simple-bus"; | |
| ranges = <0x00 0x00 0x00 0xffffffff>; | |
| phandle = <0x61e>; | |
| extcon_usb1 { | |
| pinctrl-names = "default"; | |
| id-gpio = <0x66 0x5b 0x00>; | |
| pinctrl-0 = <0x69b 0x4d6 0x69c>; | |
| vbus-out-gpio = <0x695 0x09 0x00>; | |
| compatible = "linux,extcon-usb-gpio"; | |
| vbus-gpio = <0x695 0x0a 0x00>; | |
| phandle = <0x6a3>; | |
| }; | |
| qcom,battery-data { | |
| qcom,batt-id-range-pct = <0x0f>; | |
| phandle = <0x625>; | |
| qcom,alium_860_89032_0000_3600mah_averaged_masterslave_sep24th2018 { | |
| qcom,therm-coefficients = <0x2318 0xd0c 0xdaf7 0xc556 0x848d>; | |
| qcom,max-voltage-uv = <0x432380>; | |
| qcom,battery-type = "alium_860_89032_0000_3600mah_sept24th2018"; | |
| qcom,jeita-fcc-ranges = <0x00 0x96 0x19a280 0x97 0x1c2 0x401640 0x1c3 0x1f4 0x19a280>; | |
| qcom,ocv-based-step-chg; | |
| qcom,jeita-hard-thresholds = <0x3aa4 0xc38>; | |
| qcom,therm-center-offset = <0x70>; | |
| qcom,jeita-soft-thresholds = <0x307f 0x1250>; | |
| qcom,jeita-soft-fv-uv = <0x432380 0x432380>; | |
| qcom,fg-profile-data = <0x900c7ea 0xc4dc8ee2 0x3add0000 0x15bca58a 0x280d192 0xab9d4780 0x1000df02 0x771a85ec 0xe1fdce07 0x320075eb 0xaaedf3cd 0xc0a7ae4 0xedc5401b 0xd0021fca 0xff005200 0x4d004a00 0x3c003500 0x38003900 0x48004300 0x3f00ff00 0x38004000 0x46005000 0x45005c00 0x7e646000 0x50085010 0xff006a00 0x5f006300 0x6e006000 0x7d209640 0x75506b13 0x6300d800 0x14227e0d 0x2102aa04 0xed1cd409 0x640cd323 0xa418d342 0xb5559102 0x90122a1f 0x2061f0a 0xa306ae1c 0x8d029604 0xd203d117 0x51233f45 0x28536914 0x93208eec 0x18cbc8c5 0xdb1c7bc9 0x7c05e6c2 0xb9172c93 0x8785a292 0x91a80980 0x92f21a0d 0xf4fc5eeb 0xf8fbed 0x15e2f60f 0x75027205 0x49011000 0xfae5e203 0x8d058502 0xce073200 0x23034602 0x9c040302 0x48070a00 0xba039702 0x65055000 0x3a004100 0x43644500 0x45104518 0x46084400 0x47003a08 0x4b083700 0x47204e40 0x54586010 0x57005f00 0x57085500 0x4b005000 0x3e085208 0x52005c20 0x6f407d58 0x67106300 0x69084f10 0xd8008c2a 0xdb042802 0xad040b1d 0x5022a745 0xd52a218 0x7403ad04 0x3502ae13 0x3f0a5a20 0xdd04f102 0xd805c71c 0xdd023d04 0xeb039718 0x5203d504 0x19027200 0x14227e05 0x2102aa04 0xed1cd401 0x6404d303 0xa418d302 0xb5059102 0x90007c01 0xc000fa00 0x40e0000>; | |
| qcom,fastchg-current-ma = <0x1518>; | |
| qcom,jeita-soft-hys-thresholds = <0x2cf2 0x13f9>; | |
| qcom,therm-pull-up = <0x1e>; | |
| qcom,checksum = <0x1538>; | |
| qcom,jeita-fv-ranges = <0x00 0x96 0x432380 0x97 0x1c2 0x432380 0x1c3 0x1f4 0x401640>; | |
| qcom,gui-version = "PM855GUI - 1.0.0.10"; | |
| qcom,rslow-low-coeffs = <0x51 0x04 0xd0 0x13>; | |
| qcom,therm-room-temp = <0x186a0>; | |
| qcom,fg-cc-cv-threshold-mv = <0x1126>; | |
| qcom,step-chg-ranges = <0x36ee80 0x39fbc0 0x5265c0 0x39fbc1 0x419ce0 0x36ee80 0x419ce1 0x426030 0x2625a0>; | |
| qcom,jeita-soft-fcc-ua = <0x2625a0 0x2625a0>; | |
| qcom,rslow-normal-coeffs = <0xdf 0x02 0x77 0x1a>; | |
| qcom,batt-id-kohm = <0x6b>; | |
| qcom,battery-beta = <0xed8>; | |
| }; | |
| }; | |
| bt_qca6390 { | |
| pinctrl-names = "default"; | |
| qca,bt-vdd-rfa2-voltage-level = <0x149970 0x149970>; | |
| pinctrl-0 = <0x4a3>; | |
| qca,bt-vdd-asd-supply = <0x2c7>; | |
| qca,bt-vdd-dig-voltage-level = <0xe7ef0 0xe86c0>; | |
| qca,bt-reset-gpio = <0x66 0x15 0x00>; | |
| qca,bt-vdd-asd-current-level = <0x2710>; | |
| qca,wl-reset-gpio = <0x66 0x14 0x00>; | |
| qca,bt-vdd-aon-voltage-level = <0xe7ef0 0xe7ef0>; | |
| compatible = "qca,qca6390"; | |
| qca,bt-vdd-rfa1-supply = <0xaa>; | |
| qca,bt-vdd-rfa1-voltage-level = <0x1cfde0 0x1cfde0>; | |
| qca,bt-vdd-rfa2-supply = <0xab>; | |
| phandle = <0x746>; | |
| qca,bt-vdd-dig-supply = <0xa8>; | |
| qca,bt-vdd-asd-voltage-level = <0x2e2480 0x326a40>; | |
| qca,bt-sw-ctrl-gpio = <0x66 0x7c 0x00>; | |
| qca,bt-vdd-aon-supply = <0xa7>; | |
| }; | |
| }; | |
| cpu-pmu { | |
| interrupts = <0x01 0x07 0x04>; | |
| qcom,irq-is-percpu; | |
| compatible = "arm,armv8-pmuv3"; | |
| phandle = <0x348>; | |
| }; | |
| soc { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| compatible = "simple-bus"; | |
| ranges = <0x00 0x00 0x00 0xffffffff>; | |
| phandle = <0x349>; | |
| tpdm@6900000 { | |
| arm,primecell-periphid = <0x3b968>; | |
| qcom,proxy-regs = "vddcx\0vdd"; | |
| vddcx-supply = <0x17c>; | |
| clock-names = "apb_pclk\0rbbmtimer_clk\0mem_clk\0mem_iface_clk\0gmu_clk\0gpu_cc_ahb\0l3_vote"; | |
| reg-names = "tpdm-base"; | |
| qcom,proxy-clks = "rbbmtimer_clk\0mem_clk\0mem_iface_clk\0gmu_clk\0gpu_cc_ahb\0l3_vote"; | |
| clocks = <0x49 0x00 0x6e 0x09 0x16 0x16 0x16 0x26 0x6e 0x03 0x6e 0x00 0x1ae 0x03>; | |
| coresight-name = "coresight-tpdm-gpu"; | |
| vdd-supply = <0x1af>; | |
| compatible = "arm,primecell"; | |
| reg = <0x6900000 0x1000>; | |
| regulator-names = "vddcx\0vdd"; | |
| phandle = <0x4eb>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x1b2>; | |
| phandle = <0x1b1>; | |
| }; | |
| }; | |
| }; | |
| qcom,wb-display@0 { | |
| cell-index = <0x00>; | |
| label = "wb_display"; | |
| compatible = "qcom,wb-display"; | |
| phandle = <0x643>; | |
| }; | |
| suspendable-llcc-bw-opp-table { | |
| compatible = "operating-points-v2"; | |
| phandle = <0x4f>; | |
| opp-1000 { | |
| opp-hz = <0x00 0x3b9a>; | |
| }; | |
| opp-300 { | |
| opp-hz = <0x00 0x11e1>; | |
| }; | |
| opp-600 { | |
| opp-hz = <0x00 0x23c3>; | |
| }; | |
| opp-806 { | |
| opp-hz = <0x00 0x300a>; | |
| }; | |
| opp-466 { | |
| opp-hz = <0x00 0x1bc6>; | |
| }; | |
| opp-933 { | |
| opp-hz = <0x00 0x379c>; | |
| }; | |
| opp-150 { | |
| opp-hz = <0x00 0x8f0>; | |
| }; | |
| opp-0 { | |
| opp-hz = <0x00 0x00>; | |
| }; | |
| }; | |
| cti@6e21000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti-ddr_ch13_dl_cti_0"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6e21000 0x1000>; | |
| phandle = <0x513>; | |
| }; | |
| i2c@a90000 { | |
| pinctrl-names = "default\0sleep"; | |
| #address-cells = <0x01>; | |
| pinctrl-0 = <0x2ad>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| interrupts = <0x00 0x165 0x04>; | |
| clocks = <0x16 0x72 0x16 0x86 0x16 0x87>; | |
| #size-cells = <0x00>; | |
| qcom,wrapper-core = <0x2a3>; | |
| dma-names = "tx\0rx"; | |
| compatible = "qcom,i2c-geni"; | |
| pinctrl-1 = <0x2ae>; | |
| status = "disabled"; | |
| reg = <0xa90000 0x4000>; | |
| phandle = <0x5b5>; | |
| dmas = <0x2a4 0x00 0x04 0x03 0x40 0x00 0x2a4 0x01 0x04 0x03 0x40 0x00>; | |
| }; | |
| qcom,msm-sen-auxpcm { | |
| qcom,msm-cpudai-auxpcm-quant = <0x02 0x02>; | |
| qcom,msm-cpudai-auxpcm-frame = <0x05 0x04>; | |
| qcom,msm-cpudai-auxpcm-sync = <0x01 0x01>; | |
| qcom,msm-auxpcm-interface = "senary"; | |
| qcom,msm-cpudai-auxpcm-slot-mapping = <0x01 0x01>; | |
| qcom,msm-cpudai-auxpcm-data = <0x00 0x00>; | |
| qcom,msm-cpudai-afe-clk-ver = <0x02>; | |
| qcom,msm-cpudai-auxpcm-num-slots = <0x01 0x01>; | |
| compatible = "qcom,msm-auxpcm-dev"; | |
| qcom,msm-cpudai-auxpcm-mode = <0x00 0x00>; | |
| phandle = <0x2fa>; | |
| qcom,msm-cpudai-auxpcm-pcm-clk-rate = <0x1f4000 0x1f4000>; | |
| }; | |
| cti@601e000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti14"; | |
| compatible = "arm,primecell"; | |
| reg = <0x601e000 0x1000>; | |
| phandle = <0x526>; | |
| }; | |
| hwlock { | |
| syscon = <0x81 0x00 0x1000>; | |
| compatible = "qcom,tcsr-mutex"; | |
| phandle = <0x83>; | |
| #hwlock-cells = <0x01>; | |
| }; | |
| i2c@998000 { | |
| pinctrl-names = "default\0sleep"; | |
| #address-cells = <0x01>; | |
| pinctrl-0 = <0x28d>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| interrupts = <0x00 0x25f 0x04>; | |
| clocks = <0x16 0x64 0x16 0x84 0x16 0x85>; | |
| #size-cells = <0x00>; | |
| qcom,wrapper-core = <0x274>; | |
| dma-names = "tx\0rx"; | |
| compatible = "qcom,i2c-geni"; | |
| pinctrl-1 = <0x28e>; | |
| status = "disabled"; | |
| reg = <0x998000 0x4000>; | |
| phandle = <0x5a6>; | |
| dmas = <0x280 0x00 0x06 0x03 0x40 0x00 0x280 0x01 0x06 0x03 0x40 0x00>; | |
| }; | |
| etm@7640000 { | |
| arm,primecell-periphid = <0xbb95d>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x49 0x00>; | |
| cpu = <0x13>; | |
| qcom,tupwr-disable; | |
| coresight-name = "coresight-etm6"; | |
| compatible = "arm,primecell"; | |
| reg = <0x7640000 0x1000>; | |
| phandle = <0x54d>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x241>; | |
| phandle = <0x24a>; | |
| }; | |
| }; | |
| }; | |
| interrupt-controller@17a00000 { | |
| #redistributor-regions = <0x01>; | |
| interrupts = <0x01 0x09 0x04>; | |
| redistributor-stride = <0x00 0x20000>; | |
| compatible = "arm,gic-v3"; | |
| #interrupt-cells = <0x03>; | |
| reg = <0x17a00000 0x10000 0x17a60000 0x100000>; | |
| phandle = <0x01>; | |
| interrupt-controller; | |
| }; | |
| qcom,mdss_rotator@aea8800 { | |
| power-domains = <0x24c>; | |
| qcom,mdss-rot-mode = <0x01>; | |
| rot-vdd-supply = <0x71>; | |
| qcom,mdss-rot-safe-lut = <0xffff 0xffff>; | |
| clock-names = "gcc_iface\0gcc_bus\0iface_clk\0rot_clk"; | |
| reg-names = "mdp_phys\0rot_vbif_phys"; | |
| qcom,msm-bus,name = "mdss_rotator"; | |
| interrupts = <0x02 0x00>; | |
| clocks = <0x16 0x18 0x16 0x1a 0x6c 0x00 0x6c 0x32>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x03>; | |
| interrupt-parent = <0x24c>; | |
| qcom,mdss-rot-vbif-memtype = <0x03 0x03>; | |
| qcom,mdss-sbuf-headroom = <0x14>; | |
| qcom,mdss-highest-bank-bit = <0x03>; | |
| qcom,mdss-rot-vbif-qos-setting = <0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03>; | |
| compatible = "qcom,sde_rotator"; | |
| qcom,mdss-rot-cdp-setting = <0x01 0x01>; | |
| qcom,mdss-rot-danger-lut = <0x00 0x00>; | |
| qcom,mdss-default-ot-rd-limit = <0x20>; | |
| status = "disabled"; | |
| qcom,supply-names = "rot-vdd"; | |
| qcom,mdss-rot-qos-lut = <0x00 0x00 0x00 0x00>; | |
| qcom,mdss-default-ot-wr-limit = <0x20>; | |
| reg = <0xae00000 0xac000 0xaeb8000 0x3000>; | |
| #list-cells = <0x01>; | |
| phandle = <0x554>; | |
| qcom,msm-bus,vectors-KBps = <0x19 0x200 0x00 0x00 0x19 0x200 0x00 0x61a800 0x19 0x200 0x00 0x61a800>; | |
| qcom,smmu_rot_unsec_cb { | |
| iommus = <0x47 0x215c 0x400>; | |
| compatible = "qcom,smmu_sde_rot_unsec"; | |
| qcom,iommu-dma-addr-pool = <0x20000 0xfffe0000>; | |
| phandle = <0x556>; | |
| qcom,iommu-faults = "non-fatal"; | |
| }; | |
| qcom,rot-reg-bus { | |
| qcom,msm-bus,name = "mdss_rot_reg"; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| phandle = <0x555>; | |
| qcom,msm-bus,vectors-KBps = <0x01 0x24e 0x00 0x00 0x01 0x24e 0x00 0x12c00>; | |
| }; | |
| }; | |
| qcom,npudsp-npu-ddr-bwmon@70200 { | |
| qcom,msm_bus = <0x9a 0x2756>; | |
| qcom,bwmon_clks = "npu_bwmon_ahb\0npu_bwmon_axi"; | |
| clock-names = "npu_bwmon_ahb\0npu_bwmon_axi"; | |
| reg-names = "base\0global_base"; | |
| interrupts = <0x00 0x9b 0x04>; | |
| clocks = <0x16 0x2a 0x16 0x29>; | |
| qcom,msm_bus_name = "npudsp_bwmon_cdsp"; | |
| compatible = "qcom,bimc-bwmon4"; | |
| qcom,hw-timer-hz = <0x124f800>; | |
| qcom,mport = <0x00>; | |
| qcom,count-unit = <0x10000>; | |
| reg = <0x70300 0x300 0x70200 0x200>; | |
| phandle = <0x361>; | |
| qcom,target-dev = <0x53>; | |
| }; | |
| i2c@a88000 { | |
| pinctrl-names = "default\0sleep"; | |
| #address-cells = <0x01>; | |
| pinctrl-0 = <0x2a9>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| interrupts = <0x00 0x163 0x04>; | |
| clocks = <0x16 0x6e 0x16 0x86 0x16 0x87>; | |
| #size-cells = <0x00>; | |
| qcom,wrapper-core = <0x2a3>; | |
| dma-names = "tx\0rx"; | |
| compatible = "qcom,i2c-geni"; | |
| pinctrl-1 = <0x2aa>; | |
| status = "disabled"; | |
| reg = <0xa88000 0x4000>; | |
| phandle = <0x5b3>; | |
| dmas = <0x2a4 0x00 0x02 0x03 0x40 0x00 0x2a4 0x01 0x02 0x03 0x40 0x00>; | |
| }; | |
| cti@601b000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti11"; | |
| compatible = "arm,primecell"; | |
| reg = <0x601b000 0x1000>; | |
| phandle = <0x523>; | |
| }; | |
| tpdm@684c000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-tpdm-prng"; | |
| compatible = "arm,primecell"; | |
| reg = <0x684c000 0x1000>; | |
| phandle = <0x4ef>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x1ca>; | |
| phandle = <0x1c5>; | |
| }; | |
| }; | |
| }; | |
| jtagmm@7740000 { | |
| clock-names = "core_clk"; | |
| reg-names = "etm-base"; | |
| clocks = <0x49 0x00>; | |
| compatible = "qcom,jtagv8-mm"; | |
| qcom,coresight-jtagmm-cpu = <0x14>; | |
| reg = <0x7740000 0x1000>; | |
| phandle = <0x359>; | |
| }; | |
| rsc@18200000 { | |
| reg-names = "drv-0\0drv-1\0drv-2"; | |
| interrupts = <0x00 0x03 0x04 0x00 0x04 0x04 0x00 0x05 0x04>; | |
| label = "apps_rsc"; | |
| qcom,drv-id = <0x02>; | |
| compatible = "qcom,rpmh-rsc"; | |
| qcom,tcs-offset = <0xd00>; | |
| reg = <0x18200000 0x10000 0x18210000 0x10000 0x18220000 0x10000>; | |
| phandle = <0x37a>; | |
| qcom,tcs-config = <0x02 0x02 0x00 0x03 0x01 0x03 0x03 0x01>; | |
| rpmh-regulator-lcxlvl { | |
| compatible = "qcom,rpmh-arc-regulator"; | |
| qcom,resource-name = "lcx.lvl"; | |
| regulator-pm8150-l11-level { | |
| regulator-max-microvolt = <0xffff>; | |
| regulator-min-microvolt = <0x10>; | |
| regulator-name = "pm8150_l11_level"; | |
| qcom,init-voltage-level = <0x10>; | |
| qcom,set = <0x03>; | |
| phandle = <0x91>; | |
| }; | |
| }; | |
| rpmh-regulator-ldoa15 { | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoa15"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm8150-l15 { | |
| regulator-max-microvolt = <0x1b7740>; | |
| qcom,init-mode = <0x02>; | |
| qcom,init-voltage = <0x1b7740>; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-name = "pm8150_l15"; | |
| qcom,set = <0x03>; | |
| phandle = <0xaf>; | |
| }; | |
| }; | |
| rpmh-regulator-smpa5 { | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "smpa5"; | |
| regulator-pm8150-s5 { | |
| regulator-max-microvolt = <0x1f20c0>; | |
| qcom,init-voltage = <0x1bd500>; | |
| regulator-min-microvolt = <0x1bd500>; | |
| regulator-name = "pm8150_s5"; | |
| qcom,set = <0x03>; | |
| phandle = <0xaa>; | |
| }; | |
| }; | |
| rpmh-regulator-ldoc8 { | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoc8"; | |
| regulator-pm8150a-l8 { | |
| regulator-max-microvolt = <0x1b7740>; | |
| qcom,init-voltage = <0x1b7740>; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-name = "pm8150a_l8"; | |
| qcom,set = <0x03>; | |
| phandle = <0x2c8>; | |
| }; | |
| }; | |
| rpmh-regulator-smpf1 { | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "smpf1"; | |
| regulator-pm8009-s1 { | |
| regulator-max-microvolt = <0x124f80>; | |
| qcom,init-voltage = <0x124f80>; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-name = "pm8009_s1"; | |
| qcom,set = <0x03>; | |
| phandle = <0x38c>; | |
| }; | |
| }; | |
| qcom,rpmhclk { | |
| #clock-cells = <0x01>; | |
| compatible = "qcom,kona-rpmh-clk"; | |
| phandle = <0x15>; | |
| }; | |
| rpmh-regulator-ldof6 { | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldof6"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm8009-l6 { | |
| regulator-max-microvolt = <0x2dc6c0>; | |
| qcom,init-mode = <0x02>; | |
| qcom,init-voltage = <0x2ab980>; | |
| regulator-min-microvolt = <0x2ab980>; | |
| regulator-name = "pm8009_l6"; | |
| qcom,set = <0x03>; | |
| phandle = <0x392>; | |
| }; | |
| }; | |
| rpmh-regulator-ldoa13 { | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoa13"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm8150-l13 { | |
| regulator-max-microvolt = <0x2de600>; | |
| qcom,init-mode = <0x02>; | |
| qcom,init-voltage = <0x2de600>; | |
| regulator-min-microvolt = <0x2de600>; | |
| regulator-name = "pm8150_l13"; | |
| qcom,set = <0x03>; | |
| phandle = <0x37f>; | |
| }; | |
| }; | |
| rpmh-regulator-ldoc10 { | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoc10"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm8150a-l10 { | |
| regulator-max-microvolt = <0x328980>; | |
| qcom,init-mode = <0x02>; | |
| qcom,init-voltage = <0x2dc6c0>; | |
| regulator-min-microvolt = <0x2dc6c0>; | |
| regulator-name = "pm8150a_l10"; | |
| qcom,set = <0x03>; | |
| phandle = <0x337>; | |
| }; | |
| }; | |
| rpmh-regulator-ldoc6 { | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoc6"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm8150a-l6 { | |
| regulator-max-microvolt = <0x2d2a80>; | |
| qcom,init-mode = <0x02>; | |
| qcom,init-voltage = <0x1b7740>; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-name = "pm8150a_l6"; | |
| qcom,set = <0x03>; | |
| phandle = <0x388>; | |
| }; | |
| }; | |
| rpmh-regulator-ldof4 { | |
| qcom,mode-threshold-currents = <0x00 0x01>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldof4"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm8009-l4 { | |
| regulator-max-microvolt = <0x13e5c0>; | |
| qcom,init-mode = <0x02>; | |
| qcom,init-voltage = <0x124f80>; | |
| regulator-min-microvolt = <0x10b940>; | |
| regulator-name = "pm8009_l4"; | |
| qcom,set = <0x03>; | |
| phandle = <0x390>; | |
| }; | |
| }; | |
| rpmh-regulator-ebilvl { | |
| compatible = "qcom,rpmh-arc-regulator"; | |
| qcom,resource-name = "ebi.lvl"; | |
| regulator-pm8150a-s6-level { | |
| regulator-max-microvolt = <0xffff>; | |
| regulator-min-microvolt = <0x10>; | |
| regulator-name = "pm8150a_s6_level"; | |
| qcom,init-voltage-level = <0x10>; | |
| qcom,set = <0x03>; | |
| phandle = <0x382>; | |
| }; | |
| }; | |
| rpmh-regulator-cxlvl { | |
| pm8150_s3_level-parent-supply = <0x6a>; | |
| compatible = "qcom,rpmh-arc-regulator"; | |
| qcom,resource-name = "cx.lvl"; | |
| pm8150_s3_level_ao-parent-supply = <0x7b>; | |
| proxy-supply = <0x7a>; | |
| regulator-pm8150-s3-level { | |
| regulator-max-microvolt = <0xffff>; | |
| regulator-min-microvolt = <0x10>; | |
| regulator-name = "pm8150_s3_level"; | |
| qcom,init-voltage-level = <0x10>; | |
| qcom,set = <0x03>; | |
| phandle = <0x67>; | |
| qcom,min-dropout-voltage-level = <0xffffffff>; | |
| }; | |
| regulator-pm8150-s3-level-ao { | |
| regulator-max-microvolt = <0xffff>; | |
| regulator-min-microvolt = <0x10>; | |
| regulator-name = "pm8150_s3_level_ao"; | |
| qcom,init-voltage-level = <0x10>; | |
| qcom,set = <0x01>; | |
| phandle = <0x68>; | |
| qcom,min-dropout-voltage-level = <0xffffffff>; | |
| }; | |
| regulator-pm8150-s3-mmcx-sup-level { | |
| regulator-max-microvolt = <0xffff>; | |
| regulator-min-microvolt = <0x30>; | |
| regulator-name = "pm8150_s3_mmcx_sup_level"; | |
| qcom,init-voltage-level = <0x30>; | |
| qcom,proxy-consumer-enable; | |
| qcom,set = <0x03>; | |
| phandle = <0x7a>; | |
| qcom,proxy-consumer-voltage = <0x180 0xffff>; | |
| }; | |
| }; | |
| rpmh-regulator-ldoa6 { | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoa6"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm8150-l6 { | |
| regulator-max-microvolt = <0x124f80>; | |
| qcom,init-mode = <0x02>; | |
| qcom,init-voltage = <0x124f80>; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-name = "pm8150_l6"; | |
| qcom,set = <0x03>; | |
| phandle = <0x37c>; | |
| }; | |
| }; | |
| rpmh-regulator-ldoc4 { | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoc4"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm8150a-l4 { | |
| regulator-max-microvolt = <0x2ab980>; | |
| qcom,init-mode = <0x02>; | |
| qcom,init-voltage = <0x1b7740>; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-name = "pm8150a_l4"; | |
| qcom,set = <0x03>; | |
| phandle = <0x387>; | |
| }; | |
| }; | |
| rpmh-regulator-ldof2 { | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldof2"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm8009-l2 { | |
| regulator-max-microvolt = <0x124f80>; | |
| qcom,init-mode = <0x02>; | |
| qcom,init-voltage = <0x124f80>; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-name = "pm8009_l2"; | |
| qcom,set = <0x03>; | |
| phandle = <0x38e>; | |
| }; | |
| }; | |
| rpmh-regulator-smpc8 { | |
| qcom,mode-threshold-currents = <0x00 0x30d40>; | |
| qcom,regulator-type = "pmic5-hfsmps"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "smpc8"; | |
| qcom,supported-modes = <0x01 0x03>; | |
| regulator-pm8150a-s8 { | |
| regulator-max-microvolt = <0x155cc0>; | |
| qcom,init-mode = <0x01>; | |
| qcom,init-voltage = <0x124f80>; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-name = "pm8150a_s8"; | |
| qcom,set = <0x03>; | |
| phandle = <0xab>; | |
| }; | |
| }; | |
| rpmh-regulator-ldoc2 { | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoc2"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm8150a-l2 { | |
| regulator-max-microvolt = <0x13e5c0>; | |
| qcom,init-mode = <0x02>; | |
| qcom,init-voltage = <0x124f80>; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-name = "pm8150a_l2"; | |
| qcom,set = <0x03>; | |
| phandle = <0x385>; | |
| }; | |
| }; | |
| rpmh-regulator-ldoa18 { | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoa18"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm8150-l18 { | |
| regulator-max-microvolt = <0xe09c0>; | |
| qcom,init-mode = <0x02>; | |
| qcom,init-voltage = "\0\f5"; | |
| regulator-min-microvolt = "\0\f5"; | |
| regulator-name = "pm8150_l18"; | |
| qcom,set = <0x03>; | |
| phandle = <0x187>; | |
| }; | |
| }; | |
| system_pm { | |
| compatible = "qcom,system-pm"; | |
| }; | |
| rpmh-regulator-ldoa2 { | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoa2"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm8150-l2 { | |
| regulator-max-microvolt = <0x2ee000>; | |
| qcom,init-mode = <0x02>; | |
| qcom,init-voltage = <0x2ee000>; | |
| regulator-min-microvolt = <0x2ee000>; | |
| regulator-name = "pm8150_l2"; | |
| qcom,set = <0x03>; | |
| phandle = <0x186>; | |
| }; | |
| }; | |
| msm_bus_apps_rsc { | |
| compatible = "qcom,msm-bus-rsc"; | |
| qcom,msm-bus-id = <0x1f40>; | |
| }; | |
| rpmh-regulator-ldoa16 { | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoa16"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm8150-l16 { | |
| regulator-max-microvolt = <0x326a40>; | |
| qcom,init-mode = <0x02>; | |
| qcom,init-voltage = <0x2e2480>; | |
| regulator-min-microvolt = <0x2e2480>; | |
| regulator-name = "pm8150_l16"; | |
| qcom,set = <0x03>; | |
| phandle = <0x2c7>; | |
| }; | |
| }; | |
| rpmh-regulator-smpa6 { | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "smpa6"; | |
| regulator-pm8150-s6 { | |
| regulator-max-microvolt = <0x113640>; | |
| qcom,init-voltage = <0x927c0>; | |
| regulator-min-microvolt = <0x927c0>; | |
| regulator-name = "pm8150_s6"; | |
| qcom,set = <0x03>; | |
| phandle = <0xa7>; | |
| }; | |
| }; | |
| rpmh-regulator-ldoc9 { | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoc9"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm8150a-l9 { | |
| regulator-max-microvolt = <0x2d2a80>; | |
| qcom,init-mode = <0x02>; | |
| qcom,init-voltage = <0x294280>; | |
| regulator-min-microvolt = <0x294280>; | |
| regulator-name = "pm8150a_l9"; | |
| qcom,set = <0x03>; | |
| phandle = <0x38a>; | |
| }; | |
| }; | |
| rpmh-regulator-bobc1 { | |
| qcom,mode-threshold-currents = <0x00 0xf4240 0x1e8480>; | |
| qcom,regulator-type = "pmic5-bob"; | |
| qcom,send-defaults; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "bobc1"; | |
| qcom,supported-modes = <0x00 0x02 0x04>; | |
| regulator-pm8150a-bob-ao { | |
| regulator-max-microvolt = <0x3c6cc0>; | |
| qcom,init-mode = <0x03>; | |
| qcom,init-voltage = <0x2de600>; | |
| regulator-min-microvolt = <0x2de600>; | |
| regulator-name = "pm8150a_bob_ao"; | |
| qcom,set = <0x01>; | |
| phandle = <0x38b>; | |
| }; | |
| regulator-pm8150a-bob { | |
| regulator-max-microvolt = <0x3c6cc0>; | |
| qcom,init-mode = <0x00>; | |
| qcom,init-voltage = <0x328980>; | |
| regulator-min-microvolt = <0x2de600>; | |
| regulator-name = "pm8150a_bob"; | |
| qcom,set = <0x03>; | |
| phandle = <0x2c9>; | |
| }; | |
| }; | |
| rpmh-regulator-smpf2 { | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "smpf2"; | |
| regulator-pm8009-s2 { | |
| regulator-max-microvolt = <0x10c8e0>; | |
| qcom,init-voltage = <0x7d000>; | |
| regulator-min-microvolt = <0x7d000>; | |
| regulator-name = "pm8009_s2"; | |
| qcom,set = <0x03>; | |
| phandle = <0xa8>; | |
| }; | |
| }; | |
| rpmh-regulator-ldof7 { | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldof7"; | |
| regulator-pm8009-l7 { | |
| regulator-max-microvolt = <0x1b7740>; | |
| qcom,init-voltage = <0x1b7740>; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-name = "pm8009_l7"; | |
| qcom,set = <0x03>; | |
| phandle = <0x393>; | |
| }; | |
| }; | |
| rpmh-regulator-gfxlvl { | |
| compatible = "qcom,rpmh-arc-regulator"; | |
| qcom,resource-name = "gfx.lvl"; | |
| regulator-pm8150a-s1-level { | |
| regulator-max-microvolt = <0xffff>; | |
| regulator-min-microvolt = <0x10>; | |
| regulator-name = "pm8150a_s1_level"; | |
| qcom,init-voltage-level = <0x10>; | |
| qcom,set = <0x03>; | |
| phandle = <0x75>; | |
| }; | |
| }; | |
| rpmh-regulator-ldoa14 { | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoa14"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| proxy-supply = <0x7e>; | |
| regulator-pm8150-l14 { | |
| regulator-max-microvolt = <0x1cafc0>; | |
| qcom,init-mode = <0x02>; | |
| qcom,init-voltage = <0x1b7740>; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-name = "pm8150_l14"; | |
| qcom,proxy-consumer-enable; | |
| qcom,set = <0x03>; | |
| phandle = <0x7e>; | |
| qcom,proxy-consumer-current = <0xf230>; | |
| }; | |
| }; | |
| rpmh-regulator-smpa4 { | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "smpa4"; | |
| regulator-pm8150-s4 { | |
| regulator-max-microvolt = <0x1d4c00>; | |
| qcom,init-voltage = <0x1b7740>; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-name = "pm8150_s4"; | |
| qcom,set = <0x03>; | |
| phandle = <0xa9>; | |
| }; | |
| }; | |
| rpmh-regulator-ldoa9 { | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoa9"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| proxy-supply = <0x7d>; | |
| regulator-pm8150-l9 { | |
| regulator-max-microvolt = <0x124f80>; | |
| qcom,init-mode = <0x04>; | |
| qcom,init-voltage = <0x124f80>; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-name = "pm8150_l9"; | |
| qcom,proxy-consumer-enable; | |
| qcom,set = <0x03>; | |
| phandle = <0x7d>; | |
| qcom,proxy-consumer-current = <0x186a0>; | |
| }; | |
| }; | |
| rpmh-regulator-lmxlvl { | |
| compatible = "qcom,rpmh-arc-regulator"; | |
| qcom,resource-name = "lmx.lvl"; | |
| regulator-pm8150-l4-level { | |
| regulator-max-microvolt = <0xffff>; | |
| regulator-min-microvolt = <0x10>; | |
| regulator-name = "pm8150_l4_level"; | |
| qcom,init-voltage-level = <0x10>; | |
| qcom,set = <0x03>; | |
| phandle = <0x92>; | |
| }; | |
| }; | |
| rpmh-regulator-ldoc11 { | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoc11"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| proxy-supply = <0x80>; | |
| regulator-pm8150a-l11 { | |
| regulator-max-microvolt = <0x326a40>; | |
| qcom,init-mode = <0x02>; | |
| qcom,init-voltage = "\0/]"; | |
| regulator-min-microvolt = "\0/]"; | |
| regulator-name = "pm8150a_l11"; | |
| qcom,proxy-consumer-enable; | |
| qcom,set = <0x03>; | |
| phandle = <0x80>; | |
| qcom,proxy-consumer-current = <0xd13a8>; | |
| }; | |
| }; | |
| rpmh-regulator-ldoc7 { | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoc7"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm8150a-l7 { | |
| regulator-max-microvolt = "\0/]"; | |
| qcom,init-mode = <0x02>; | |
| qcom,init-voltage = <0x2b9440>; | |
| regulator-min-microvolt = <0x2b9440>; | |
| regulator-name = "pm8150a_l7"; | |
| qcom,set = <0x03>; | |
| phandle = <0x389>; | |
| }; | |
| }; | |
| rpmh-regulator-ldof5 { | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldof5"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm8009-l5 { | |
| regulator-max-microvolt = <0x2dc6c0>; | |
| qcom,init-mode = <0x02>; | |
| qcom,init-voltage = <0x2ab980>; | |
| regulator-min-microvolt = <0x2ab980>; | |
| regulator-name = "pm8009_l5"; | |
| qcom,set = <0x03>; | |
| phandle = <0x391>; | |
| }; | |
| }; | |
| rpmh-regulator-ldoa12 { | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoa12"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm8150-l12-so { | |
| regulator-max-microvolt = <0x1b7740>; | |
| qcom,init-mode = <0x02>; | |
| qcom,init-voltage = <0x1b7740>; | |
| regulator-min-microvolt = <0x1b7740>; | |
| qcom,init-enable = <0x00>; | |
| regulator-name = "pm8150_l12_so"; | |
| qcom,set = <0x02>; | |
| }; | |
| regulator-pm8150-l12-ao { | |
| regulator-max-microvolt = <0x1b7740>; | |
| qcom,init-mode = <0x02>; | |
| qcom,init-voltage = <0x1b7740>; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-name = "pm8150_l12_ao"; | |
| qcom,set = <0x01>; | |
| phandle = <0x18>; | |
| }; | |
| regulator-pm8150-l12 { | |
| regulator-max-microvolt = <0x1b7740>; | |
| qcom,init-mode = <0x02>; | |
| qcom,init-voltage = <0x1b7740>; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-name = "pm8150_l12"; | |
| qcom,set = <0x03>; | |
| phandle = <0x185>; | |
| }; | |
| }; | |
| rpmh-regulator-ldoa7 { | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoa7"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm8150-l7 { | |
| regulator-max-microvolt = <0x1b7740>; | |
| qcom,init-mode = <0x02>; | |
| qcom,init-voltage = <0x1a0040>; | |
| regulator-min-microvolt = <0x1a0040>; | |
| regulator-name = "pm8150_l7"; | |
| qcom,set = <0x03>; | |
| phandle = <0x37d>; | |
| }; | |
| }; | |
| rpmh-regulator-ldoc5 { | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoc5"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm8150a-l5 { | |
| regulator-max-microvolt = <0x2ab980>; | |
| qcom,init-mode = <0x02>; | |
| qcom,init-voltage = <0x1b7740>; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-name = "pm8150a_l5"; | |
| qcom,set = <0x03>; | |
| phandle = <0xac>; | |
| }; | |
| }; | |
| rpmh-regulator-ldof3 { | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldof3"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm8009-l3 { | |
| regulator-max-microvolt = <0x124f80>; | |
| qcom,init-mode = <0x02>; | |
| qcom,init-voltage = <0x124f80>; | |
| regulator-min-microvolt = <0x101d00>; | |
| regulator-name = "pm8009_l3"; | |
| qcom,set = <0x03>; | |
| phandle = <0x38f>; | |
| }; | |
| }; | |
| rpmh-regulator-ldoa10 { | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoa10"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm8150-l10 { | |
| regulator-max-microvolt = <0x2d2a80>; | |
| qcom,init-mode = <0x02>; | |
| qcom,init-voltage = <0x1b7740>; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-name = "pm8150_l10"; | |
| qcom,set = <0x03>; | |
| phandle = <0x37e>; | |
| }; | |
| }; | |
| rpmh-regulator-ldoa5 { | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoa5"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| proxy-supply = <0x7c>; | |
| regulator-pm8150-l5-so { | |
| regulator-max-microvolt = <0xd6d80>; | |
| qcom,init-mode = <0x02>; | |
| qcom,init-voltage = <0xd6d80>; | |
| regulator-min-microvolt = <0xd6d80>; | |
| qcom,init-enable = <0x00>; | |
| regulator-name = "pm8150_l5_so"; | |
| qcom,set = <0x02>; | |
| }; | |
| regulator-pm8150-l5 { | |
| regulator-max-microvolt = <0xd6d80>; | |
| qcom,init-mode = <0x04>; | |
| qcom,init-voltage = <0xd6d80>; | |
| regulator-min-microvolt = <0xd6d80>; | |
| regulator-name = "pm8150_l5"; | |
| qcom,proxy-consumer-enable; | |
| qcom,set = <0x03>; | |
| phandle = <0x7c>; | |
| qcom,proxy-consumer-current = <0x186a0>; | |
| }; | |
| regulator-pm8150-l5-ao { | |
| regulator-max-microvolt = <0xd6d80>; | |
| qcom,init-mode = <0x02>; | |
| qcom,init-voltage = <0xd6d80>; | |
| regulator-min-microvolt = <0xd6d80>; | |
| regulator-name = "pm8150_l5_ao"; | |
| qcom,set = <0x01>; | |
| phandle = <0x17>; | |
| }; | |
| }; | |
| rpmh-regulator-mmcxlvl { | |
| pm8150a_s4_level-parent-supply = <0x7f>; | |
| compatible = "qcom,rpmh-arc-regulator"; | |
| qcom,resource-name = "mmcx.lvl"; | |
| pm8150a_s4_level_ao-parent-supply = <0x7b>; | |
| proxy-supply = <0x69>; | |
| regulator-pm8150a-s4-level { | |
| regulator-max-microvolt = <0xffff>; | |
| regulator-min-microvolt = <0x40>; | |
| regulator-name = "pm8150a_s4_level"; | |
| qcom,init-voltage-level = <0x40>; | |
| qcom,proxy-consumer-enable; | |
| qcom,set = <0x03>; | |
| phandle = <0x69>; | |
| qcom,proxy-consumer-voltage = <0x180 0xffff>; | |
| qcom,min-dropout-voltage-level = <0xffffffff>; | |
| }; | |
| regulator-pm8150a-s4-level-so { | |
| regulator-max-microvolt = <0xffff>; | |
| regulator-min-microvolt = <0x40>; | |
| regulator-name = "pm8150a_s4_level_so"; | |
| qcom,init-voltage-level = <0x40>; | |
| qcom,set = <0x02>; | |
| }; | |
| regulator-pm8150a-s4-level-ao { | |
| regulator-max-microvolt = <0xffff>; | |
| regulator-min-microvolt = <0x40>; | |
| regulator-name = "pm8150a_s4_level_ao"; | |
| qcom,init-voltage-level = <0x40>; | |
| qcom,set = <0x01>; | |
| phandle = <0x381>; | |
| qcom,min-dropout-voltage-level = <0xffffffff>; | |
| }; | |
| }; | |
| rpmh-regulator-mxlvl { | |
| compatible = "qcom,rpmh-arc-regulator"; | |
| qcom,resource-name = "mx.lvl"; | |
| pm8150a_s3_mmcx_sup_level-parent-supply = <0x7a>; | |
| regulator-pm8150a-s3-mmcx-sup-level { | |
| regulator-max-microvolt = <0xffff>; | |
| regulator-min-microvolt = <0x10>; | |
| regulator-name = "pm8150a_s3_mmcx_sup_level"; | |
| qcom,init-voltage-level = <0x10>; | |
| qcom,set = <0x03>; | |
| phandle = <0x7f>; | |
| }; | |
| regulator-pm8150a-s3-level-ao { | |
| regulator-max-microvolt = <0xffff>; | |
| regulator-min-microvolt = <0x10>; | |
| regulator-name = "pm8150a_s3_level_ao"; | |
| qcom,init-voltage-level = <0x10>; | |
| qcom,set = <0x01>; | |
| phandle = <0x7b>; | |
| }; | |
| regulator-pm8150a-s3-level { | |
| regulator-max-microvolt = <0xffff>; | |
| regulator-min-microvolt = <0x10>; | |
| regulator-name = "pm8150a_s3_level"; | |
| qcom,init-voltage-level = <0x10>; | |
| qcom,set = <0x03>; | |
| phandle = <0x6a>; | |
| }; | |
| }; | |
| rpmh-regulator-ldoc3 { | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoc3"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm8150a-l3 { | |
| regulator-max-microvolt = <0x124f80>; | |
| qcom,init-mode = <0x02>; | |
| qcom,init-voltage = "\0\f5"; | |
| regulator-min-microvolt = "\0\f5"; | |
| regulator-name = "pm8150a_l3"; | |
| qcom,set = <0x03>; | |
| phandle = <0x386>; | |
| }; | |
| }; | |
| rpmh-regulator-ldof1 { | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldof1"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm8009-l1 { | |
| regulator-max-microvolt = <0x124f80>; | |
| qcom,init-mode = <0x02>; | |
| qcom,init-voltage = <0x124f80>; | |
| regulator-min-microvolt = <0x10d880>; | |
| regulator-name = "pm8009_l1"; | |
| qcom,set = <0x03>; | |
| phandle = <0x38d>; | |
| }; | |
| }; | |
| rpmh-regulator-ldoa3 { | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoa3"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm8150-l3 { | |
| regulator-max-microvolt = <0xe38a0>; | |
| qcom,init-mode = <0x02>; | |
| qcom,init-voltage = <0xe2900>; | |
| regulator-min-microvolt = <0xe2900>; | |
| regulator-name = "pm8150_l3"; | |
| qcom,set = <0x03>; | |
| phandle = <0x37b>; | |
| }; | |
| }; | |
| rpmh-regulator-smpc7 { | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "smpc7"; | |
| regulator-pm8150a-s7 { | |
| regulator-max-microvolt = <0xf4240>; | |
| qcom,init-voltage = <0x54f60>; | |
| regulator-min-microvolt = <0x54f60>; | |
| regulator-name = "pm8150a_s7"; | |
| qcom,set = <0x03>; | |
| phandle = <0x383>; | |
| }; | |
| }; | |
| rpmh-regulator-ldoc1 { | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoc1"; | |
| regulator-pm8150a-l1 { | |
| regulator-max-microvolt = <0x1b7740>; | |
| qcom,init-voltage = <0x1b7740>; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-name = "pm8150a_l1"; | |
| qcom,set = <0x03>; | |
| phandle = <0x384>; | |
| }; | |
| }; | |
| rpmh-regulator-ldoa17 { | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| qcom,regulator-type = "pmic5-ldo"; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoa17"; | |
| qcom,supported-modes = <0x02 0x04>; | |
| regulator-pm8150-l17 { | |
| regulator-max-microvolt = <0x2de600>; | |
| qcom,init-mode = <0x02>; | |
| qcom,init-voltage = <0x261600>; | |
| regulator-min-microvolt = <0x261600>; | |
| regulator-name = "pm8150_l17"; | |
| qcom,set = <0x03>; | |
| phandle = <0x380>; | |
| }; | |
| }; | |
| }; | |
| qcom,msm-dai-tdm-sec-tx { | |
| qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
| qcom,msm-cpudai-tdm-data-out = <0x00>; | |
| qcom,msm-cpudai-tdm-data-delay = <0x01>; | |
| qcom,msm-cpudai-tdm-group-port-id = <0x9011>; | |
| qcom,msm-cpudai-tdm-group-num-ports = <0x01>; | |
| qcom,msm-cpudai-tdm-invert-sync = <0x01>; | |
| compatible = "qcom,msm-dai-tdm"; | |
| qcom,msm-cpudai-tdm-group-id = <0x9111>; | |
| phandle = <0x5e9>; | |
| qcom,msm-cpudai-tdm-sync-src = <0x01>; | |
| qcom,msm-cpudai-tdm-clk-internal = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-mode = <0x01>; | |
| qcom,msm-dai-q6-tdm-sec-tx-0 { | |
| qcom,msm-cpudai-tdm-dev-id = <0x9011>; | |
| qcom,msm-cpudai-tdm-data-align = <0x00>; | |
| compatible = "qcom,msm-dai-q6-tdm"; | |
| phandle = <0x30c>; | |
| }; | |
| }; | |
| qcom,msm-pcm-loopback-low-latency { | |
| qcom,msm-pcm-loopback-low-latency; | |
| compatible = "qcom,msm-pcm-loopback"; | |
| phandle = <0x5cf>; | |
| }; | |
| qcom,smp2p-npu { | |
| qcom,local-pid = <0x00>; | |
| interrupts = <0x07 0x02 0x01>; | |
| interrupt-parent = <0x8a>; | |
| qcom,remote-pid = <0x0a>; | |
| compatible = "qcom,smp2p"; | |
| mboxes = <0x3f 0x07 0x02>; | |
| qcom,smem = <0x269 0x268>; | |
| slave-kernel { | |
| qcom,entry-name = "slave-kernel"; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x4d9>; | |
| interrupt-controller; | |
| }; | |
| master-kernel { | |
| qcom,entry-name = "master-kernel"; | |
| #qcom,smem-state-cells = <0x01>; | |
| phandle = <0x9d>; | |
| }; | |
| }; | |
| secbootfuse@0x7805E8 { | |
| reg-names = "sec-boot-base"; | |
| compatible = "qcom,sec-boot-fuse"; | |
| reg = <0x7805e8 0x04>; | |
| phandle = <0x351>; | |
| }; | |
| spi@88c000 { | |
| pinctrl-names = "default\0sleep"; | |
| #address-cells = <0x01>; | |
| pinctrl-0 = <0x2d8>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| reg-names = "se_phys"; | |
| interrupts = <0x00 0x249 0x04>; | |
| clocks = <0x16 0x7e 0x16 0x88 0x16 0x89>; | |
| #size-cells = <0x00>; | |
| qcom,wrapper-core = <0x2bf>; | |
| spi-max-frequency = <0x2faf080>; | |
| dma-names = "tx\0rx"; | |
| compatible = "qcom,spi-geni"; | |
| pinctrl-1 = <0x2d9>; | |
| status = "disabled"; | |
| reg = <0x88c000 0x4000>; | |
| phandle = <0x5c9>; | |
| dmas = <0x2c2 0x00 0x03 0x01 0x40 0x00 0x2c2 0x01 0x03 0x01 0x40 0x00>; | |
| }; | |
| syscon@3d91008 { | |
| compatible = "syscon"; | |
| reg = <0x3d91008 0x04>; | |
| phandle = <0x74>; | |
| }; | |
| qcom,csiphy@ac6e000 { | |
| clock-names = "cphy_rx_clk_src\0csiphy2_clk\0csi2phytimer_clk_src\0csi2phytimer_clk"; | |
| reg-names = "csiphy"; | |
| reg-cam-base = <0x6e000>; | |
| csi-vdd-voltage = <0x124f80>; | |
| cell-index = <0x02>; | |
| interrupts = <0x00 0x1df 0x01>; | |
| clocks = <0x6d 0x0e 0x6d 0x1d 0x6d 0x14 0x6d 0x13>; | |
| gdscr-supply = <0x253>; | |
| clock-cntl-level = "turbo"; | |
| compatible = "qcom,csiphy-v1.2.1\0qcom,csiphy"; | |
| src-clock-name = "csi2phytimer_clk_src"; | |
| mipi-csi-vdd-supply = <0x7d>; | |
| status = "ok"; | |
| interrupt-names = "csiphy"; | |
| reg = <0xac6e000 0x2000>; | |
| regulator-names = "gdscr\0refgen"; | |
| phandle = <0x55f>; | |
| refgen-supply = <0xb4>; | |
| clock-rates = <0x17d78400 0x00 0x11e1a300 0x00>; | |
| }; | |
| qcom,cam-cdm-intf { | |
| cdm-client-names = "vfe\0jpegdma\0jpegenc\0fd"; | |
| num-hw-cdm = <0x03>; | |
| cell-index = <0x00>; | |
| label = "cam-cdm-intf"; | |
| compatible = "qcom,cam-cdm-intf"; | |
| status = "ok"; | |
| }; | |
| spi@980000 { | |
| pinctrl-names = "default\0sleep"; | |
| #address-cells = <0x01>; | |
| pinctrl-0 = <0x291>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| reg-names = "se_phys"; | |
| interrupts = <0x00 0x259 0x04>; | |
| clocks = <0x16 0x58 0x16 0x84 0x16 0x85>; | |
| #size-cells = <0x00>; | |
| qcom,wrapper-core = <0x274>; | |
| spi-max-frequency = <0x2faf080>; | |
| dma-names = "tx\0rx"; | |
| compatible = "qcom,spi-geni"; | |
| pinctrl-1 = <0x292>; | |
| status = "okay"; | |
| reg = <0x980000 0x4000>; | |
| phandle = <0x5a8>; | |
| dmas = <0x280 0x00 0x00 0x01 0x40 0x00 0x280 0x01 0x00 0x01 0x40 0x00>; | |
| dbmd8_interface@0x0 { | |
| dma_min_buffer_size = <0x00>; | |
| spi-max-frequency = <0x7735940>; | |
| write-chunk-size = <0x8000>; | |
| compatible = "dspg,dbmd8-spi"; | |
| reg = <0x00>; | |
| phandle = <0x652>; | |
| read-chunk-size = <0x2000>; | |
| }; | |
| }; | |
| qcom,rpmh-master-stats@b221200 { | |
| compatible = "qcom,rpmh-master-stats-v1"; | |
| reg = <0xb221200 0x60>; | |
| }; | |
| tpdm@6b09000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-tpdm-swao-0"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6b09000 0x1000>; | |
| phandle = <0x4e3>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x19f>; | |
| phandle = <0x19d>; | |
| }; | |
| }; | |
| }; | |
| cti@6962000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| qcom,proxy-regs = "vddcx\0vdd"; | |
| vddcx-supply = <0x17c>; | |
| clock-names = "apb_pclk\0rbbmtimer_clk\0mem_clk\0mem_iface_clk\0gmu_clk\0gpu_cc_ahb\0l3_vote"; | |
| reg-names = "cti-base"; | |
| qcom,proxy-clks = "rbbmtimer_clk\0mem_clk\0mem_iface_clk\0gmu_clk\0gpu_cc_ahb\0l3_vote"; | |
| clocks = <0x49 0x00 0x6e 0x09 0x16 0x16 0x16 0x26 0x6e 0x03 0x6e 0x00 0x1ae 0x03>; | |
| coresight-name = "coresight-cti-gpu_cortex_m3"; | |
| vdd-supply = <0x1af>; | |
| compatible = "arm,primecell"; | |
| status = "disabled"; | |
| reg = <0x6962000 0x1000>; | |
| regulator-names = "vddcx\0vdd"; | |
| phandle = <0x530>; | |
| }; | |
| qcom,gdsc@abf0c98 { | |
| clock-names = "ahb_clk"; | |
| qcom,msm-bus,name = "mvs1c_gdsc_ahb"; | |
| parent-supply = <0x69>; | |
| qcom,retain-regs; | |
| clocks = <0x16 0xcd>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| regulator-name = "mvs1c_gdsc"; | |
| vdd_parent-supply = <0x69>; | |
| compatible = "qcom,gdsc"; | |
| reg = <0xabf0c98 0x04>; | |
| phandle = <0x32f>; | |
| qcom,msm-bus,vectors-KBps = <0x01 0x254 0x00 0x00 0x01 0x254 0x00 0x01>; | |
| }; | |
| qcom,mdss_dsi_ctrl1@ae96000 { | |
| clock-names = "byte_clk\0byte_clk_rcg\0byte_intf_clk\0pixel_clk\0pixel_clk_rcg\0esc_clk"; | |
| reg-names = "dsi_ctrl\0disp_cc_base"; | |
| cell-index = <0x01>; | |
| interrupts = <0x05 0x00>; | |
| clocks = <0x6c 0x06 0x6c 0x07 0x6c 0x09 0x6c 0x30 0x6c 0x31 0x6c 0x28>; | |
| interrupt-parent = <0x24c>; | |
| label = "dsi-ctrl-1"; | |
| vdda-1p2-supply = <0x7d>; | |
| compatible = "qcom,dsi-ctrl-hw-v2.4"; | |
| frame-threshold-time-us = <0x320>; | |
| reg = <0xae96000 0x400 0xaf08000 0x04>; | |
| phandle = <0x558>; | |
| refgen-supply = <0xb4>; | |
| qcom,ctrl-supply-entries { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,ctrl-supply-entry@0 { | |
| qcom,supply-disable-load = <0x00>; | |
| qcom,supply-enable-load = <0x684c>; | |
| qcom,supply-name = "vdda-1p2"; | |
| qcom,supply-max-voltage = <0x124f80>; | |
| reg = <0x00>; | |
| qcom,supply-min-voltage = <0x124f80>; | |
| }; | |
| }; | |
| qcom,core-supply-entries { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,core-supply-entry@0 { | |
| qcom,supply-disable-load = <0x00>; | |
| qcom,supply-enable-load = <0x00>; | |
| qcom,supply-name = "refgen"; | |
| qcom,supply-max-voltage = <0x00>; | |
| reg = <0x00>; | |
| qcom,supply-min-voltage = <0x00>; | |
| }; | |
| }; | |
| }; | |
| timer@17c20000 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| clock-frequency = <0x124f800>; | |
| compatible = "arm,armv7-timer-mem"; | |
| ranges; | |
| reg = <0x17c20000 0x1000>; | |
| phandle = <0x34f>; | |
| frame@17c2b000 { | |
| interrupts = <0x00 0x0d 0x04>; | |
| frame-number = <0x05>; | |
| status = "disabled"; | |
| reg = <0x17c2b000 0x1000>; | |
| }; | |
| frame@17c25000 { | |
| interrupts = <0x00 0x0a 0x04>; | |
| frame-number = <0x02>; | |
| status = "disabled"; | |
| reg = <0x17c25000 0x1000>; | |
| }; | |
| frame@17c2d000 { | |
| interrupts = <0x00 0x0e 0x04>; | |
| frame-number = <0x06>; | |
| status = "disabled"; | |
| reg = <0x17c2d000 0x1000>; | |
| }; | |
| frame@17c27000 { | |
| interrupts = <0x00 0x0b 0x04>; | |
| frame-number = <0x03>; | |
| status = "disabled"; | |
| reg = <0x17c27000 0x1000>; | |
| }; | |
| frame@17c21000 { | |
| interrupts = <0x00 0x08 0x04 0x00 0x06 0x04>; | |
| frame-number = <0x00>; | |
| reg = <0x17c21000 0x1000 0x17c22000 0x1000>; | |
| }; | |
| frame@17c29000 { | |
| interrupts = <0x00 0x0c 0x04>; | |
| frame-number = <0x04>; | |
| status = "disabled"; | |
| reg = <0x17c29000 0x1000>; | |
| }; | |
| frame@17c23000 { | |
| interrupts = <0x00 0x09 0x04>; | |
| frame-number = <0x01>; | |
| status = "disabled"; | |
| reg = <0x17c23000 0x1000>; | |
| }; | |
| }; | |
| funnel@6c44000 { | |
| arm,primecell-periphid = <0xbb908>; | |
| qcom,proxy-regs = "vdd\0vdd_cx"; | |
| clock-names = "apb_pclk\0gcc_npu_axi_clk\0gcc_npu_cfg_ahb_clk\0npu_cc_xo_clk\0npu_core_clk\0npu_core_clk_src\0npu_cc_atb_clk"; | |
| reg-names = "funnel-base"; | |
| qcom,proxy-clks = "gcc_npu_axi_clk\0gcc_npu_cfg_ahb_clk\0npu_cc_xo_clk\0npu_core_clk\0npu_core_clk_src\0npu_cc_atb_clk"; | |
| clocks = <0x49 0x00 0x16 0x28 0x16 0x2b 0x55 0x28 0x55 0x0d 0x55 0x0e 0x55 0x00>; | |
| coresight-name = "coresight-funnel-npu"; | |
| vdd-supply = <0x1de>; | |
| compatible = "arm,primecell"; | |
| reg = <0x6c44000 0x1000>; | |
| regulator-names = "vdd\0vdd_cx"; | |
| phandle = <0x503>; | |
| vdd_cx-supply = <0x67>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x21a>; | |
| phandle = <0x1dc>; | |
| }; | |
| }; | |
| port@3 { | |
| reg = <0x02>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x21d>; | |
| phandle = <0x1e1>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x00>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x21b>; | |
| phandle = <0x1df>; | |
| }; | |
| }; | |
| port@4 { | |
| reg = <0x03>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x21e>; | |
| phandle = <0x237>; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x01>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x21c>; | |
| phandle = <0x1e0>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,cam_smmu { | |
| compatible = "qcom,msm-cam-smmu"; | |
| status = "ok"; | |
| msm_cam_smmu_ife { | |
| iommus = <0x47 0x800 0x400 0x47 0x801 0x400 0x47 0x840 0x400 0x47 0x841 0x400 0x47 0xc00 0x400 0x47 0xc01 0x400 0x47 0xc40 0x400 0x47 0xc41 0x400>; | |
| label = "ife"; | |
| compatible = "qcom,msm-cam-smmu-cb"; | |
| qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; | |
| iova-mem-map { | |
| phandle = <0x56d>; | |
| iova-mem-region-io { | |
| iova-region-len = <0xd8c00000>; | |
| iova-region-name = "io"; | |
| status = "ok"; | |
| iova-region-id = <0x03>; | |
| iova-region-start = "\a@\0"; | |
| }; | |
| }; | |
| }; | |
| msm_cam_smmu_cpas_cdm { | |
| iommus = <0x47 0x20c0 0x400 0x47 0x24c0 0x400>; | |
| label = "cpas-cdm0"; | |
| compatible = "qcom,msm-cam-smmu-cb"; | |
| qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; | |
| iova-mem-map { | |
| phandle = <0x570>; | |
| iova-mem-region-io { | |
| iova-region-len = <0xd8c00000>; | |
| iova-region-name = "io"; | |
| status = "ok"; | |
| iova-region-id = <0x03>; | |
| iova-region-start = "\a@\0"; | |
| }; | |
| }; | |
| }; | |
| msm_cam_smmu_fd { | |
| iommus = <0x47 0x2080 0x400 0x47 0x2480 0x400>; | |
| label = "fd"; | |
| compatible = "qcom,msm-cam-smmu-cb"; | |
| qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; | |
| iova-mem-map { | |
| phandle = <0x571>; | |
| iova-mem-region-io { | |
| iova-region-len = <0xd8c00000>; | |
| iova-region-name = "io"; | |
| status = "ok"; | |
| iova-region-id = <0x03>; | |
| iova-region-start = "\a@\0"; | |
| }; | |
| }; | |
| }; | |
| msm_cam_smmu_icp { | |
| iommus = <0x47 0x20e2 0x400 0x47 0x24e2 0x400 0x47 0x2000 0x400 0x47 0x2001 0x400 0x47 0x2400 0x400 0x47 0x2401 0x400 0x47 0x2060 0x400 0x47 0x2061 0x400 0x47 0x2460 0x400 0x47 0x2461 0x400 0x47 0x2020 0x400 0x47 0x2021 0x400 0x47 0x2420 0x400 0x47 0x2421 0x400>; | |
| iova-region-discard = <0xdff00000 0x300000>; | |
| label = "icp"; | |
| compatible = "qcom,msm-cam-smmu-cb"; | |
| qcom,iommu-dma-addr-pool = <0x10c00000 0xee300000>; | |
| iova-mem-map { | |
| phandle = <0x56f>; | |
| iova-mem-qdss-region { | |
| iova-region-len = <0x100000>; | |
| qdss-phy-addr = <0x16790000>; | |
| iova-region-name = "qdss"; | |
| status = "ok"; | |
| iova-region-id = <0x05>; | |
| iova-region-start = <0x10b00000>; | |
| }; | |
| iova-mem-region-secondary-heap { | |
| iova-region-len = <0x100000>; | |
| iova-region-name = "secheap"; | |
| status = "ok"; | |
| iova-region-id = <0x04>; | |
| iova-region-start = <0x10a00000>; | |
| }; | |
| iova-mem-region-firmware { | |
| iova-region-len = <0x500000>; | |
| iova-region-name = "firmware"; | |
| status = "ok"; | |
| iova-region-id = <0x00>; | |
| iova-region-start = <0x00>; | |
| }; | |
| iova-mem-region-io { | |
| iova-region-len = <0xee300000>; | |
| iova-region-discard = <0xdff00000 0x300000>; | |
| iova-region-name = "io"; | |
| status = "ok"; | |
| iova-region-id = <0x03>; | |
| iova-region-start = <0x10c00000>; | |
| }; | |
| iova-mem-region-shared { | |
| iova-region-len = "\t`\0"; | |
| iova-region-name = "shared"; | |
| status = "ok"; | |
| iova-region-id = <0x01>; | |
| iova-region-start = "\a@\0"; | |
| }; | |
| }; | |
| }; | |
| msm_cam_smmu_jpeg { | |
| iommus = <0x47 0x2040 0x400 0x47 0x2440 0x400>; | |
| label = "jpeg"; | |
| compatible = "qcom,msm-cam-smmu-cb"; | |
| qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; | |
| iova-mem-map { | |
| phandle = <0x56e>; | |
| iova-mem-region-io { | |
| iova-region-len = <0xd8c00000>; | |
| iova-region-name = "io"; | |
| status = "ok"; | |
| iova-region-id = <0x03>; | |
| iova-region-start = "\a@\0"; | |
| }; | |
| }; | |
| }; | |
| msm_cam_smmu_secure { | |
| qcom,secure-cb; | |
| label = "cam-secure"; | |
| compatible = "qcom,msm-cam-smmu-cb"; | |
| }; | |
| msm_cam_icp_fw { | |
| memory-region = <0x25c>; | |
| label = "icp"; | |
| compatible = "qcom,msm-cam-smmu-fw-dev"; | |
| }; | |
| }; | |
| qcom,gpi-dma@800000 { | |
| iommus = <0x47 0x76 0x00>; | |
| qcom,gpi-ee-offset = <0x6000>; | |
| qcom,gpii-mask = <0x3f>; | |
| qcom,smmu-cfg = <0x01>; | |
| reg-names = "gpi-top"; | |
| interrupts = <0x00 0x24c 0x04 0x00 0x24d 0x04 0x00 0x24e 0x04 0x00 0x24f 0x04 0x00 0x250 0x04 0x00 0x251 0x04 0x00 0x252 0x04 0x00 0x253 0x04 0x00 0x254 0x04 0x00 0x255 0x04>; | |
| qcom,ev-factor = <0x02>; | |
| compatible = "qcom,gpi-dma"; | |
| status = "ok"; | |
| qcom,iommu-dma-addr-pool = <0x100000 0x100000>; | |
| qcom,max-num-gpii = <0x0a>; | |
| reg = <0x800000 0x70000>; | |
| phandle = <0x2c2>; | |
| #dma-cells = <0x05>; | |
| }; | |
| ipcc-self-ping-adsp { | |
| interrupts-extended = <0x8a 0x03 0x03 0x04>; | |
| compatible = "qcom,ipcc-self-ping"; | |
| phandle = <0x610>; | |
| mboxes = <0x8a 0x03 0x03>; | |
| }; | |
| tpdm@6980000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-tpdm-turing"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6980000 0x1000>; | |
| phandle = <0x1f1>; | |
| qcom,msr-fix-req; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x223>; | |
| phandle = <0x220>; | |
| }; | |
| }; | |
| }; | |
| qcom,smp2p_interrupt_rdbg_5_out { | |
| qcom,smem-state-names = "rdbg-smp2p-out"; | |
| compatible = "qcom,smp2p-interrupt-rdbg-5-out"; | |
| qcom,smem-states = <0x251 0x00>; | |
| }; | |
| qcom,npu-staticmap-mon { | |
| clock-names = "cal_hm0_clk"; | |
| clocks = <0x55 0x04>; | |
| qcom,core-dev-table = <0x00 0x00 0x493e0 0x6b8 0x631f0 0xb71 0x82208 0x172b 0xb2390 0x1ae1 0xe09c0 0x1f2c 0xf4240 0x28c5>; | |
| qcom,dev_clk = "cal_hm0_clk"; | |
| compatible = "qcom,static-map"; | |
| phandle = <0x362>; | |
| qcom,target-dev = <0x54>; | |
| }; | |
| cti@7220000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| cpu = <0x0f>; | |
| coresight-name = "coresight-cti-cpu2"; | |
| compatible = "arm,primecell"; | |
| reg = <0x7220000 0x1000>; | |
| phandle = <0x52a>; | |
| }; | |
| syscon@182a0000 { | |
| compatible = "syscon"; | |
| reg = <0x182a0000 0x1c>; | |
| phandle = <0x6f>; | |
| }; | |
| qcom,cpu-llcc-ddr-bwmon@9091000 { | |
| reg-names = "base"; | |
| interrupts = <0x00 0x51 0x04>; | |
| compatible = "qcom,bimc-bwmon5"; | |
| qcom,hw-timer-hz = <0x124f800>; | |
| qcom,count-unit = <0x10000>; | |
| reg = <0x9091000 0x1000>; | |
| phandle = <0x35e>; | |
| qcom,target-dev = <0x4e>; | |
| }; | |
| ssc_etm0 { | |
| qcom,inst-id = <0x08>; | |
| coresight-name = "coresight-ssc-etm0"; | |
| compatible = "qcom,coresight-remote-etm"; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x236>; | |
| phandle = <0x197>; | |
| }; | |
| }; | |
| }; | |
| cti@6c09000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti-dlmm_cti0"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6c09000 0x1000>; | |
| phandle = <0x514>; | |
| }; | |
| qcom,ipcc@408000 { | |
| interrupts = <0x00 0xe5 0x04>; | |
| #mbox-cells = <0x02>; | |
| compatible = "qcom,ipcc"; | |
| #interrupt-cells = <0x03>; | |
| reg = <0x408000 0x1000>; | |
| phandle = <0x8a>; | |
| interrupt-controller; | |
| }; | |
| qcom,gdsc@16b004 { | |
| qcom,retain-regs; | |
| regulator-name = "pcie_0_gdsc"; | |
| compatible = "qcom,gdsc"; | |
| reg = <0x16b004 0x04>; | |
| phandle = <0x16b>; | |
| }; | |
| qcom,msm-dai-tdm-sec-rx { | |
| qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
| qcom,msm-cpudai-tdm-data-out = <0x00>; | |
| qcom,msm-cpudai-tdm-data-delay = <0x01>; | |
| qcom,msm-cpudai-tdm-group-port-id = <0x9010>; | |
| qcom,msm-cpudai-tdm-group-num-ports = <0x01>; | |
| qcom,msm-cpudai-tdm-invert-sync = <0x01>; | |
| compatible = "qcom,msm-dai-tdm"; | |
| qcom,msm-cpudai-tdm-group-id = <0x9110>; | |
| phandle = <0x5e8>; | |
| qcom,msm-cpudai-tdm-sync-src = <0x01>; | |
| qcom,msm-cpudai-tdm-clk-internal = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-mode = <0x01>; | |
| qcom,msm-dai-q6-tdm-sec-rx-0 { | |
| qcom,msm-cpudai-tdm-dev-id = <0x9010>; | |
| qcom,msm-cpudai-tdm-data-align = <0x00>; | |
| compatible = "qcom,msm-dai-q6-tdm"; | |
| phandle = <0x30b>; | |
| }; | |
| }; | |
| qcom,cc-debug { | |
| qcom,gpucc = <0x6e>; | |
| clock-names = "xo_clk_src"; | |
| clocks = <0x15 0x00>; | |
| #clock-cells = <0x01>; | |
| qcom,gcc = <0x16>; | |
| qcom,dispcc = <0x6c>; | |
| compatible = "qcom,kona-debugcc"; | |
| qcom,mccc = <0x70>; | |
| phandle = <0x373>; | |
| qcom,videocc = <0x6b>; | |
| qcom,npucc = <0x55>; | |
| qcom,apsscc = <0x6f>; | |
| qcom,camcc = <0x6d>; | |
| }; | |
| qcom,gdsc@3d9100c { | |
| parent-supply = <0x75>; | |
| qcom,retain-regs; | |
| domain-addr = <0x73>; | |
| regulator-name = "gpu_gx_gdsc"; | |
| vdd_parent-supply = <0x75>; | |
| qcom,reset-aon-logic; | |
| compatible = "qcom,gdsc"; | |
| reg = <0x3d9100c 0x04>; | |
| sw-reset = <0x74>; | |
| phandle = <0x1af>; | |
| qcom,skip-disable-before-sw-enable; | |
| }; | |
| qcom,csid-lite1@acdb400 { | |
| camss-supply = <0x253>; | |
| clock-control-debugfs = "true"; | |
| clock-names = "ife_csid_clk_src\0ife_csid_clk\0cphy_rx_clk_src\0ife_cphy_rx_clk\0ife_clk_src\0ife_lite_ahb\0ife_clk"; | |
| reg-names = "csid-lite"; | |
| reg-cam-base = <0xdb400>; | |
| cell-index = <0x03>; | |
| interrupts = <0x00 0x167 0x01>; | |
| clocks = <0x6d 0x41 0x6d 0x40 0x6d 0x0e 0x6d 0x3f 0x6d 0x3e 0x6d 0x3b 0x6d 0x3d>; | |
| clock-cntl-level = "lowsvs\0svs\0svs_l1\0turbo"; | |
| compatible = "qcom,csid-lite480"; | |
| src-clock-name = "ife_csid_clk_src"; | |
| status = "ok"; | |
| interrupt-names = "csid-lite"; | |
| reg = <0xacdb400 0x1000>; | |
| regulator-names = "camss"; | |
| phandle = <0x594>; | |
| clock-rates = <0x17d78400 0x00 0x00 0x00 0x17d78400 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x1c9c3800 0x00 0x00>; | |
| }; | |
| qcom,chd_gold { | |
| qcom,config-arr = <0x18040060 0x18050060 0x18060060 0x18070060>; | |
| label = "gold"; | |
| qcom,threshold-arr = <0x18040058 0x18050058 0x18060058 0x18070058>; | |
| compatible = "qcom,core-hang-detect"; | |
| }; | |
| spi@894000 { | |
| pinctrl-names = "default\0sleep"; | |
| #address-cells = <0x01>; | |
| pinctrl-0 = <0x2dc>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| reg-names = "se_phys"; | |
| interrupts = <0x00 0x24b 0x04>; | |
| clocks = <0x16 0x82 0x16 0x88 0x16 0x89>; | |
| #size-cells = <0x00>; | |
| qcom,wrapper-core = <0x2bf>; | |
| spi-max-frequency = <0x2faf080>; | |
| dma-names = "tx\0rx"; | |
| compatible = "qcom,spi-geni"; | |
| pinctrl-1 = <0x2dd>; | |
| status = "disabled"; | |
| reg = <0x894000 0x4000>; | |
| phandle = <0x5cb>; | |
| dmas = <0x2c2 0x00 0x05 0x01 0x40 0x00 0x2c2 0x01 0x05 0x01 0x40 0x00>; | |
| }; | |
| qcom,qsee_irq { | |
| syscon = <0x84>; | |
| interrupts = <0x00 0x15c 0x04 0x00 0x15d 0x04>; | |
| compatible = "qcom,kona-qsee-irq"; | |
| #interrupt-cells = <0x03>; | |
| interrupt-names = "sp_ipc0\0sp_ipc1"; | |
| phandle = <0x85>; | |
| interrupt-controller; | |
| }; | |
| funnel@6c39000 { | |
| arm,primecell-periphid = <0xbb908>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "funnel-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-funnel-dl-compute"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6c39000 0x1000>; | |
| phandle = <0x4f9>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x1da>; | |
| phandle = <0x202>; | |
| }; | |
| }; | |
| port@3 { | |
| reg = <0x03>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x1dd>; | |
| phandle = <0x1d3>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x00>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x1db>; | |
| phandle = <0x21f>; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x01>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x1dc>; | |
| phandle = <0x21a>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| tpda@69c1000 { | |
| arm,primecell-periphid = <0xbb969>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpda-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-tpda-dl-south"; | |
| qcom,dsb-elem-size = <0x00 0x40>; | |
| compatible = "arm,primecell"; | |
| qcom,tpda-atid = <0x4b>; | |
| reg = <0x69c1000 0x1000>; | |
| phandle = <0x4f6>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x1d5>; | |
| phandle = <0x1d4>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x00>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x1d6>; | |
| phandle = <0x1d7>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,dispcc@af00000 { | |
| #reset-cells = <0x01>; | |
| clock-names = "cfg_ahb_clk"; | |
| reg-names = "cc_base"; | |
| clocks = <0x16 0x18>; | |
| vdd_mm-supply = <0x69>; | |
| #clock-cells = <0x01>; | |
| compatible = "qcom,kona-dispcc\0syscon"; | |
| reg = <0xaf00000 0x20000>; | |
| phandle = <0x6c>; | |
| }; | |
| qcom,cpu4-cpu-ddr-qoslat { | |
| governor = "powersave"; | |
| compatible = "qcom,devfreq-qoslat"; | |
| phandle = <0x5f>; | |
| mboxes = <0x02 0x00>; | |
| operating-points-v2 = <0x56>; | |
| }; | |
| qcom,msm-dai-q6-dp1 { | |
| compatible = "qcom,msm-dai-q6-hdmi"; | |
| qcom,msm-dai-q6-dev-id = <0x01>; | |
| phandle = <0x2ee>; | |
| }; | |
| i2c@984000 { | |
| pinctrl-names = "default\0sleep"; | |
| #address-cells = <0x01>; | |
| pinctrl-0 = <0x283>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| interrupts = <0x00 0x25a 0x04>; | |
| clocks = <0x16 0x5a 0x16 0x84 0x16 0x85>; | |
| #size-cells = <0x00>; | |
| qcom,wrapper-core = <0x274>; | |
| dma-names = "tx\0rx"; | |
| compatible = "qcom,i2c-geni"; | |
| pinctrl-1 = <0x284>; | |
| status = "ok"; | |
| reg = <0x984000 0x4000>; | |
| phandle = <0x5a1>; | |
| dmas = <0x280 0x00 0x01 0x03 0x40 0x00 0x280 0x01 0x01 0x03 0x40 0x00>; | |
| qcom,clk-freq-out = <0xf4240>; | |
| ptp@60 { | |
| pinctrl-names = "mcu_pin"; | |
| pinctrl-0 = <0x4d8>; | |
| interrupts = <0x0e 0x2002>; | |
| interrupt-parent = <0x66>; | |
| vdd-supply = <0x2c7>; | |
| compatible = "hid-over-i2c"; | |
| post-power-on-delay-ms = <0x64>; | |
| reg = <0x60>; | |
| phandle = <0x744>; | |
| vddl-supply = <0x2c8>; | |
| hid-descr-addr = <0x01>; | |
| }; | |
| }; | |
| qcom,ipa_fws { | |
| qcom,pil-force-shutdown; | |
| memory-region = <0x87>; | |
| qcom,pas-id = <0x0f>; | |
| compatible = "qcom,pil-tz-generic"; | |
| qcom,firmware-name = "ipa_fws"; | |
| }; | |
| cache-controller@9200000 { | |
| reg-names = "llcc_base\0llcc_broadcast_base"; | |
| compatible = "qcom,llcc-v2"; | |
| reg = <0x9200000 0x1d0000 0x9600000 0x50000>; | |
| cap-based-alloc-and-pwr-collapse; | |
| }; | |
| qcom,aopclk { | |
| #clock-cells = <0x01>; | |
| qcom,clk-stop-bimc-log; | |
| compatible = "qcom,aop-qmp-clk"; | |
| phandle = <0x49>; | |
| mboxes = <0x02 0x00>; | |
| mbox-names = "qdss_clk"; | |
| }; | |
| funnel@7810000 { | |
| arm,primecell-periphid = <0xbb908>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "funnel-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-funnel-apss-merg"; | |
| compatible = "arm,primecell"; | |
| reg = <0x7810000 0x1000>; | |
| phandle = <0x546>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x238>; | |
| phandle = <0x1ad>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x00>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x239>; | |
| phandle = <0x243>; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x03>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x23a>; | |
| phandle = <0x208>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| cti@6018000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti8"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6018000 0x1000>; | |
| phandle = <0x520>; | |
| }; | |
| jtagmm@7040000 { | |
| clock-names = "core_clk"; | |
| reg-names = "etm-base"; | |
| clocks = <0x49 0x00>; | |
| compatible = "qcom,jtagv8-mm"; | |
| qcom,coresight-jtagmm-cpu = <0x0d>; | |
| reg = <0x7040000 0x1000>; | |
| phandle = <0x352>; | |
| }; | |
| hsphy@88e3000 { | |
| qcom,vdd-voltage-level = <0x00 0xd6d80 0xd6d80>; | |
| clock-names = "ref_clk_src"; | |
| reg-names = "hsusb_phy_base\0eud_enable_reg"; | |
| resets = <0x16 0x1b>; | |
| qcom,param-override-seq = <0x83 0x70>; | |
| clocks = <0x15 0x00>; | |
| vdd-supply = <0x7c>; | |
| compatible = "qcom,usb-hsphy-snps-femto"; | |
| reg = <0x88e3000 0x110 0x88e2000 0x04>; | |
| phandle = <0x183>; | |
| reset-names = "phy_reset"; | |
| vdda33-supply = <0x186>; | |
| vdda18-supply = <0x185>; | |
| }; | |
| gpu-opp-table { | |
| compatible = "operating-points-v2"; | |
| phandle = <0x607>; | |
| opp-290000000 { | |
| opp-microvolt = <0x40>; | |
| opp-hz = <0x00 0x11490c80>; | |
| }; | |
| opp-480000000 { | |
| opp-microvolt = <0xc0>; | |
| opp-hz = <0x00 0x1c9c3800>; | |
| }; | |
| opp-381000000 { | |
| opp-microvolt = <0x80>; | |
| opp-hz = <0x00 0x16b59940>; | |
| }; | |
| }; | |
| qcom,gdsc@af03000 { | |
| clock-names = "ahb_clk"; | |
| qcom,msm-bus,name = "mdss_core_gdsc_ahb"; | |
| parent-supply = <0x69>; | |
| qcom,support-hw-trigger; | |
| qcom,retain-regs; | |
| clocks = <0x16 0x18>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| regulator-name = "mdss_core_gdsc"; | |
| vdd_parent-supply = <0x69>; | |
| compatible = "qcom,gdsc"; | |
| qcom,proxy-consumer-enable; | |
| reg = <0xaf03000 0x04>; | |
| phandle = <0x71>; | |
| qcom,msm-bus,vectors-KBps = <0x01 0x24e 0x00 0x00 0x01 0x24e 0x00 0x01>; | |
| proxy-supply = <0x71>; | |
| }; | |
| ufsphy_mem@1d87000 { | |
| clock-names = "ref_clk_src\0ref_aux_clk"; | |
| reg-names = "phy_mem\0ufs_ice"; | |
| lanes-per-direction = <0x02>; | |
| clocks = <0x15 0x00 0x16 0xad>; | |
| vdda-phy-supply = <0x7c>; | |
| #phy-cells = <0x00>; | |
| vdda-pll-supply = <0x7d>; | |
| compatible = "qcom,ufs-phy-qmp-v4"; | |
| status = "ok"; | |
| vdda-phy-max-microamp = <0x15f2c>; | |
| reg = <0x1d87000 0xe00 0x1d90000 0x8000>; | |
| phandle = <0x77>; | |
| vdda-phy-always-on; | |
| vdda-pll-max-microamp = <0x4970>; | |
| }; | |
| funnel@6005000 { | |
| arm,primecell-periphid = <0xbb908>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "funnel-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-funnel-qatb"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6005000 0x1000>; | |
| phandle = <0x508>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x230>; | |
| phandle = <0x1a9>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x00>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x231>; | |
| phandle = <0x1b3>; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x03>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x232>; | |
| phandle = <0x1fe>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| cti@6e02000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti-ddr_dl_0_cti_1"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6e02000 0x1000>; | |
| phandle = <0x50d>; | |
| }; | |
| spi@99c000 { | |
| pinctrl-names = "default\0sleep"; | |
| #address-cells = <0x01>; | |
| pinctrl-0 = <0x29f>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| reg-names = "se_phys"; | |
| interrupts = <0x00 0x260 0x04>; | |
| clocks = <0x16 0x66 0x16 0x84 0x16 0x85>; | |
| #size-cells = <0x00>; | |
| qcom,wrapper-core = <0x274>; | |
| spi-max-frequency = <0x2faf080>; | |
| dma-names = "tx\0rx"; | |
| compatible = "qcom,spi-geni"; | |
| pinctrl-1 = <0x2a0>; | |
| status = "disabled"; | |
| reg = <0x99c000 0x4000>; | |
| phandle = <0x5af>; | |
| dmas = <0x280 0x00 0x07 0x01 0x40 0x00 0x280 0x01 0x07 0x01 0x40 0x00>; | |
| }; | |
| qcom,csiphy@ac70000 { | |
| clock-names = "cphy_rx_clk_src\0csiphy3_clk\0csi3phytimer_clk_src\0csi3phytimer_clk"; | |
| reg-names = "csiphy"; | |
| reg-cam-base = <0x70000>; | |
| csi-vdd-voltage = <0x124f80>; | |
| cell-index = <0x03>; | |
| interrupts = <0x00 0x1c0 0x01>; | |
| clocks = <0x6d 0x0e 0x6d 0x1e 0x6d 0x16 0x6d 0x15>; | |
| gdscr-supply = <0x253>; | |
| clock-cntl-level = "turbo"; | |
| compatible = "qcom,csiphy-v1.2.1\0qcom,csiphy"; | |
| src-clock-name = "csi3phytimer_clk_src"; | |
| mipi-csi-vdd-supply = <0x7d>; | |
| status = "ok"; | |
| interrupt-names = "csiphy"; | |
| reg = <0xac70000 0x2000>; | |
| regulator-names = "gdscr\0refgen"; | |
| phandle = <0x560>; | |
| refgen-supply = <0xb4>; | |
| clock-rates = <0x17d78400 0x00 0x11e1a300 0x00>; | |
| }; | |
| tpdm@78a0000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-tpdm-llm-silver"; | |
| compatible = "arm,primecell"; | |
| reg = <0x78a0000 0x1000>; | |
| phandle = <0x4fd>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x20d>; | |
| phandle = <0x209>; | |
| }; | |
| }; | |
| }; | |
| qcom,msm-voip-dsp { | |
| compatible = "qcom,msm-voip-dsp"; | |
| phandle = <0x2e3>; | |
| }; | |
| cti@6015000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti5"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6015000 0x1000>; | |
| phandle = <0x51d>; | |
| }; | |
| cti@6c43000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti-npu_dl_cti_1"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6c43000 0x1000>; | |
| phandle = <0x538>; | |
| }; | |
| rsc@af20000 { | |
| reg-names = "drv-0"; | |
| interrupts = <0x00 0x81 0x04>; | |
| label = "disp_rsc"; | |
| qcom,drv-id = <0x00>; | |
| compatible = "qcom,rpmh-rsc"; | |
| qcom,tcs-offset = <0x1c00>; | |
| reg = <0xaf20000 0x10000>; | |
| phandle = <0x394>; | |
| qcom,tcs-config = <0x02 0x00 0x00 0x01 0x01 0x01 0x03 0x00>; | |
| sde_rsc_rpmh { | |
| cell-index = <0x00>; | |
| compatible = "qcom,sde-rsc-rpmh"; | |
| }; | |
| msm_bus_disp_rsc { | |
| compatible = "qcom,msm-bus-rsc"; | |
| qcom,msm-bus-id = <0x1f41>; | |
| }; | |
| }; | |
| qcom,turing@8300000 { | |
| qcom,smem-state-names = "qcom,force-stop"; | |
| qcom,smem-id = <0x259>; | |
| qcom,sysmon-id = <0x07>; | |
| qcom,ssctl-instance-id = <0x17>; | |
| clock-names = "xo"; | |
| qcom,msm-bus,name = "pil-cdsp"; | |
| qcom,proxy-timeout-ms = <0x2710>; | |
| memory-region = <0x96>; | |
| clocks = <0x15 0x00>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| qcom,signal-aop; | |
| qcom,complete-ramdump; | |
| qcom,pas-id = <0x12>; | |
| interrupts-extended = <0x01 0x00 0x242 0x04 0x97 0x00 0x00 0x97 0x02 0x00 0x97 0x01 0x00 0x97 0x03 0x00>; | |
| compatible = "qcom,pil-tz-generic"; | |
| qcom,vdd_cx-uV-uA = <0x180 0x186a0>; | |
| interrupt-names = "qcom,wdog\0qcom,err-fatal\0qcom,proxy-unvote\0qcom,err-ready\0qcom,stop-ack"; | |
| reg = <0x8300000 0x100000>; | |
| qcom,smem-states = <0x98 0x00>; | |
| qcom,msm-bus,vectors-KBps = <0x9a 0x2756 0x00 0x00 0x9a 0x2756 0x00 0x01>; | |
| mboxes = <0x02 0x00>; | |
| vdd_cx-supply = <0x67>; | |
| qcom,proxy-clock-names = "xo"; | |
| qcom,proxy-reg-names = "vdd_cx"; | |
| qcom,firmware-name = "cdsp"; | |
| mbox-names = "cdsp-pil"; | |
| }; | |
| qcom,kgsl-iommu@3da0000 { | |
| clock-names = "gcc_gpu_memnoc_gfx\0gcc_gpu_snoc_dvm_gfx\0gpu_cc_ahb"; | |
| qcom,retention; | |
| clocks = <0x16 0x26 0x16 0x27 0x6e 0x00>; | |
| qcom,protect = <0xa0000 0xc000>; | |
| compatible = "qcom,kgsl-smmu-v2"; | |
| reg = <0x3da0000 0x10000>; | |
| phandle = <0x608>; | |
| qcom,hyp_secure_alloc; | |
| qcom,secure_align_mask = <0xfff>; | |
| gfx3d_user { | |
| iommus = <0x181 0x00 0x401>; | |
| label = "gfx3d_user"; | |
| compatible = "qcom,smmu-kgsl-cb"; | |
| phandle = <0x609>; | |
| qcom,gpu-offset = <0xa8000>; | |
| qcom,iommu-dma = "disabled"; | |
| }; | |
| gfx3d_secure { | |
| iommus = <0x181 0x02 0x400>; | |
| label = "gfx3d_secure"; | |
| compatible = "qcom,smmu-kgsl-cb"; | |
| phandle = <0x60a>; | |
| qcom,iommu-dma = "disabled"; | |
| }; | |
| }; | |
| spi@a8c000 { | |
| pinctrl-names = "default\0sleep"; | |
| #address-cells = <0x01>; | |
| pinctrl-0 = <0x2b6>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| reg-names = "se_phys"; | |
| interrupts = <0x00 0x164 0x04>; | |
| clocks = <0x16 0x70 0x16 0x86 0x16 0x87>; | |
| #size-cells = <0x00>; | |
| qcom,wrapper-core = <0x2a3>; | |
| spi-max-frequency = <0x2faf080>; | |
| dma-names = "tx\0rx"; | |
| compatible = "qcom,spi-geni"; | |
| pinctrl-1 = <0x2b7>; | |
| status = "disabled"; | |
| reg = <0xa8c000 0x4000>; | |
| phandle = <0x5ba>; | |
| dmas = <0x2a4 0x00 0x03 0x01 0x40 0x00 0x2a4 0x01 0x03 0x01 0x40 0x00>; | |
| }; | |
| tpdm@6e20000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-tpdm-ddr-ch13"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6e20000 0x1000>; | |
| phandle = <0x1ed>; | |
| qcom,msr-fix-req; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x22e>; | |
| phandle = <0x22c>; | |
| }; | |
| }; | |
| }; | |
| qcom,cpu0-cpugrp { | |
| qcom,cpulist = <0x0d 0x0e 0x0f 0x10>; | |
| compatible = "qcom,arm-memlat-cpugrp"; | |
| phandle = <0x363>; | |
| qcom,cpu0-cpu-l3-latmon { | |
| qcom,cachemiss-ev = <0x17>; | |
| qcom,core-dev-table = <0x493e0 0x11e1a300 0x62700 0x18085800 0x7e900 0x1ee62800 0xa8c00 0x249f0000 0xd7a00 0x3135a800 0x106800 0x36ee8000 0x11df00 0x3ca75800 0x148200 0x43852800 0x15ae00 0x493e0000 0x172500 0x4ef6d800 0x189c00 0x5a688800 0x1b8a00 0x60216000>; | |
| compatible = "qcom,arm-memlat-mon"; | |
| phandle = <0x364>; | |
| qcom,target-dev = <0x57>; | |
| }; | |
| qcom,cpu0-llcc-ddr-latmon { | |
| qcom,cachemiss-ev = <0x1000>; | |
| qcom,cpulist = <0x0d 0x0e 0x0f 0x10>; | |
| compatible = "qcom,arm-memlat-mon"; | |
| phandle = <0x366>; | |
| qcom,target-dev = <0x59>; | |
| ddr4-map { | |
| qcom,core-dev-table = <0x493e0 0x2fa 0xc0300 0x6b8 0x11df00 0x826 0x172500 0xb71 0x1b8a00 0xf27>; | |
| qcom,ddr-type = <0x07>; | |
| }; | |
| ddr5-map { | |
| qcom,core-dev-table = <0x493e0 0x2fa 0xc0300 0x6b8 0x11df00 0x826 0x172500 0xb71 0x1b8a00 0xf27>; | |
| qcom,ddr-type = <0x08>; | |
| }; | |
| }; | |
| qcom,cpu0-cpu-llcc-latmon { | |
| qcom,cachemiss-ev = <0x2a>; | |
| qcom,core-dev-table = <0x493e0 0x8f0 0xc0300 0x11e1 0x172500 0x1bc6 0x1b8a00 0x23c3>; | |
| compatible = "qcom,arm-memlat-mon"; | |
| phandle = <0x365>; | |
| qcom,target-dev = <0x58>; | |
| }; | |
| }; | |
| qcom,gdsc@10f004 { | |
| qcom,retain-regs; | |
| regulator-name = "usb30_prim_gdsc"; | |
| compatible = "qcom,gdsc"; | |
| reg = <0x10f004 0x04>; | |
| phandle = <0x182>; | |
| }; | |
| qseecom@82400000 { | |
| qcom,hlos-num-ce-hw-instances = <0x01>; | |
| reg-names = "secapp-region"; | |
| memory-region = <0x60>; | |
| qcom,qsee-reentrancy-support = <0x02>; | |
| compatible = "qcom,qseecom"; | |
| qcom,no-clock-support; | |
| qcom,disk-encrypt-pipe-pair = <0x02>; | |
| qcom,support-fde; | |
| qcom,appsbl-qseecom-support; | |
| qcom,qsee-ce-hw-instance = <0x00>; | |
| reg = <0x82400000 0x3e00000>; | |
| phandle = <0x36f>; | |
| qcom,commonlib64-loaded-by-uefi; | |
| qcom,hlos-ce-hw-instance = <0x00>; | |
| qcom,fde-key-size; | |
| }; | |
| qcom,mdss_dsi_ctrl0@ae94000 { | |
| clock-names = "byte_clk\0byte_clk_rcg\0byte_intf_clk\0pixel_clk\0pixel_clk_rcg\0esc_clk"; | |
| reg-names = "dsi_ctrl\0disp_cc_base"; | |
| cell-index = <0x00>; | |
| interrupts = <0x04 0x00>; | |
| clocks = <0x6c 0x02 0x6c 0x03 0x6c 0x05 0x6c 0x2e 0x6c 0x2f 0x6c 0x26>; | |
| interrupt-parent = <0x24c>; | |
| label = "dsi-ctrl-0"; | |
| vdda-1p2-supply = <0x7d>; | |
| compatible = "qcom,dsi-ctrl-hw-v2.4"; | |
| frame-threshold-time-us = <0x320>; | |
| reg = <0xae94000 0x400 0xaf08000 0x04>; | |
| phandle = <0x557>; | |
| refgen-supply = <0xb4>; | |
| qcom,ctrl-supply-entries { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,ctrl-supply-entry@0 { | |
| qcom,supply-disable-load = <0x00>; | |
| qcom,supply-enable-load = <0x684c>; | |
| qcom,supply-name = "vdda-1p2"; | |
| qcom,supply-max-voltage = <0x124f80>; | |
| reg = <0x00>; | |
| qcom,supply-min-voltage = <0x124f80>; | |
| }; | |
| }; | |
| qcom,core-supply-entries { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,core-supply-entry@0 { | |
| qcom,supply-disable-load = <0x00>; | |
| qcom,supply-enable-load = <0x00>; | |
| qcom,supply-name = "refgen"; | |
| qcom,supply-max-voltage = <0x00>; | |
| reg = <0x00>; | |
| qcom,supply-min-voltage = <0x00>; | |
| }; | |
| }; | |
| }; | |
| cti@6012000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| pinctrl-names = "cti-trigout-pctrl"; | |
| qcom,cti-gpio-trigout = <0x04>; | |
| pinctrl-0 = <0x233>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti2"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6012000 0x1000>; | |
| phandle = <0x51a>; | |
| }; | |
| cti@6c2a000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti-dlct_cti0"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6c2a000 0x1000>; | |
| phandle = <0x516>; | |
| }; | |
| funnel@6045000 { | |
| arm,primecell-periphid = <0xbb908>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "funnel-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-funnel-merg"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6045000 0x1000>; | |
| phandle = <0x4e6>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x1a4>; | |
| phandle = <0x19a>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x00>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x1a5>; | |
| phandle = <0x1a8>; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x01>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x1a6>; | |
| phandle = <0x1ab>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,msm-pcm-loopback { | |
| compatible = "qcom,msm-pcm-loopback"; | |
| phandle = <0x2e5>; | |
| }; | |
| qcom,gpi-dma@a00000 { | |
| iommus = <0x47 0x56 0x00>; | |
| qcom,gpi-ee-offset = <0x6000>; | |
| qcom,gpii-mask = <0x3f>; | |
| qcom,smmu-cfg = <0x01>; | |
| reg-names = "gpi-top"; | |
| interrupts = <0x00 0x117 0x04 0x00 0x118 0x04 0x00 0x119 0x04 0x00 0x11a 0x04 0x00 0x11b 0x04 0x00 0x11c 0x04 0x00 0x125 0x04 0x00 0x126 0x04 0x00 0x127 0x04 0x00 0x128 0x04>; | |
| qcom,ev-factor = <0x02>; | |
| compatible = "qcom,gpi-dma"; | |
| status = "ok"; | |
| qcom,iommu-dma-addr-pool = <0x100000 0x100000>; | |
| qcom,max-num-gpii = <0x0a>; | |
| reg = <0xa00000 0x70000>; | |
| phandle = <0x2a4>; | |
| #dma-cells = <0x05>; | |
| }; | |
| qcom,cvp@ab00000 { | |
| qcom,allowed-clock-rates = <0x10b07600 0x15d0b780 0x1a76e700>; | |
| clock-names = "gcc_video_axi1\0cvp_clk\0core_clk"; | |
| resets = <0x16 0x2c 0x6b 0x05>; | |
| interrupts = <0x00 0xea 0x04>; | |
| cvp-supply = <0x32f>; | |
| clocks = <0x16 0xcf 0x6b 0x0b 0x6b 0x07>; | |
| qcom,reg-presets = <0xb0088 0x00>; | |
| cvp-core-supply = <0x330>; | |
| compatible = "qcom,msm-cvp\0qcom,kona-cvp"; | |
| status = "ok"; | |
| reg = <0xab00000 0x100000>; | |
| phandle = <0x604>; | |
| qcom,proxy-clock-names = "gcc_video_axi1\0cvp_clk\0core_clk"; | |
| reset-names = "cvp_axi_reset\0cvp_core_reset"; | |
| qcom,clock-configs = <0x00 0x01 0x01>; | |
| cache-slice-names = "cvp"; | |
| qcom,msm-cvp,mem_cdsp { | |
| memory-region = <0x331>; | |
| compatible = "qcom,msm-cvp,mem-cdsp"; | |
| }; | |
| cvp_non_secure_cb { | |
| iommus = <0x47 0x2120 0x400>; | |
| label = "cvp_hlos"; | |
| compatible = "qcom,msm-cvp,context-bank"; | |
| qcom,iommu-dma-addr-pool = <0x4b000000 0x90000000>; | |
| buffer-types = <0xfff>; | |
| }; | |
| cvp_bus_ddr { | |
| qcom,bus-governor = "performance"; | |
| label = "cvp-ddr"; | |
| compatible = "qcom,msm-cvp,bus"; | |
| qcom,bus-slave = <0x200>; | |
| qcom,bus-master = <0x8a>; | |
| qcom,bus-range-kbps = <0x3e8 0x63af88>; | |
| }; | |
| cvp_secure_pixel_cb { | |
| iommus = <0x47 0x2123 0x400>; | |
| label = "cvp_sec_pixel"; | |
| compatible = "qcom,msm-cvp,context-bank"; | |
| qcom,iommu-dma-addr-pool = <0x26800000 0x24800000>; | |
| buffer-types = <0x106>; | |
| qcom,iommu-vmid = <0x0a>; | |
| }; | |
| cvp_secure_nonpixel_cb { | |
| iommus = <0x47 0x2124 0x400>; | |
| label = "cvp_sec_nonpixel"; | |
| compatible = "qcom,msm-cvp,context-bank"; | |
| qcom,iommu-dma-addr-pool = <0x1000000 0x25800000>; | |
| buffer-types = <0x741>; | |
| qcom,iommu-vmid = <0x0b>; | |
| }; | |
| cvp_cnoc { | |
| qcom,bus-governor = "performance"; | |
| label = "cvp-cnoc"; | |
| compatible = "qcom,msm-cvp,bus"; | |
| qcom,bus-slave = <0x254>; | |
| qcom,bus-master = <0x01>; | |
| qcom,bus-range-kbps = <0x3e8 0x3e8>; | |
| }; | |
| }; | |
| tpda@7863000 { | |
| arm,primecell-periphid = <0xbb969>; | |
| qcom,cmb-elem-size = <0x00 0x20 0x01 0x20 0x02 0x40>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpda-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-tpda-apss"; | |
| qcom,dsb-elem-size = <0x03 0x20>; | |
| compatible = "arm,primecell"; | |
| qcom,tpda-atid = <0x42>; | |
| reg = <0x7863000 0x1000>; | |
| phandle = <0x4fc>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x208>; | |
| phandle = <0x23a>; | |
| }; | |
| }; | |
| port@3 { | |
| reg = <0x02>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x20b>; | |
| phandle = <0x20f>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x00>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x209>; | |
| phandle = <0x20d>; | |
| }; | |
| }; | |
| port@4 { | |
| reg = <0x03>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x20c>; | |
| phandle = <0x210>; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x01>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x20a>; | |
| phandle = <0x20e>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| etm@7540000 { | |
| arm,primecell-periphid = <0xbb95d>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x49 0x00>; | |
| cpu = <0x12>; | |
| qcom,tupwr-disable; | |
| coresight-name = "coresight-etm5"; | |
| compatible = "arm,primecell"; | |
| reg = <0x7540000 0x1000>; | |
| phandle = <0x54c>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x240>; | |
| phandle = <0x249>; | |
| }; | |
| }; | |
| }; | |
| qcom,gcc@100000 { | |
| #reset-cells = <0x01>; | |
| reg-names = "cc_base"; | |
| vdd_cx_ao-supply = <0x68>; | |
| vdd_mm-supply = <0x69>; | |
| #clock-cells = <0x01>; | |
| compatible = "qcom,gcc-kona\0syscon"; | |
| reg = <0x100000 0x1f0000>; | |
| phandle = <0x16>; | |
| vdd_cx-supply = <0x67>; | |
| }; | |
| funnel@6b04000 { | |
| arm,primecell-periphid = <0xbb908>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "funnel-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-funnel-swao"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6b04000 0x1000>; | |
| phandle = <0x4e1>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x196>; | |
| phandle = <0x195>; | |
| }; | |
| }; | |
| port@5 { | |
| reg = <0x05>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x19b>; | |
| phandle = <0x1d0>; | |
| }; | |
| }; | |
| port@3 { | |
| reg = <0x06>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x199>; | |
| phandle = <0x19c>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x03>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x197>; | |
| phandle = <0x236>; | |
| }; | |
| }; | |
| port@4 { | |
| reg = <0x07>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x19a>; | |
| phandle = <0x1a4>; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x05>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x198>; | |
| phandle = <0x235>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,npu@9800000 { | |
| qcom,smem-state-names = "qcom,force-stop"; | |
| memory-region = <0x9c>; | |
| qcom,pas-id = <0x17>; | |
| compatible = "qcom,pil-tz-generic"; | |
| status = "ok"; | |
| reg = <0x9800000 0x800000>; | |
| qcom,smem-states = <0x9d 0x00>; | |
| qcom,firmware-name = "npu"; | |
| }; | |
| qcom,cpu0-cpu-llcc-lat { | |
| qcom,src-dst-ports = <0x01 0x302>; | |
| governor = "performance"; | |
| compatible = "qcom,devbw"; | |
| phandle = <0x58>; | |
| qcom,active-only; | |
| operating-points-v2 = <0x4b>; | |
| }; | |
| jtagmm@7640000 { | |
| clock-names = "core_clk"; | |
| reg-names = "etm-base"; | |
| clocks = <0x49 0x00>; | |
| compatible = "qcom,jtagv8-mm"; | |
| qcom,coresight-jtagmm-cpu = <0x13>; | |
| reg = <0x7640000 0x1000>; | |
| phandle = <0x358>; | |
| }; | |
| tpdm@6840000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-tpdm-vsense"; | |
| compatible = "arm,primecell"; | |
| status = "disabled"; | |
| reg = <0x6840000 0x1000>; | |
| phandle = <0x4ee>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x1c9>; | |
| phandle = <0x1c3>; | |
| }; | |
| }; | |
| }; | |
| cti@6c38000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti-compute_dl_cti"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6c38000 0x1000>; | |
| phandle = <0x543>; | |
| }; | |
| funnel@6042000 { | |
| arm,primecell-periphid = <0xbb908>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "funnel-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-funnel-in1"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6042000 0x1000>; | |
| phandle = <0x4e9>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x1ab>; | |
| phandle = <0x1a6>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x1ac>; | |
| phandle = <0x1d8>; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x04>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x1ad>; | |
| phandle = <0x238>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| spi@880000 { | |
| pinctrl-names = "default\0sleep"; | |
| #address-cells = <0x01>; | |
| pinctrl-0 = <0x2d2>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| reg-names = "se_phys"; | |
| interrupts = <0x00 0x175 0x04>; | |
| clocks = <0x16 0x78 0x16 0x88 0x16 0x89>; | |
| #size-cells = <0x00>; | |
| qcom,wrapper-core = <0x2bf>; | |
| spi-max-frequency = <0x2faf080>; | |
| dma-names = "tx\0rx"; | |
| compatible = "qcom,spi-geni"; | |
| pinctrl-1 = <0x2d3>; | |
| status = "disabled"; | |
| reg = <0x880000 0x4000>; | |
| phandle = <0x5c6>; | |
| dmas = <0x2c2 0x00 0x00 0x01 0x40 0x00 0x2c2 0x01 0x00 0x01 0x40 0x00>; | |
| }; | |
| syscon@90ba000 { | |
| compatible = "syscon"; | |
| reg = <0x90ba000 0x54>; | |
| phandle = <0x70>; | |
| }; | |
| spi@a94000 { | |
| pinctrl-names = "default\0sleep"; | |
| #address-cells = <0x01>; | |
| pinctrl-0 = <0x2ba>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| reg-names = "se_phys"; | |
| interrupts = <0x00 0x166 0x04>; | |
| clocks = <0x16 0x74 0x16 0x86 0x16 0x87>; | |
| #size-cells = <0x00>; | |
| qcom,wrapper-core = <0x2a3>; | |
| spi-max-frequency = <0x2faf080>; | |
| dma-names = "tx\0rx"; | |
| compatible = "qcom,spi-geni"; | |
| pinctrl-1 = <0x2bb>; | |
| status = "disabled"; | |
| reg = <0xa94000 0x4000>; | |
| phandle = <0x5bc>; | |
| dmas = <0x2a4 0x00 0x05 0x01 0x40 0x00 0x2a4 0x01 0x05 0x01 0x40 0x00>; | |
| }; | |
| qcom,gdsc@ad09004 { | |
| clock-names = "ahb_clk"; | |
| qcom,msm-bus,name = "sbi_gdsc_ahb"; | |
| parent-supply = <0x69>; | |
| qcom,retain-regs; | |
| clocks = <0x16 0x0b>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| regulator-name = "sbi_gdsc"; | |
| vdd_parent-supply = <0x69>; | |
| compatible = "qcom,gdsc"; | |
| reg = <0xad09004 0x04>; | |
| phandle = <0x375>; | |
| qcom,msm-bus,vectors-KBps = <0x01 0x24d 0x00 0x00 0x01 0x24d 0x00 0x01>; | |
| }; | |
| regulator-dbb1 { | |
| regulator-max-microvolt = <0x36ee80>; | |
| gpio = <0x635 0x01 0x00>; | |
| enable-active-high; | |
| regulator-min-microvolt = <0x36ee80>; | |
| regulator-name = "vdd_tof"; | |
| startup-delay-us = <0x3e8>; | |
| compatible = "regulator-fixed"; | |
| phandle = <0x6d2>; | |
| }; | |
| qcom,smp2p_sleepstate { | |
| interrupts = <0x00 0x00>; | |
| interrupt-parent = <0x9f>; | |
| compatible = "qcom,smp2p-sleepstate"; | |
| interrupt-names = "smp2p-sleepstate-in"; | |
| qcom,smem-states = <0x9e 0x00>; | |
| }; | |
| qcom,a5@ac00000 { | |
| ubwc-ipe-write-cfg = <0x161ef 0x1620f>; | |
| ubwc-bps-write-cfg = <0x161ef 0x1620f>; | |
| clock-names = "soc_fast_ahb\0icp_ahb_clk\0icp_clk_src\0icp_clk"; | |
| fw_name = "CAMERA_ICP.elf"; | |
| reg-names = "a5_qgic\0a5_sierra\0a5_csr"; | |
| reg-cam-base = <0x00 0x10000 0x18000>; | |
| cell-index = <0x00>; | |
| camss-vdd-supply = <0x253>; | |
| interrupts = <0x00 0x1cf 0x01>; | |
| clocks = <0x6d 0x21 0x6d 0x26 0x6d 0x28 0x6d 0x27>; | |
| clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; | |
| compatible = "qcom,cam-a5"; | |
| src-clock-name = "icp_clk_src"; | |
| status = "ok"; | |
| interrupt-names = "a5"; | |
| reg = <0xac00000 0x6000 0xac10000 0x8000 0xac18000 0x3000>; | |
| regulator-names = "camss-vdd"; | |
| phandle = <0x596>; | |
| clock-rates = <0x5f5e100 0x00 0x17d78400 0x00 0xbebc200 0x00 0x1c9c3800 0x00 0x11e1a300 0x00 0x23c34600 0x00 0x17d78400 0x00 0x23c34600 0x00 0x17d78400 0x00 0x23c34600 0x00>; | |
| ubwc-ipe-fetch-cfg = <0x707b 0x7083>; | |
| ubwc-bps-fetch-cfg = <0x707b 0x7083>; | |
| }; | |
| cti@7120000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| cpu = <0x0e>; | |
| coresight-name = "coresight-cti-cpu1"; | |
| compatible = "arm,primecell"; | |
| reg = <0x7120000 0x1000>; | |
| phandle = <0x529>; | |
| }; | |
| wsa_core_clk { | |
| qcom,codec-ext-clk-src = <0x03>; | |
| #clock-cells = <0x01>; | |
| compatible = "qcom,audio-ref-clk"; | |
| phandle = <0x657>; | |
| qcom,codec-lpass-clk-id = <0x309>; | |
| qcom,codec-lpass-ext-clk-freq = <0x124f800>; | |
| }; | |
| tpdm@69c0000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-tpdm-dl-south"; | |
| compatible = "arm,primecell"; | |
| reg = <0x69c0000 0x1000>; | |
| phandle = <0x4f7>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x1d7>; | |
| phandle = <0x1d6>; | |
| }; | |
| }; | |
| }; | |
| tpdm@6c08000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-tpdm-mm"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6c08000 0x1000>; | |
| phandle = <0x1e7>; | |
| qcom,msr-fix-req; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x219>; | |
| phandle = <0x214>; | |
| }; | |
| }; | |
| }; | |
| qcom,spmi@c440000 { | |
| #address-cells = <0x02>; | |
| reg-names = "core\0chnls\0obsrvr\0intr\0cnfg"; | |
| qcom,channel = <0x00>; | |
| cell-index = <0x00>; | |
| #size-cells = <0x00>; | |
| interrupts-extended = <0x76 0x01 0x04>; | |
| compatible = "qcom,spmi-pmic-arb"; | |
| #interrupt-cells = <0x04>; | |
| interrupt-names = "periph_irq"; | |
| reg = <0xc440000 0x1100 0xc600000 0x2000000 0xe600000 0x100000 0xe700000 0xa0000 0xc40a000 0x26000>; | |
| phandle = <0x376>; | |
| qcom,ee = <0x00>; | |
| interrupt-controller; | |
| qcom,pm8150l@4 { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,spmi-pmic"; | |
| reg = <0x04 0x00>; | |
| qcom,power-on@800 { | |
| compatible = "qcom,qpnp-power-on"; | |
| reg = <0x800 0x100>; | |
| }; | |
| bcl@3d00 { | |
| interrupts = <0x04 0x3d 0x00 0x00 0x04 0x3d 0x01 0x00 0x04 0x3d 0x02 0x00>; | |
| #thermal-sensor-cells = <0x01>; | |
| compatible = "qcom,bcl-v5"; | |
| interrupt-names = "bcl-lvl0\0bcl-lvl1\0bcl-lvl2"; | |
| reg = <0x3d00 0x100>; | |
| phandle = <0x634>; | |
| }; | |
| vadc@3100 { | |
| io-channel-ranges; | |
| #address-cells = <0x01>; | |
| interrupts = <0x04 0x31 0x00 0x01>; | |
| #io-channel-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,spmi-adc5"; | |
| qcom,adc-vdd-reference = <0x753>; | |
| interrupt-names = "eoc-int-en-set"; | |
| reg = <0x3100 0x100>; | |
| phandle = <0x630>; | |
| skin_msm_therm@4e { | |
| label = "skin_msm_therm"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| qcom,ratiometric; | |
| reg = <0x4e>; | |
| qcom,hw-settle-time = <0xc8>; | |
| }; | |
| vph_pwr@83 { | |
| label = "vph_pwr"; | |
| qcom,pre-scaling = <0x01 0x03>; | |
| reg = <0x83>; | |
| }; | |
| vref_1p25@1 { | |
| label = "vref_1p25"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| reg = <0x01>; | |
| }; | |
| ref_gnd@0 { | |
| label = "ref_gnd"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| reg = <0x00>; | |
| }; | |
| pa_therm2@4f { | |
| label = "pa_therm2"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| qcom,ratiometric; | |
| reg = <0x4f>; | |
| qcom,hw-settle-time = <0xc8>; | |
| }; | |
| camera_flash_therm@4d { | |
| label = "camera_flash_therm"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| qcom,ratiometric; | |
| reg = <0x4d>; | |
| qcom,hw-settle-time = <0xc8>; | |
| }; | |
| die_temp@2 { | |
| label = "die_temp"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| reg = <0x06>; | |
| }; | |
| }; | |
| pinctrl@c000 { | |
| qcom,gpios-disallowed = <0x02 0x09 0x0c>; | |
| gpio-controller; | |
| interrupts = <0x04 0xc0 0x00 0x00 0x04 0xc2 0x00 0x00 0x04 0xc3 0x00 0x00 0x04 0xc4 0x00 0x00 0x04 0xc5 0x00 0x00 0x04 0xc6 0x00 0x00 0x04 0xc7 0x00 0x00 0x04 0xc9 0x00 0x00 0x04 0xca 0x00 0x00>; | |
| compatible = "qcom,spmi-gpio"; | |
| interrupt-names = "pm8150l_gpio1\0pm8150l_gpio3\0pm8150l_gpio4\0pm8150l_gpio5\0pm8150l_gpio6\0pm8150l_gpio7\0pm8150l_gpio8\0pm8150l_gpio10\0pm8150l_gpio11"; | |
| reg = <0xc000 0xc00>; | |
| phandle = <0x6bb>; | |
| #gpio-cells = <0x02>; | |
| }; | |
| clock-controller@5b00 { | |
| clock-output-names = "pm8150l_div_clk1"; | |
| clock-names = "xo"; | |
| clocks = <0x15 0x00>; | |
| #clock-cells = <0x01>; | |
| compatible = "qcom,spmi-clkdiv"; | |
| qcom,num-clkdivs = <0x01>; | |
| reg = <0x5b00 0x100>; | |
| phandle = <0x6ba>; | |
| }; | |
| adc_tm@3500 { | |
| #address-cells = <0x01>; | |
| interrupts = <0x04 0x35 0x00 0x01>; | |
| io-channels = <0x630 0x4d 0x630 0x4e 0x630 0x4f>; | |
| #size-cells = <0x00>; | |
| #thermal-sensor-cells = <0x01>; | |
| compatible = "qcom,adc-tm5"; | |
| interrupt-names = "thr-int-en"; | |
| reg = <0x3500 0x100>; | |
| phandle = <0x6a2>; | |
| skin_msm_therm@4e { | |
| qcom,ratiometric; | |
| reg = <0x4e>; | |
| qcom,hw-settle-time = <0xc8>; | |
| }; | |
| pa_therm2@4f { | |
| qcom,ratiometric; | |
| reg = <0x4f>; | |
| qcom,hw-settle-time = <0xc8>; | |
| }; | |
| camera_flash_therm@4d { | |
| qcom,ratiometric; | |
| reg = <0x4d>; | |
| qcom,hw-settle-time = <0xc8>; | |
| }; | |
| }; | |
| qcom,revid@100 { | |
| compatible = "qcom,qpnp-revid"; | |
| reg = <0x100 0x100>; | |
| phandle = <0x631>; | |
| }; | |
| qcom,temp-alarm@2400 { | |
| qcom,temperature-threshold-set = <0x01>; | |
| interrupts = <0x04 0x24 0x00 0x03>; | |
| io-channels = <0x630 0x06>; | |
| #thermal-sensor-cells = <0x00>; | |
| compatible = "qcom,spmi-temp-alarm"; | |
| reg = <0x2400 0x100>; | |
| phandle = <0x633>; | |
| io-channel-names = "thermal"; | |
| }; | |
| }; | |
| qcom,pm8150@0 { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,spmi-pmic"; | |
| reg = <0x00 0x00>; | |
| qcom,power-on@800 { | |
| interrupts = <0x00 0x08 0x00 0x03 0x00 0x08 0x01 0x03>; | |
| qcom,pon-dbc-delay = <0x3d09>; | |
| compatible = "qcom,qpnp-power-on"; | |
| qcom,system-reset; | |
| interrupt-names = "kpdpwr\0resin"; | |
| reg = <0x800 0x100>; | |
| qcom,kpdpwr-sw-debounce; | |
| qcom,store-hard-reset-reason; | |
| qcom,pon_1 { | |
| qcom,pull-up; | |
| qcom,pon-type = <0x00>; | |
| linux,code = <0x74>; | |
| }; | |
| qcom,pon_2 { | |
| qcom,pull-up; | |
| qcom,pon-type = <0x01>; | |
| linux,code = <0x72>; | |
| }; | |
| }; | |
| vadc@3100 { | |
| io-channel-ranges; | |
| #address-cells = <0x01>; | |
| interrupts = <0x00 0x31 0x00 0x01>; | |
| #io-channel-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,spmi-adc5"; | |
| qcom,adc-vdd-reference = <0x753>; | |
| interrupt-names = "eoc-int-en-set"; | |
| reg = <0x3100 0x100>; | |
| phandle = <0x61f>; | |
| vph_pwr@83 { | |
| label = "vph_pwr"; | |
| qcom,pre-scaling = <0x01 0x03>; | |
| reg = <0x83>; | |
| }; | |
| vref_1p25@1 { | |
| label = "vref_1p25"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| reg = <0x01>; | |
| }; | |
| pa_therm1@4e { | |
| label = "pa_therm1"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| qcom,ratiometric; | |
| reg = <0x4e>; | |
| qcom,hw-settle-time = <0xc8>; | |
| }; | |
| vcoin@85 { | |
| label = "vcoin"; | |
| qcom,pre-scaling = <0x01 0x03>; | |
| reg = <0x85>; | |
| }; | |
| ref_gnd@0 { | |
| label = "ref_gnd"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| reg = <0x00>; | |
| }; | |
| xo_therm@4c { | |
| label = "xo_therm"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| qcom,ratiometric; | |
| reg = <0x4c>; | |
| qcom,hw-settle-time = <0xc8>; | |
| }; | |
| skin_therm@4d { | |
| label = "skin_therm"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| qcom,ratiometric; | |
| reg = <0x4d>; | |
| qcom,hw-settle-time = <0xc8>; | |
| }; | |
| die_temp@2 { | |
| label = "die_temp"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| reg = <0x06>; | |
| }; | |
| }; | |
| pinctrl@c000 { | |
| qcom,gpios-disallowed = <0x02 0x04 0x05 0x08>; | |
| gpio-controller; | |
| interrupts = <0x00 0xc0 0x00 0x00 0x00 0xc2 0x00 0x00 0x00 0xc5 0x00 0x00 0x00 0xc6 0x00 0x00 0x00 0xc8 0x00 0x00 0x00 0xc9 0x00 0x00>; | |
| compatible = "qcom,spmi-gpio"; | |
| interrupt-names = "pm8150_gpio1\0pm8150_gpio3\0pm8150_gpio6\0pm8150_gpio7\0pm8150_gpio9\0pm8150_gpio10"; | |
| reg = <0xc000 0xa00>; | |
| phandle = <0x695>; | |
| #gpio-cells = <0x02>; | |
| key_confirm { | |
| key_confirm_default { | |
| function = "normal"; | |
| pins = "gpio7"; | |
| phandle = <0x6a7>; | |
| bias-pull-up; | |
| power-source = <0x00>; | |
| input-enable; | |
| }; | |
| }; | |
| key_vol_up { | |
| key_vol_up_default { | |
| function = "normal"; | |
| pins = "gpio6"; | |
| phandle = <0x694>; | |
| bias-pull-up; | |
| power-source = <0x01>; | |
| input-enable; | |
| }; | |
| }; | |
| usb2_vbus_det { | |
| usb2_vbus_det_default { | |
| function = "normal"; | |
| pins = "gpio10"; | |
| bias-pull-down; | |
| phandle = <0x69b>; | |
| power-source = <0x01>; | |
| input-enable; | |
| }; | |
| }; | |
| usb2_vbus_boost { | |
| usb2_vbus_boost_default { | |
| function = "normal"; | |
| pins = "gpio9"; | |
| phandle = <0x69c>; | |
| power-source = <0x01>; | |
| output-low; | |
| }; | |
| }; | |
| imu_clkin { | |
| imu_clkin_default { | |
| function = "func1"; | |
| pins = "gpio3"; | |
| qcom,dtest-buffer = <0x01>; | |
| qcom,drive-strength = <0x01>; | |
| bias-disable; | |
| phandle = <0x6a5>; | |
| power-source = <0x00>; | |
| output-low; | |
| }; | |
| imu_clkin_sleep { | |
| function = "func1"; | |
| pins = "gpio3"; | |
| qcom,dtest-buffer = <0x01>; | |
| qcom,drive-strength = <0x01>; | |
| bias-pull-down; | |
| phandle = <0x6a6>; | |
| power-source = <0x00>; | |
| input-enable; | |
| }; | |
| }; | |
| key_home { | |
| key_home_default { | |
| function = "normal"; | |
| pins = "gpio1"; | |
| phandle = <0x696>; | |
| bias-pull-up; | |
| power-source = <0x00>; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| sdam@b100 { | |
| compatible = "qcom,spmi-sdam"; | |
| reg = <0xb100 0x100>; | |
| phandle = <0x62a>; | |
| }; | |
| clock-controller@5b00 { | |
| clock-output-names = "pm8150_div_clk1\0pm8150_div_clk2"; | |
| clock-names = "xo"; | |
| clocks = <0x15 0x00>; | |
| #clock-cells = <0x01>; | |
| compatible = "qcom,spmi-clkdiv"; | |
| qcom,num-clkdivs = <0x02>; | |
| reg = <0x5b00 0x200>; | |
| phandle = <0x6a4>; | |
| }; | |
| adc_tm@3500 { | |
| #address-cells = <0x01>; | |
| interrupts = <0x00 0x35 0x00 0x01>; | |
| io-channels = <0x61f 0x4c 0x61f 0x4d 0x61f 0x4e>; | |
| #size-cells = <0x00>; | |
| #thermal-sensor-cells = <0x01>; | |
| compatible = "qcom,adc-tm5"; | |
| interrupt-names = "thr-int-en"; | |
| reg = <0x3500 0x100>; | |
| phandle = <0x6a1>; | |
| pa_therm1@4e { | |
| qcom,ratiometric; | |
| reg = <0x4e>; | |
| qcom,hw-settle-time = <0xc8>; | |
| }; | |
| xo_therm@4c { | |
| qcom,ratiometric; | |
| reg = <0x4c>; | |
| qcom,hw-settle-time = <0xc8>; | |
| }; | |
| skin_therm@4d { | |
| qcom,ratiometric; | |
| reg = <0x4d>; | |
| qcom,hw-settle-time = <0xc8>; | |
| }; | |
| }; | |
| qcom,temp-alarm@2400 { | |
| qcom,temperature-threshold-set = <0x01>; | |
| interrupts = <0x00 0x24 0x00 0x03>; | |
| io-channels = <0x61f 0x06>; | |
| #thermal-sensor-cells = <0x00>; | |
| compatible = "qcom,spmi-temp-alarm"; | |
| reg = <0x2400 0x100>; | |
| phandle = <0x620>; | |
| io-channel-names = "thermal"; | |
| }; | |
| qcom,pm8150_rtc { | |
| interrupts = <0x00 0x61 0x01 0x00>; | |
| compatible = "qcom,pm8941-rtc"; | |
| phandle = <0x6a8>; | |
| }; | |
| }; | |
| qcom,pm8150b@2 { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,spmi-pmic"; | |
| reg = <0x02 0x00>; | |
| qcom,power-on@800 { | |
| compatible = "qcom,qpnp-power-on"; | |
| reg = <0x800 0x100>; | |
| }; | |
| clock-controller@6000 { | |
| clock-output-names = "pm8150b_div_clk1"; | |
| clock-names = "xo"; | |
| clocks = <0x15 0x00>; | |
| #clock-cells = <0x01>; | |
| compatible = "qcom,spmi-clkdiv"; | |
| qcom,num-clkdivs = <0x01>; | |
| reg = <0x6000 0x100>; | |
| phandle = <0x6ac>; | |
| }; | |
| qcom,qpnp-smb5 { | |
| pinctrl-names = "default"; | |
| qcom,auto-recharge-vbat-mv = <0x10ea>; | |
| #address-cells = <0x01>; | |
| qcom,pogo_det-gpio = <0x66 0x18 0x00>; | |
| pinctrl-0 = <0x4d7>; | |
| qcom,charger-temp-max = <0x320>; | |
| #qcom,auto-recharge-soc = <0x62>; | |
| #qcom,suspend-input-on-debug-batt; | |
| #qcom,fcc-stepping-enable; | |
| qcom,chg-term-current-ma = <0xfffffe70>; | |
| qcom,sec-charger-config = <0x01>; | |
| io-channels = <0x621 0x1e 0x621 0x07 0x621 0x99 0x621 0x83 0x621 0x09>; | |
| #size-cells = <0x01>; | |
| dpdm-supply = <0x183>; | |
| qcom,battery-data = <0x625>; | |
| qcom,boost_en = <0x626 0x02 0x00>; | |
| qcom,usb-icl-ua = <0x1e8480>; | |
| qcom,thermal-mitigation = <0x401640 0x3567e0 0x2dc6c0 0x2625a0 0x1e8480 0x16e360 0xf4240 0x7a120>; | |
| compatible = "qcom,qpnp-smb5"; | |
| status = "ok"; | |
| qcom,chg-term-src = <0x01>; | |
| qcom,sw-jeita-enable; | |
| qcom,typec_en-gpio = <0x66 0x4a 0x00>; | |
| qcom,pmic-revid = <0x624>; | |
| phandle = <0x6ae>; | |
| qcom,typec_det-gpio = <0x66 0x81 0x00>; | |
| qcom,smb-internal-pull-kohm = <0x00>; | |
| qcom,pogo_en-gpio = <0x66 0x41 0x00>; | |
| #qcom,step-charging-enable; | |
| qcom,float-option = <0x02>; | |
| qcom,wd-bark-time-secs = <0x10>; | |
| io-channel-names = "mid_voltage\0usb_in_current\0sbux_res\0vph_voltage\0chg_temp"; | |
| #cooling-cells = <0x02>; | |
| qcom,smb-temp-max = <0x320>; | |
| qcom,chgr@1000 { | |
| interrupts = <0x02 0x10 0x00 0x01 0x02 0x10 0x01 0x01 0x02 0x10 0x02 0x01 0x02 0x10 0x03 0x01 0x02 0x10 0x04 0x01 0x02 0x10 0x06 0x03 0x02 0x10 0x07 0x03>; | |
| interrupt-names = "chgr-error\0chg-state-change\0step-chg-state-change\0step-chg-soc-update-fail\0step-chg-soc-update-req\0vph-alarm\0vph-drop-prechg"; | |
| reg = <0x1000 0x100>; | |
| }; | |
| qcom,batif@1200 { | |
| interrupts = <0x02 0x12 0x00 0x01 0x02 0x12 0x02 0x03 0x02 0x12 0x03 0x03 0x02 0x12 0x04 0x03 0x02 0x12 0x05 0x03 0x02 0x12 0x06 0x03 0x02 0x12 0x07 0x03>; | |
| interrupt-names = "bat-temp\0bat-ov\0bat-low\0bat-therm-or-id-missing\0bat-terminal-missing\0buck-oc\0vph-ov"; | |
| reg = <0x1200 0x100>; | |
| }; | |
| qcom,typec@1500 { | |
| interrupts = <0x02 0x15 0x00 0x01 0x02 0x15 0x01 0x03 0x02 0x15 0x02 0x01 0x02 0x15 0x03 0x03 0x02 0x15 0x04 0x01 0x02 0x15 0x05 0x01 0x02 0x15 0x06 0x03 0x02 0x15 0x07 0x01>; | |
| interrupt-names = "typec-or-rid-detect-change\0typec-vpd-detect\0typec-cc-state-change\0typec-vconn-oc\0typec-vbus-change\0typec-attach-detach\0typec-legacy-cable-detect\0typec-try-snk-src-detect"; | |
| reg = <0x1500 0x100>; | |
| }; | |
| qcom,dc@1400 { | |
| interrupts = <0x02 0x14 0x01 0x03 0x02 0x14 0x02 0x03 0x02 0x14 0x03 0x03 0x02 0x14 0x04 0x03 0x02 0x14 0x05 0x03 0x02 0x14 0x06 0x03 0x02 0x14 0x07 0x03>; | |
| interrupt-names = "dcin-vashdn\0dcin-uv\0dcin-ov\0dcin-plugin\0dcin-revi\0dcin-pon\0dcin-en"; | |
| reg = <0x1400 0x100>; | |
| }; | |
| qcom,misc@1600 { | |
| interrupts = <0x02 0x16 0x00 0x01 0x02 0x16 0x01 0x01 0x02 0x16 0x02 0x03 0x02 0x16 0x03 0x03 0x02 0x16 0x04 0x03 0x02 0x16 0x06 0x03 0x02 0x16 0x07 0x03>; | |
| interrupt-names = "wdog-snarl\0wdog-bark\0aicl-fail\0aicl-done\0smb-en\0temp-change\0temp-change-smb"; | |
| reg = <0x1600 0x100>; | |
| }; | |
| qcom,dcdc@1100 { | |
| interrupts = <0x02 0x11 0x00 0x03 0x02 0x11 0x01 0x03 0x02 0x11 0x02 0x03 0x02 0x11 0x04 0x03 0x02 0x11 0x05 0x03 0x02 0x11 0x06 0x03 0x02 0x11 0x07 0x03>; | |
| interrupt-names = "otg-fail\0otg-oc-disable-sw\0otg-oc-hiccup\0high-duty-cycle\0input-current-limiting\0concurrent-mode-disable\0switcher-power-ok"; | |
| reg = <0x1100 0x100>; | |
| }; | |
| qcom,usb@1300 { | |
| interrupts = <0x02 0x13 0x00 0x03 0x02 0x13 0x01 0x03 0x02 0x13 0x02 0x03 0x02 0x13 0x03 0x03 0x02 0x13 0x04 0x03 0x02 0x13 0x05 0x03 0x02 0x13 0x06 0x01 0x02 0x13 0x07 0x01>; | |
| interrupt-names = "usbin-collapse\0usbin-vashdn\0usbin-uv\0usbin-ov\0usbin-plugin\0usbin-revi-change\0usbin-src-change\0usbin-icl-change"; | |
| reg = <0x1300 0x100>; | |
| }; | |
| qcom,smb5-vbus { | |
| regulator-name = "smb5-vbus"; | |
| phandle = <0x627>; | |
| }; | |
| qcom,smb5-vconn { | |
| regulator-name = "smb5-vconn"; | |
| phandle = <0x628>; | |
| }; | |
| }; | |
| qpnp,fg { | |
| qcom,fg-esr-timer-dischg-slow = <0x00 0x60>; | |
| qcom,fg-esr-timer-dischg-fast = <0x00 0x07>; | |
| #address-cells = <0x01>; | |
| qcom,force-calib-level = <0x00>; | |
| nvmem-names = "fg_sdam"; | |
| qcom,fg-esr-cal-soc-thresh = <0x1a 0xe6>; | |
| #size-cells = <0x01>; | |
| qcom,fg-esr-timer-chg-slow = <0x00 0x60>; | |
| qcom,fg-esr-timer-chg-fast = <0x00 0x07>; | |
| qcom,hold-soc-while-full; | |
| qcom,battery-data = <0x625>; | |
| qcom,soc-scale-mode-en; | |
| qcom,linearize-soc; | |
| qcom,cl-wt-enable; | |
| compatible = "qcom,fg-gen4"; | |
| status = "ok"; | |
| nvmem = <0x62a>; | |
| qcom,pmic-pbs = <0x629>; | |
| qcom,pmic-revid = <0x624>; | |
| phandle = <0x6af>; | |
| qcom,fg-esr-cal-temp-thresh = <0x0a 0x28>; | |
| qcom,five-pin-battery; | |
| qcom,fg-memif@4300 { | |
| interrupts = <0x02 0x43 0x00 0x03 0x02 0x43 0x01 0x03 0x02 0x43 0x02 0x03 0x02 0x43 0x03 0x01 0x02 0x43 0x04 0x02>; | |
| status = "okay"; | |
| interrupt-names = "ima-rdy\0ima-xcp\0dma-xcp\0dma-grant\0mem-attn"; | |
| reg = <0x4300 0x100>; | |
| }; | |
| qcom,fg-batt-soc@4000 { | |
| interrupts = <0x02 0x40 0x00 0x03 0x02 0x40 0x01 0x03 0x02 0x40 0x02 0x01 0x02 0x40 0x03 0x01 0x02 0x40 0x04 0x03 0x02 0x40 0x05 0x01 0x02 0x40 0x06 0x03 0x02 0x40 0x07 0x03>; | |
| status = "okay"; | |
| interrupt-names = "soc-update\0soc-ready\0bsoc-delta\0msoc-delta\0msoc-low\0msoc-empty\0msoc-high\0msoc-full"; | |
| reg = <0x4000 0x100>; | |
| }; | |
| qcom,fg-batt-info@4100 { | |
| interrupts = <0x02 0x41 0x00 0x03 0x02 0x41 0x01 0x03 0x02 0x41 0x03 0x01>; | |
| status = "okay"; | |
| interrupt-names = "vbatt-low\0vbatt-pred-delta\0esr-delta"; | |
| reg = <0x4100 0x100>; | |
| }; | |
| qcom,fg-rradc@4200 { | |
| interrupts = <0x02 0x42 0x00 0x03 0x02 0x42 0x01 0x03 0x02 0x42 0x02 0x03 0x02 0x42 0x03 0x03 0x02 0x42 0x04 0x03>; | |
| status = "okay"; | |
| interrupt-names = "batt-missing\0batt-id\0batt-temp-delta\0batt-temp-hot\0batt-temp-cold"; | |
| reg = <0x4200 0x100>; | |
| }; | |
| }; | |
| qcom,pbs@7200 { | |
| compatible = "qcom,qpnp-pbs"; | |
| reg = <0x7200 0x100>; | |
| phandle = <0x629>; | |
| }; | |
| vadc@3100 { | |
| io-channel-ranges; | |
| #address-cells = <0x01>; | |
| reg-names = "adc5-usr-base\0adc5-cal-base"; | |
| interrupts = <0x02 0x31 0x00 0x01>; | |
| #io-channel-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,spmi-adc5"; | |
| qcom,adc-vdd-reference = <0x753>; | |
| interrupt-names = "eoc-int-en-set"; | |
| reg = <0x3100 0x100 0x3700 0x100>; | |
| phandle = <0x621>; | |
| smb1390_therm@e { | |
| label = "smb1390_therm"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| reg = <0x0e>; | |
| qcom,hw-settle-time = <0xc8>; | |
| }; | |
| mid_chg_div6@1e { | |
| label = "chg_mid"; | |
| qcom,pre-scaling = <0x01 0x06>; | |
| reg = <0x1e>; | |
| }; | |
| usb_in_v_div_16@8 { | |
| label = "usb_in_v_div_16"; | |
| qcom,pre-scaling = <0x01 0x10>; | |
| reg = <0x08>; | |
| }; | |
| smb1355_therm@4e { | |
| label = "smb1355_therm"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| qcom,ratiometric; | |
| reg = <0x4e>; | |
| qcom,hw-settle-time = <0xc8>; | |
| }; | |
| vph_pwr@83 { | |
| label = "vph_pwr"; | |
| qcom,pre-scaling = <0x01 0x03>; | |
| reg = <0x83>; | |
| }; | |
| vref_1p25@1 { | |
| label = "vref_1p25"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| reg = <0x01>; | |
| }; | |
| usb_in_i_uv@7 { | |
| label = "usb_in_i_uv"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| reg = <0x07>; | |
| }; | |
| ref_gnd@0 { | |
| label = "ref_gnd"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| reg = <0x00>; | |
| }; | |
| bat_id@4b { | |
| label = "bat_id"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| qcom,ratiometric; | |
| reg = <0x4b>; | |
| qcom,hw-settle-time = <0xc8>; | |
| }; | |
| chg_temp@9 { | |
| label = "chg_temp"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| reg = <0x09>; | |
| }; | |
| chg_sbux@99 { | |
| label = "chg_sbux"; | |
| qcom,pre-scaling = <0x01 0x03>; | |
| reg = <0x99>; | |
| }; | |
| conn_therm@4f { | |
| label = "conn_therm"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| qcom,ratiometric; | |
| reg = <0x4f>; | |
| qcom,hw-settle-time = <0xc8>; | |
| }; | |
| die_temp@2 { | |
| label = "die_temp"; | |
| qcom,pre-scaling = <0x01 0x01>; | |
| reg = <0x06>; | |
| }; | |
| }; | |
| pinctrl@c000 { | |
| qcom,gpios-disallowed = <0x03 0x04 0x0b>; | |
| gpio-controller; | |
| interrupts = <0x02 0xc0 0x00 0x00 0x02 0xc1 0x00 0x00 0x02 0xc4 0x00 0x00 0x02 0xc5 0x00 0x00 0x02 0xc6 0x00 0x00 0x02 0xc7 0x00 0x00 0x02 0xc8 0x00 0x00 0x02 0xc9 0x00 0x00 0x02 0xcb 0x00 0x00>; | |
| compatible = "qcom,spmi-gpio"; | |
| interrupt-names = "pm8150b_gpio1\0pm8150b_gpio2\0pm8150b_gpio5\0pm8150b_gpio6\0pm8150b_gpio7\0pm8150b_gpio8\0pm8150b_gpio9\0pm8150b_gpio10\0pm8150b_gpio12"; | |
| reg = <0xc000 0xc00>; | |
| phandle = <0x626>; | |
| #gpio-cells = <0x02>; | |
| qnovo_fet_ctrl { | |
| qnovo_fet_ctrl_state1 { | |
| function = "normal"; | |
| pins = "gpio8"; | |
| bias-disable; | |
| phandle = <0x622>; | |
| output-disable; | |
| power-source = <0x00>; | |
| input-enable; | |
| }; | |
| qnovo_fet_ctrl_state2 { | |
| function = "normal"; | |
| pins = "gpio8"; | |
| bias-pull-down; | |
| phandle = <0x623>; | |
| output-disable; | |
| power-source = <0x00>; | |
| input-enable; | |
| }; | |
| }; | |
| smb_stat { | |
| smb_stat_default { | |
| function = "normal"; | |
| pins = "gpio6"; | |
| qcom,pull-up-strength = <0x00>; | |
| phandle = <0x69d>; | |
| bias-pull-up; | |
| power-source = <0x00>; | |
| input-enable; | |
| }; | |
| }; | |
| haptics_boost { | |
| haptics_boost_default { | |
| input-disable; | |
| function = "normal"; | |
| pins = "gpio5"; | |
| qcom,drive-strength = <0x03>; | |
| bias-disable; | |
| phandle = <0x636>; | |
| output-enable; | |
| power-source = <0x01>; | |
| }; | |
| }; | |
| }; | |
| qcom,usb-pdphy@1700 { | |
| vdd-pdphy-supply = <0x186>; | |
| interrupts = <0x02 0x17 0x00 0x01 0x02 0x17 0x01 0x01 0x02 0x17 0x02 0x01 0x02 0x17 0x03 0x01 0x02 0x17 0x04 0x01 0x02 0x17 0x05 0x01 0x02 0x17 0x06 0x01 0x02 0x17 0x07 0x01>; | |
| vconn-supply = <0x628>; | |
| vbus-supply = <0x627>; | |
| qcom,default-sink-caps = <0x1388 0xbb8 0x2328 0xbb8 0x2ee0 0x8ca>; | |
| compatible = "qcom,qpnp-pdphy"; | |
| interrupt-names = "sig-tx\0sig-rx\0msg-tx\0msg-rx\0msg-tx-failed\0msg-tx-discarded\0msg-rx-discarded\0fr-swap"; | |
| reg = <0x1700 0x100>; | |
| phandle = <0x637>; | |
| }; | |
| qcom,sdam-qnovo@b000 { | |
| pinctrl-names = "q_state1\0q_state2"; | |
| pinctrl-0 = <0x622>; | |
| interrupts = <0x02 0xb0 0x01 0x01>; | |
| compatible = "qcom,qpnp-qnovo5"; | |
| pinctrl-1 = <0x623>; | |
| interrupt-names = "ptrain-done"; | |
| reg = <0xb000 0x100>; | |
| phandle = <0x6ad>; | |
| }; | |
| adc_tm@3500 { | |
| #address-cells = <0x01>; | |
| interrupts = <0x02 0x35 0x00 0x01>; | |
| io-channels = <0x621 0x4f>; | |
| #size-cells = <0x00>; | |
| #thermal-sensor-cells = <0x01>; | |
| compatible = "qcom,adc-tm5"; | |
| interrupt-names = "thr-int-en"; | |
| qcom,pmic-revid = <0x624>; | |
| reg = <0x3500 0x100>; | |
| phandle = <0x6a0>; | |
| conn_therm@4f { | |
| qcom,ratiometric; | |
| reg = <0x4f>; | |
| qcom,hw-settle-time = <0xc8>; | |
| }; | |
| }; | |
| bcl@1d00 { | |
| interrupts = <0x02 0x1d 0x00 0x00 0x02 0x1d 0x01 0x00 0x02 0x1d 0x02 0x00>; | |
| #thermal-sensor-cells = <0x01>; | |
| compatible = "qcom,bcl-v5"; | |
| interrupt-names = "bcl-lvl0\0bcl-lvl1\0bcl-lvl2"; | |
| reg = <0x1d00 0x100>; | |
| phandle = <0x62e>; | |
| }; | |
| qcom,revid@100 { | |
| compatible = "qcom,qpnp-revid"; | |
| reg = <0x100 0x100>; | |
| phandle = <0x624>; | |
| }; | |
| qcom,temp-alarm@2400 { | |
| qcom,temperature-threshold-set = <0x01>; | |
| interrupts = <0x02 0x24 0x00 0x03>; | |
| io-channels = <0x621 0x06>; | |
| #thermal-sensor-cells = <0x00>; | |
| compatible = "qcom,spmi-temp-alarm"; | |
| reg = <0x2400 0x100>; | |
| phandle = <0x62d>; | |
| io-channel-names = "thermal"; | |
| }; | |
| bcl-soc { | |
| #thermal-sensor-cells = <0x00>; | |
| compatible = "qcom,msm-bcl-soc"; | |
| phandle = <0x62f>; | |
| }; | |
| }; | |
| qcom,pm8009@a { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,spmi-pmic"; | |
| reg = <0x0a 0x00>; | |
| qcom,power-on@800 { | |
| compatible = "qcom,qpnp-power-on"; | |
| reg = <0x800 0x100>; | |
| }; | |
| pinctrl@c000 { | |
| gpio-controller; | |
| interrupts = <0x0a 0xc0 0x00 0x00 0x0a 0xc1 0x00 0x00 0x0a 0xc2 0x00 0x00 0x0a 0xc3 0x00 0x00>; | |
| compatible = "qcom,spmi-gpio"; | |
| interrupt-names = "pm8009_gpio1\0pm8009_gpio2\0pm8009_gpio3\0pm8009_gpio4"; | |
| reg = <0xc000 0x400>; | |
| phandle = <0x635>; | |
| #gpio-cells = <0x02>; | |
| }; | |
| qcom,revid@100 { | |
| compatible = "qcom,qpnp-revid"; | |
| reg = <0x100 0x100>; | |
| }; | |
| }; | |
| qcom,pmxprairie@8 { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,spmi-pmic"; | |
| reg = <0x08 0x00>; | |
| qcom,power-on@800 { | |
| qcom,modem-reset; | |
| compatible = "qcom,qpnp-power-on"; | |
| reg = <0x800 0x100>; | |
| }; | |
| }; | |
| qcom,pm8150l@5 { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,spmi-pmic"; | |
| reg = <0x05 0x00>; | |
| qcom,pwms@bc00 { | |
| qcom,num-lpg-channels = <0x02>; | |
| reg-names = "lpg-base"; | |
| #pwm-cells = <0x02>; | |
| compatible = "qcom,pwm-lpg"; | |
| reg = <0xbc00 0x200>; | |
| phandle = <0x6ca>; | |
| }; | |
| qcom,amoled { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| compatible = "qcom,qpnp-amoled-regulator"; | |
| status = "ok"; | |
| phandle = <0x6cc>; | |
| ab@de00 { | |
| regulator-max-microvolt = <0x5d1420>; | |
| reg-names = "ab_base"; | |
| regulator-min-microvolt = <0x4630c0>; | |
| regulator-name = "ab"; | |
| reg = <0xde00 0x100>; | |
| phandle = <0x63d>; | |
| qcom,swire-control; | |
| }; | |
| oledb@e000 { | |
| regulator-max-microvolt = <0x7b98a0>; | |
| reg-names = "oledb_base"; | |
| regulator-min-microvolt = <0x4b2648>; | |
| regulator-name = "oledb"; | |
| reg = <0xe000 0x100>; | |
| phandle = <0x6cd>; | |
| qcom,swire-control; | |
| }; | |
| ibb@dc00 { | |
| regulator-max-microvolt = <0x5265c0>; | |
| reg-names = "ibb_base"; | |
| regulator-min-microvolt = "\0\f5"; | |
| regulator-name = "ibb"; | |
| reg = <0xdc00 0x100>; | |
| phandle = <0x63e>; | |
| qcom,swire-control; | |
| }; | |
| }; | |
| qcom,lcdb@ec00 { | |
| interrupts = <0x05 0xec 0x01 0x01>; | |
| qcom,voltage-step-ramp; | |
| compatible = "qcom,qpnp-lcdb-regulator"; | |
| status = "disabled"; | |
| interrupt-names = "sc-irq"; | |
| qcom,pmic-revid = <0x631>; | |
| reg = <0xec00 0x100>; | |
| phandle = <0x6bc>; | |
| bst { | |
| regulator-max-microvolt = <0x5fbfb8>; | |
| label = "bst"; | |
| regulator-min-microvolt = <0x47b760>; | |
| regulator-name = "lcdb_bst"; | |
| phandle = <0x6bf>; | |
| }; | |
| ldo { | |
| regulator-max-microvolt = <0x5b8d80>; | |
| label = "ldo"; | |
| regulator-min-microvolt = "\0=\t"; | |
| regulator-name = "lcdb_ldo"; | |
| phandle = <0x6bd>; | |
| }; | |
| ncp { | |
| regulator-max-microvolt = <0x5b8d80>; | |
| label = "ncp"; | |
| regulator-min-microvolt = "\0=\t"; | |
| regulator-name = "lcdb_ncp"; | |
| phandle = <0x6be>; | |
| }; | |
| }; | |
| qcom,leds@d000 { | |
| compatible = "qcom,tri-led"; | |
| reg = <0xd000 0x100>; | |
| phandle = <0x6cb>; | |
| green { | |
| linux,default-trigger = "timer"; | |
| label = "green"; | |
| led-sources = <0x01>; | |
| pwms = <0x632 0x01 0xf4240>; | |
| }; | |
| red { | |
| linux,default-trigger = "timer"; | |
| label = "red"; | |
| led-sources = <0x00>; | |
| pwms = <0x632 0x00 0xf4240>; | |
| }; | |
| blue { | |
| linux,default-trigger = "timer"; | |
| label = "blue"; | |
| led-sources = <0x02>; | |
| pwms = <0x632 0x02 0xf4240>; | |
| }; | |
| }; | |
| qcom,leds@d300 { | |
| qcom,hdrm-auto-mode; | |
| qcom,open-circuit-det; | |
| qcom,vph-droop-det; | |
| interrupts = <0x05 0xd3 0x00 0x01 0x05 0xd3 0x03 0x01 0x05 0xd3 0x04 0x01>; | |
| label = "flash"; | |
| compatible = "qcom,qpnp-flash-led-v2"; | |
| status = "okay"; | |
| interrupt-names = "led-fault-irq\0all-ramp-down-done-irq\0all-ramp-up-done-irq"; | |
| qcom,thermal-derate-en; | |
| qcom,pmic-revid = <0x631>; | |
| reg = <0xd300 0x100>; | |
| phandle = <0x6c0>; | |
| qcom,short-circuit-det; | |
| qcom,thermal-derate-current = <0xc8 0x1f4 0x3e8>; | |
| qcom,isc-delay = <0xc0>; | |
| qcom,torch_2 { | |
| qcom,led-name = "led:torch_2"; | |
| qcom,ires-ua = <0x30d4>; | |
| qcom,id = <0x02>; | |
| qcom,current-ma = <0x12c>; | |
| qcom,hdrm-vol-hi-lo-win-mv = <0x64>; | |
| label = "torch"; | |
| status = "disabled"; | |
| qcom,hdrm-voltage-mv = <0x145>; | |
| phandle = <0x6c2>; | |
| qcom,max-current = <0x1f4>; | |
| qcom,default-led-trigger = "torch2_trigger"; | |
| }; | |
| qcom,flash_1 { | |
| qcom,led-name = "led:flash_1"; | |
| qcom,ires-ua = <0x30d4>; | |
| qcom,id = <0x01>; | |
| qcom,current-ma = <0x3e8>; | |
| qcom,duration-ms = <0x500>; | |
| qcom,hdrm-vol-hi-lo-win-mv = <0x64>; | |
| label = "flash"; | |
| qcom,hdrm-voltage-mv = <0x145>; | |
| phandle = <0x647>; | |
| qcom,max-current = <0x5dc>; | |
| qcom,default-led-trigger = "flash1_trigger"; | |
| }; | |
| qcom,led_switch_3 { | |
| qcom,led-name = "led:switch_3"; | |
| qcom,led-mask = <0x04>; | |
| label = "switch"; | |
| phandle = <0x6c5>; | |
| qcom,default-led-trigger = "switch3_trigger"; | |
| }; | |
| qcom,torch_0 { | |
| qcom,led-name = "led:torch_0"; | |
| qcom,ires-ua = <0x30d4>; | |
| qcom,id = <0x00>; | |
| qcom,current-ma = <0x12c>; | |
| qcom,hdrm-vol-hi-lo-win-mv = <0x64>; | |
| label = "torch"; | |
| qcom,hdrm-voltage-mv = <0x145>; | |
| phandle = <0x648>; | |
| qcom,max-current = <0x1f4>; | |
| qcom,default-led-trigger = "torch0_trigger"; | |
| }; | |
| qcom,led_switch_1 { | |
| qcom,led-name = "led:switch_1"; | |
| qcom,led-mask = <0x02>; | |
| label = "switch"; | |
| phandle = <0x6c4>; | |
| qcom,default-led-trigger = "switch1_trigger"; | |
| }; | |
| qcom,flash_2 { | |
| qcom,led-name = "led:flash_2"; | |
| qcom,ires-ua = <0x30d4>; | |
| qcom,id = <0x02>; | |
| qcom,current-ma = <0x1f4>; | |
| qcom,duration-ms = <0x500>; | |
| qcom,hdrm-vol-hi-lo-win-mv = <0x64>; | |
| label = "flash"; | |
| status = "disabled"; | |
| qcom,hdrm-voltage-mv = <0x145>; | |
| phandle = <0x6c1>; | |
| qcom,max-current = <0x2ee>; | |
| qcom,default-led-trigger = "flash2_trigger"; | |
| }; | |
| qcom,torch_1 { | |
| qcom,led-name = "led:torch_1"; | |
| qcom,ires-ua = <0x30d4>; | |
| qcom,id = <0x01>; | |
| qcom,current-ma = <0x12c>; | |
| qcom,hdrm-vol-hi-lo-win-mv = <0x64>; | |
| label = "torch"; | |
| qcom,hdrm-voltage-mv = <0x145>; | |
| phandle = <0x649>; | |
| qcom,max-current = <0x1f4>; | |
| qcom,default-led-trigger = "torch1_trigger"; | |
| }; | |
| qcom,flash_0 { | |
| qcom,led-name = "led:flash_0"; | |
| qcom,ires-ua = <0x30d4>; | |
| qcom,id = <0x00>; | |
| qcom,current-ma = <0x3e8>; | |
| qcom,duration-ms = <0x500>; | |
| qcom,hdrm-vol-hi-lo-win-mv = <0x64>; | |
| label = "flash"; | |
| qcom,hdrm-voltage-mv = <0x145>; | |
| phandle = <0x646>; | |
| qcom,max-current = <0x5dc>; | |
| qcom,default-led-trigger = "flash0_trigger"; | |
| }; | |
| qcom,led_switch_2 { | |
| qcom,led-name = "led:switch_2"; | |
| qcom,led-mask = <0x03>; | |
| label = "switch"; | |
| phandle = <0x64a>; | |
| qcom,default-led-trigger = "switch2_trigger"; | |
| }; | |
| qcom,led_switch_0 { | |
| qcom,led-name = "led:switch_0"; | |
| qcom,led-mask = <0x01>; | |
| label = "switch"; | |
| phandle = <0x6c3>; | |
| qcom,default-led-trigger = "switch0_trigger"; | |
| }; | |
| }; | |
| qcom,pwms@b100 { | |
| qcom,num-lpg-channels = <0x03>; | |
| reg-names = "lpg-base\0lut-base"; | |
| #pwm-cells = <0x02>; | |
| compatible = "qcom,pwm-lpg"; | |
| qcom,lut-patterns = <0x00 0x0a 0x14 0x1e 0x28 0x32 0x3c 0x46 0x50 0x5a 0x64 0x5a 0x50 0x46 0x3c 0x32 0x28 0x1e 0x14 0x0a 0x00>; | |
| reg = <0xb100 0x300 0xb000 0x100>; | |
| phandle = <0x632>; | |
| lpg3 { | |
| qcom,ramp-pattern-repeat; | |
| qcom,ramp-pause-hi-count = <0x02>; | |
| qcom,ramp-step-ms = <0x64>; | |
| qcom,ramp-from-low-to-high; | |
| qcom,ramp-low-index = <0x00>; | |
| qcom,ramp-high-index = <0x14>; | |
| qcom,lpg-chan-id = <0x03>; | |
| qcom,ramp-pause-lo-count = <0x02>; | |
| }; | |
| lpg1 { | |
| qcom,ramp-pattern-repeat; | |
| qcom,ramp-pause-hi-count = <0x02>; | |
| qcom,ramp-step-ms = <0x64>; | |
| qcom,ramp-from-low-to-high; | |
| qcom,ramp-low-index = <0x00>; | |
| qcom,ramp-high-index = <0x14>; | |
| qcom,lpg-chan-id = <0x01>; | |
| qcom,ramp-pause-lo-count = <0x02>; | |
| }; | |
| lpg2 { | |
| qcom,ramp-pattern-repeat; | |
| qcom,ramp-pause-hi-count = <0x02>; | |
| qcom,ramp-step-ms = <0x64>; | |
| qcom,ramp-from-low-to-high; | |
| qcom,ramp-low-index = <0x00>; | |
| qcom,ramp-high-index = <0x14>; | |
| qcom,lpg-chan-id = <0x02>; | |
| qcom,ramp-pause-lo-count = <0x02>; | |
| }; | |
| }; | |
| qcom,wled@d800 { | |
| reg-names = "wled-ctrl-base\0wled-sink-base"; | |
| interrupts = <0x05 0xd8 0x01 0x01 0x05 0xd8 0x04 0x03 0x05 0xd8 0x05 0x03>; | |
| label = "backlight"; | |
| qcom,auto-calibration; | |
| compatible = "qcom,pm8150l-spmi-wled"; | |
| status = "disabled"; | |
| interrupt-names = "ovp-irq\0pre-flash-irq\0flash-irq"; | |
| qcom,pmic-revid = <0x631>; | |
| reg = <0xd800 0x100 0xd900 0x100>; | |
| phandle = <0x6c6>; | |
| qcom,wled-torch { | |
| label = "torch"; | |
| phandle = <0x6c8>; | |
| qcom,wled-torch-timer = <0x4b0>; | |
| qcom,default-led-trigger = "wled_torch"; | |
| }; | |
| qcom,wled-switch { | |
| label = "switch"; | |
| phandle = <0x6c9>; | |
| qcom,default-led-trigger = "wled_switch"; | |
| }; | |
| qcom,wled-flash { | |
| label = "flash"; | |
| phandle = <0x6c7>; | |
| qcom,default-led-trigger = "wled_flash"; | |
| }; | |
| }; | |
| }; | |
| qcom,pm8150@1 { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,spmi-pmic"; | |
| reg = <0x01 0x00>; | |
| }; | |
| qcom,pm8150b@3 { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,spmi-pmic"; | |
| reg = <0x03 0x00>; | |
| qcom,haptics@c000 { | |
| qcom,lra-auto-resonance-mode = "qwd"; | |
| qcom,lra-allow-variable-play-rate; | |
| qcom,vmax-mv = <0xe10>; | |
| interrupts = <0x03 0xc0 0x00 0x03 0x03 0xc0 0x01 0x03>; | |
| qcom,lra-resonance-sig-shape = "sine"; | |
| vdd-supply = <0x62c>; | |
| compatible = "qcom,haptics"; | |
| interrupt-names = "hap-sc-irq\0hap-play-irq"; | |
| reg = <0xc000 0x100>; | |
| phandle = <0x6b1>; | |
| qcom,actuator-type = "erm"; | |
| qcom,play-rate-us = <0x1a0b>; | |
| wf_5 { | |
| qcom,wf-s-repeat-count = <0x01>; | |
| qcom,wf-play-rate-us = <0x1a0b>; | |
| qcom,wf-brake-pattern = <0x00>; | |
| qcom,effect-id = <0x05>; | |
| qcom,wf-pattern = <0x3e3e3e3e 0x3e3e3e3e>; | |
| qcom,wf-vmax-mv = <0xe10>; | |
| qcom,lra-auto-resonance-disable; | |
| qcom,wf-repeat-count = <0x01>; | |
| }; | |
| wf_3 { | |
| qcom,wf-s-repeat-count = <0x01>; | |
| qcom,wf-play-rate-us = <0x1a0b>; | |
| qcom,wf-brake-pattern = <0x00>; | |
| qcom,effect-id = <0x03>; | |
| qcom,wf-pattern = <0x3e3e3e3e 0x3e3e3e3e>; | |
| qcom,wf-vmax-mv = <0xe10>; | |
| qcom,lra-auto-resonance-disable; | |
| qcom,wf-repeat-count = <0x01>; | |
| }; | |
| wf_1 { | |
| qcom,wf-s-repeat-count = <0x01>; | |
| qcom,wf-play-rate-us = <0x1a0b>; | |
| qcom,wf-brake-pattern = <0x00>; | |
| qcom,effect-id = <0x01>; | |
| qcom,wf-pattern = <0x3e3e3e3e 0x3e3e3e3e>; | |
| qcom,wf-vmax-mv = <0xe10>; | |
| qcom,lra-auto-resonance-disable; | |
| qcom,wf-repeat-count = <0x01>; | |
| }; | |
| wf_4 { | |
| qcom,wf-s-repeat-count = <0x01>; | |
| qcom,wf-play-rate-us = <0x1a0b>; | |
| qcom,wf-brake-pattern = <0x00>; | |
| qcom,effect-id = <0x04>; | |
| qcom,wf-pattern = <0x3e3e3e3e 0x3e3e3e3e>; | |
| qcom,wf-vmax-mv = <0xe10>; | |
| qcom,lra-auto-resonance-disable; | |
| qcom,wf-repeat-count = <0x01>; | |
| }; | |
| wf_2 { | |
| qcom,wf-s-repeat-count = <0x01>; | |
| qcom,wf-play-rate-us = <0x1a0b>; | |
| qcom,wf-brake-pattern = <0x00>; | |
| qcom,effect-id = <0x02>; | |
| qcom,wf-pattern = <0x3e3e3e3e 0x3e3e3e3e>; | |
| qcom,wf-vmax-mv = <0xe10>; | |
| qcom,lra-auto-resonance-disable; | |
| qcom,wf-repeat-count = <0x01>; | |
| }; | |
| wf_0 { | |
| qcom,wf-s-repeat-count = <0x01>; | |
| qcom,wf-play-rate-us = <0x1a0b>; | |
| qcom,wf-brake-pattern = <0x00>; | |
| qcom,effect-id = <0x00>; | |
| qcom,wf-pattern = <0x3e3e3e3e 0x3e3e3e3e>; | |
| qcom,wf-vmax-mv = <0xe10>; | |
| qcom,lra-auto-resonance-disable; | |
| qcom,wf-repeat-count = <0x01>; | |
| }; | |
| }; | |
| qcom,leds@d000 { | |
| nvmem-names = "pbs_sdam"; | |
| compatible = "qcom,tri-led"; | |
| nvmem = <0x62a>; | |
| reg = <0xd000 0x100>; | |
| phandle = <0x6b0>; | |
| hr_led2 { | |
| label = "hr_led2"; | |
| led-sources = <0x01>; | |
| pwms = <0x62b 0x01 0xf4240>; | |
| }; | |
| hr_led1 { | |
| label = "hr_led1"; | |
| led-sources = <0x00>; | |
| pwms = <0x62b 0x00 0xf4240>; | |
| }; | |
| }; | |
| qcom,pwms@b100 { | |
| qcom,num-lpg-channels = <0x02>; | |
| reg-names = "lpg-base"; | |
| #pwm-cells = <0x02>; | |
| compatible = "qcom,pwm-lpg"; | |
| reg = <0xb100 0x200>; | |
| phandle = <0x62b>; | |
| }; | |
| }; | |
| qcom,pm8009@b { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,spmi-pmic"; | |
| reg = <0x0b 0x00>; | |
| }; | |
| qcom,pmxprairie@9 { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,spmi-pmic"; | |
| reg = <0x09 0x00>; | |
| }; | |
| }; | |
| qcom,msm-ultra-low-latency { | |
| qcom,msm-pcm-dsp-id = <0x02>; | |
| qcom,latency-level = "ultra"; | |
| compatible = "qcom,msm-pcm-dsp"; | |
| phandle = <0x2e2>; | |
| qcom,msm-pcm-low-latency; | |
| }; | |
| lenovo,hardware_info { | |
| compatible = "lenovo,hardware_info"; | |
| status = "ok"; | |
| }; | |
| qcom,qup_uart@88c000 { | |
| pinctrl-names = "default\0sleep"; | |
| pinctrl-0 = <0x2bc 0x2bd 0x2be>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| reg-names = "se_phys"; | |
| clocks = <0x16 0x7e 0x16 0x88 0x16 0x89>; | |
| qcom,wrapper-core = <0x2bf>; | |
| interrupts-extended = <0x01 0x00 0x249 0x04 0x66 0x37 0x00>; | |
| compatible = "qcom,msm-geni-serial-hs"; | |
| pinctrl-1 = <0x2bc 0x2bd 0x2be>; | |
| status = "disabled"; | |
| reg = <0x88c000 0x4000>; | |
| phandle = <0x5bd>; | |
| qcom,wakeup-byte = <0xfd>; | |
| }; | |
| kgsl_iommu_coherent_test_device { | |
| iommus = <0x181 0x09 0x00>; | |
| dma-coherent; | |
| compatible = "iommu-debug-test"; | |
| status = "disabled"; | |
| qcom,iommu-dma = "disabled"; | |
| }; | |
| qcom,msm-dai-q6 { | |
| compatible = "qcom,msm-dai-q6"; | |
| qcom,msm-dai-q6-int-fm-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x3004>; | |
| phandle = <0x5d6>; | |
| }; | |
| qcom,msm-dai-q6-usb-audio-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x7000>; | |
| phandle = <0x305>; | |
| }; | |
| qcom,msm-dai-q6-sb-8-tx { | |
| qcom,msm-dai-q6-slim-dev-id = <0x00>; | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x4011>; | |
| phandle = <0x5d3>; | |
| }; | |
| qcom,msm-dai-q6-incall-record-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x8004>; | |
| phandle = <0x300>; | |
| }; | |
| qcom,msm-dai-q6-incall-record-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x8003>; | |
| phandle = <0x2ff>; | |
| }; | |
| qcom,msm-dai-q6-incall-music-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x8005>; | |
| phandle = <0x301>; | |
| }; | |
| qcom,msm-dai-q6-incall-music-2-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x8002>; | |
| phandle = <0x302>; | |
| }; | |
| qcom,msm-dai-q6-proxy-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x2003>; | |
| phandle = <0x304>; | |
| }; | |
| qcom,msm-dai-q6-sb-7-tx { | |
| qcom,msm-dai-q6-slim-dev-id = <0x00>; | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x400f>; | |
| phandle = <0x308>; | |
| }; | |
| qcom,msm-dai-q6-proxy-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x2002>; | |
| phandle = <0x303>; | |
| }; | |
| qcom,msm-dai-q6-sb-7-rx { | |
| qcom,msm-dai-q6-slim-dev-id = <0x00>; | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x400e>; | |
| phandle = <0x307>; | |
| }; | |
| qcom,msm-dai-q6-be-afe-pcm-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0xe1>; | |
| phandle = <0x2fc>; | |
| }; | |
| qcom,msm-dai-q6-be-afe-pcm-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0xe0>; | |
| phandle = <0x2fb>; | |
| }; | |
| qcom,msm-dai-q6-bt-sco-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x3001>; | |
| phandle = <0x5d5>; | |
| }; | |
| qcom,msm-dai-q6-bt-sco-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x3000>; | |
| phandle = <0x5d4>; | |
| }; | |
| qcom,msm-dai-q6-afe-proxy-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0xf0>; | |
| phandle = <0x2fe>; | |
| }; | |
| qcom,msm-dai-q6-int-fm-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x3005>; | |
| phandle = <0x5d7>; | |
| }; | |
| qcom,msm-dai-q6-afe-proxy-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0xf1>; | |
| phandle = <0x2fd>; | |
| }; | |
| qcom,msm-dai-q6-usb-audio-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x7001>; | |
| phandle = <0x306>; | |
| }; | |
| }; | |
| qcom,gdsc@9981004 { | |
| clock-names = "ahb_clk"; | |
| qcom,retain-regs; | |
| clocks = <0x16 0x2b>; | |
| regulator-name = "npu_core_gdsc"; | |
| compatible = "qcom,gdsc"; | |
| reg = <0x9981004 0x04>; | |
| phandle = <0x1de>; | |
| }; | |
| msm_cdc_pinctrl@32 { | |
| pinctrl-names = "aud_active\0aud_sleep"; | |
| pinctrl-0 = <0x467>; | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| pinctrl-1 = <0x468>; | |
| phandle = <0x65d>; | |
| }; | |
| funnel@6ac2000 { | |
| arm,primecell-periphid = <0xbb908>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "funnel-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-funnel-dl-north"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6ac2000 0x1000>; | |
| phandle = <0x4f8>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x1d8>; | |
| phandle = <0x1ac>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x00>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x1d9>; | |
| phandle = <0x1d1>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| va_core_clk { | |
| qcom,codec-ext-clk-src = <0x02>; | |
| #clock-cells = <0x01>; | |
| compatible = "qcom,audio-ref-clk"; | |
| phandle = <0x659>; | |
| qcom,codec-lpass-clk-id = <0x30b>; | |
| qcom,codec-lpass-ext-clk-freq = <0x124f800>; | |
| }; | |
| qcom,pcie2_msi@17a10040 { | |
| interrupts = <0x00 0x340 0x01 0x00 0x341 0x01 0x00 0x342 0x01 0x00 0x343 0x01 0x00 0x344 0x01 0x00 0x345 0x01 0x00 0x346 0x01 0x00 0x347 0x01 0x00 0x348 0x01 0x00 0x349 0x01 0x00 0x34a 0x01 0x00 0x34b 0x01 0x00 0x34c 0x01 0x00 0x34d 0x01 0x00 0x34e 0x01 0x00 0x34f 0x01 0x00 0x350 0x01 0x00 0x351 0x01 0x00 0x352 0x01 0x00 0x353 0x01 0x00 0x354 0x01 0x00 0x355 0x01 0x00 0x356 0x01 0x00 0x357 0x01 0x00 0x358 0x01 0x00 0x359 0x01 0x00 0x35a 0x01 0x00 0x35b 0x01 0x00 0x35c 0x01 0x00 0x35d 0x01 0x00 0x35e 0x01 0x00 0x35f 0x01>; | |
| interrupt-parent = <0x01>; | |
| msi-controller; | |
| compatible = "qcom,pci-msi"; | |
| reg = <0x17a10040 0x00>; | |
| phandle = <0x174>; | |
| }; | |
| tpda@6004000 { | |
| arm,primecell-periphid = <0xbb969>; | |
| qcom,cmb-elem-size = <0x07 0x40 0x0d 0x20 0x0f 0x20 0x10 0x20 0x11 0x20 0x12 0x40 0x14 0x40 0x15 0x40 0x16 0x20 0x17 0x20 0x19 0x40>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpda-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-tpda"; | |
| qcom,dsb-elem-size = <0x01 0x20 0x06 0x20 0x07 0x20 0x0a 0x20 0x0b 0x20 0x0c 0x20 0x0d 0x20 0x0e 0x20 0x10 0x20 0x13 0x20 0x18 0x20 0x19 0x20>; | |
| qcom,tc-elem-size = <0x10 0x20 0x19 0x20>; | |
| compatible = "arm,primecell"; | |
| qcom,tpda-atid = <0x41>; | |
| qcom,bc-elem-size = <0x10 0x20 0x18 0x20 0x19 0x20>; | |
| reg = <0x6004000 0x1000>; | |
| phandle = <0x4ec>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x1b3>; | |
| phandle = <0x231>; | |
| }; | |
| }; | |
| port@14 { | |
| reg = <0x13>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x1c1>; | |
| phandle = <0x1fa>; | |
| }; | |
| }; | |
| port@9 { | |
| reg = <0x0e>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x1bc>; | |
| phandle = <0x1f0>; | |
| }; | |
| }; | |
| port@12 { | |
| reg = <0x11>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x1bf>; | |
| phandle = <0x1f6>; | |
| }; | |
| }; | |
| port@7 { | |
| reg = <0x0c>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x1ba>; | |
| phandle = <0x1ec>; | |
| }; | |
| }; | |
| port@20 { | |
| reg = <0x19>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x1c7>; | |
| phandle = <0x1cb>; | |
| }; | |
| }; | |
| port@10 { | |
| reg = <0x0f>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x1bd>; | |
| phandle = <0x1f2>; | |
| }; | |
| }; | |
| port@5 { | |
| reg = <0x0a>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x1b8>; | |
| phandle = <0x1e8>; | |
| }; | |
| }; | |
| port@19 { | |
| reg = <0x18>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x1c6>; | |
| phandle = <0x207>; | |
| }; | |
| }; | |
| port@3 { | |
| reg = <0x07>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x1b6>; | |
| phandle = <0x1e4>; | |
| }; | |
| }; | |
| port@17 { | |
| reg = <0x16>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x1c4>; | |
| phandle = <0x1c8>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x1b4>; | |
| phandle = <0x1b0>; | |
| }; | |
| }; | |
| port@15 { | |
| reg = <0x14>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x1c2>; | |
| phandle = <0x1fc>; | |
| }; | |
| }; | |
| port@13 { | |
| reg = <0x12>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x1c0>; | |
| phandle = <0x1f8>; | |
| }; | |
| }; | |
| port@8 { | |
| reg = <0x0d>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x1bb>; | |
| phandle = <0x1ee>; | |
| }; | |
| }; | |
| port@11 { | |
| reg = <0x10>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x1be>; | |
| phandle = <0x1f4>; | |
| }; | |
| }; | |
| port@6 { | |
| reg = <0x0b>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x1b9>; | |
| phandle = <0x1ea>; | |
| }; | |
| }; | |
| port@4 { | |
| reg = <0x09>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x1b7>; | |
| phandle = <0x1e6>; | |
| }; | |
| }; | |
| port@18 { | |
| reg = <0x17>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x1c5>; | |
| phandle = <0x1ca>; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x06>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x1b5>; | |
| phandle = <0x1e2>; | |
| }; | |
| }; | |
| port@16 { | |
| reg = <0x15>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x1c3>; | |
| phandle = <0x1c9>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,msm-quin-auxpcm { | |
| qcom,msm-cpudai-auxpcm-quant = <0x02 0x02>; | |
| qcom,msm-cpudai-auxpcm-frame = <0x05 0x04>; | |
| qcom,msm-cpudai-auxpcm-sync = <0x01 0x01>; | |
| qcom,msm-auxpcm-interface = "quinary"; | |
| qcom,msm-cpudai-auxpcm-slot-mapping = <0x01 0x01>; | |
| qcom,msm-cpudai-auxpcm-data = <0x00 0x00>; | |
| qcom,msm-cpudai-afe-clk-ver = <0x02>; | |
| qcom,msm-cpudai-auxpcm-num-slots = <0x01 0x01>; | |
| compatible = "qcom,msm-auxpcm-dev"; | |
| qcom,msm-cpudai-auxpcm-mode = <0x00 0x00>; | |
| phandle = <0x2f9>; | |
| qcom,msm-cpudai-auxpcm-pcm-clk-rate = <0x1f4000 0x1f4000>; | |
| }; | |
| cti@6b03000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti-swao_cti3"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6b03000 0x1000>; | |
| phandle = <0x192>; | |
| }; | |
| i2c@884000 { | |
| pinctrl-names = "default\0sleep"; | |
| #address-cells = <0x01>; | |
| pinctrl-0 = <0x2c5>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| interrupts = <0x00 0x247 0x04>; | |
| clocks = <0x16 0x7a 0x16 0x88 0x16 0x89>; | |
| #size-cells = <0x00>; | |
| qcom,wrapper-core = <0x2bf>; | |
| dma-names = "tx\0rx"; | |
| compatible = "qcom,i2c-geni"; | |
| pinctrl-1 = <0x2c6>; | |
| status = "ok"; | |
| reg = <0x884000 0x4000>; | |
| phandle = <0x5c0>; | |
| dmas = <0x2c2 0x00 0x01 0x03 0x40 0x00 0x2c2 0x01 0x01 0x03 0x40 0x00>; | |
| qcom,smb1390@10 { | |
| pinctrl-names = "default"; | |
| #address-cells = <0x01>; | |
| pinctrl-0 = <0x69d>; | |
| interrupts = <0x02 0xc5 0x00 0x08>; | |
| interrupt_names = "smb1390"; | |
| #size-cells = <0x00>; | |
| interrupt-parent = <0x376>; | |
| compatible = "qcom,i2c-pmic"; | |
| #interrupt-cells = <0x03>; | |
| status = "ok"; | |
| reg = <0x10>; | |
| qcom,periph-map = <0x10>; | |
| phandle = <0x69f>; | |
| interrupt-controller; | |
| qcom,charge_pump { | |
| qcom,min-ilim-ua = <0xf4240>; | |
| qcom,max-cutoff-soc = <0x50>; | |
| qcom,parallel-output-mode = <0x02>; | |
| io-channels = <0x621 0x0e>; | |
| interrupt-parent = <0x69f>; | |
| compatible = "qcom,smb1390-charger-psy"; | |
| status = "ok"; | |
| qcom,pmic-revid = <0x69e>; | |
| phandle = <0x747>; | |
| io-channel-names = "cp_die_temp"; | |
| qcom,core { | |
| interrupts = <0x10 0x00 0x03 0x10 0x01 0x03 0x10 0x02 0x03 0x10 0x03 0x03 0x10 0x04 0x03 0x10 0x05 0x01 0x10 0x06 0x01 0x10 0x07 0x01>; | |
| interrupt-names = "switcher-off-window\0switcher-off-fault\0tsd-fault\0irev-fault\0vph-ov-hard\0vph-ov-soft\0ilim\0temp-alarm"; | |
| }; | |
| }; | |
| qcom,revid@100 { | |
| compatible = "qcom,qpnp-revid"; | |
| reg = <0x100>; | |
| phandle = <0x69e>; | |
| }; | |
| }; | |
| fsa4480@43 { | |
| compatible = "qcom,fsa4480-i2c"; | |
| reg = <0x43>; | |
| phandle = <0x32c>; | |
| }; | |
| qcom,smb1390_slave@18 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,i2c-pmic"; | |
| status = "disabled"; | |
| reg = <0x18>; | |
| qcom,periph-map = <0x10>; | |
| phandle = <0x748>; | |
| qcom,charge_pump_slave { | |
| compatible = "qcom,smb1390-slave"; | |
| status = "disabled"; | |
| phandle = <0x749>; | |
| }; | |
| }; | |
| nq@64 { | |
| fmint-gpio = <0x66 0x33 0x00>; | |
| rtc6226,vdd-supply-voltage = "\02K\0\02K"; | |
| rtc6226,vio-supply-voltage = <0x1b7740 0x1b7740>; | |
| vdd-supply = <0x2c9>; | |
| compatible = "rtc6226"; | |
| reg = <0x64>; | |
| vio-supply = <0xa9>; | |
| }; | |
| es7210@40 { | |
| vd-supply = <0x2c7>; | |
| vp-supply = <0x2c8>; | |
| compatible = "es7210"; | |
| reg = <0x40>; | |
| phandle = <0x5c1>; | |
| }; | |
| halo,hl6111r@25 { | |
| compatible = "halo,hl6111r"; | |
| status = "ok"; | |
| reg = <0x25>; | |
| }; | |
| }; | |
| ufshc@1d84000 { | |
| vcc-low-voltage-sup; | |
| vcc-max-microamp = "\0\f5"; | |
| pinctrl-names = "dev-reset-assert\0dev-reset-deassert"; | |
| freq-table-hz = <0x23c3460 0x11e1a300 0x00 0x00 0x00 0x00 0x23c3460 0x11e1a300 0x23c3460 0x11e1a300 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; | |
| qcom,pm-qos-cpu-group-latency-us = <0x2c 0x2c>; | |
| phy-names = "ufsphy"; | |
| pinctrl-0 = <0x78>; | |
| clock-names = "core_clk\0bus_aggr_clk\0iface_clk\0core_clk_unipro\0core_clk_ice\0ref_clk\0tx_lane0_sync_clk\0rx_lane0_sync_clk\0rx_lane1_sync_clk"; | |
| reg-names = "ufs_mem\0ufs_ice"; | |
| qcom,bus-vector-names = "MIN\0PWM_G1_L1\0PWM_G2_L1\0PWM_G3_L1\0PWM_G4_L1\0PWM_G1_L2\0PWM_G2_L2\0PWM_G3_L2\0PWM_G4_L2\0HS_RA_G1_L1\0HS_RA_G2_L1\0HS_RA_G3_L1\0HS_RA_G4_L1\0HS_RA_G1_L2\0HS_RA_G2_L2\0HS_RA_G3_L2\0HS_RA_G4_L2\0HS_RB_G1_L1\0HS_RB_G2_L1\0HS_RB_G3_L1\0HS_RB_G4_L1\0HS_RB_G1_L2\0HS_RB_G2_L2\0HS_RB_G3_L2\0HS_RB_G4_L2\0MAX"; | |
| vcc-voltage-level = <0x263540 0x2d0370>; | |
| qcom,msm-bus,name = "ufshc_mem"; | |
| lanes-per-direction = <0x02>; | |
| qcom,vddp-ref-clk-max-microamp = <0x64>; | |
| resets = <0x16 0x21>; | |
| interrupts = <0x00 0x109 0x04>; | |
| clocks = <0x16 0xa7 0x16 0x06 0x16 0xa6 0x16 0xb3 0x16 0xaa 0x15 0x00 0x16 0xb2 0x16 0xb0 0x16 0xb1>; | |
| dev-ref-clk-freq = <0x00>; | |
| qcom,vccq-parent-max-microamp = <0x33450>; | |
| vccq2-supply = <0xa9>; | |
| qcom,msm-bus,num-paths = <0x02>; | |
| qcom,msm-bus,num-cases = <0x1a>; | |
| vdd-hba-fixed-regulator; | |
| qcom,pm-qos-cpu-groups = <0x0f 0xf0>; | |
| qcom,vccq-parent-supply = <0xab>; | |
| compatible = "qcom,ufshc"; | |
| pinctrl-1 = <0x79>; | |
| status = "ok"; | |
| phys = <0x77>; | |
| vdd-hba-supply = <0x374>; | |
| reg = <0x1d84000 0x3000 0x1d90000 0x8000>; | |
| phandle = <0x378>; | |
| vccq-max-microamp = "\0\f5"; | |
| qcom,msm-bus,vectors-KBps = <0x7b 0x200 0x00 0x00 0x01 0x2f5 0x00 0x00 0x7b 0x200 0x39a 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x734 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0xe68 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x1cd0 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x734 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0xe68 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x1cd0 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x39a0 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x1f334 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x3e667 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x200000 0x00 0x01 0x2f5 0x19000 0x00 0x7b 0x200 0x400000 0x00 0x01 0x2f5 0x32000 0x00 0x7b 0x200 0x3e667 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x7cccd 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x400000 0x00 0x01 0x2f5 0x32000 0x00 0x7b 0x200 0x800000 0x00 0x01 0x2f5 0x64000 0x00 0x7b 0x200 0x247ae 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x48ccd 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x200000 0x00 0x01 0x2f5 0x19000 0x00 0x7b 0x200 0x400000 0x00 0x01 0x2f5 0x32000 0x00 0x7b 0x200 0x48ccd 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x9199a 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x400000 0x00 0x01 0x2f5 0x32000 0x64000 0x7b 0x200 0x800000 0x00 0x01 0x2f5 0x64000 0x64000 0x7b 0x200 0x74a000 0x00 0x01 0x2f5 0x4b000 0x00>; | |
| vccq2-max-microamp = "\0\f5"; | |
| reset-names = "core_reset"; | |
| vccq-supply = <0x37c>; | |
| vcc-supply = <0x380>; | |
| qcom,pm-qos-default-cpu = <0x00>; | |
| qcom,vddp-ref-clk-supply = <0x37c>; | |
| }; | |
| wsa_npl_clk { | |
| qcom,codec-ext-clk-src = <0x04>; | |
| #clock-cells = <0x01>; | |
| compatible = "qcom,audio-ref-clk"; | |
| phandle = <0x658>; | |
| qcom,codec-lpass-clk-id = <0x30a>; | |
| qcom,codec-lpass-ext-clk-freq = <0x124f800>; | |
| }; | |
| qcom,smp2p-adsp { | |
| qcom,local-pid = <0x00>; | |
| interrupts = <0x03 0x02 0x01>; | |
| interrupt-parent = <0x8a>; | |
| qcom,remote-pid = <0x02>; | |
| compatible = "qcom,smp2p"; | |
| mboxes = <0x8a 0x03 0x02>; | |
| qcom,smem = <0x1bb 0x1ad>; | |
| qcom,smp2p-rdbg2-out { | |
| qcom,entry-name = "rdbg"; | |
| #qcom,smem-state-cells = <0x01>; | |
| phandle = <0x24f>; | |
| }; | |
| slave-kernel { | |
| qcom,entry-name = "slave-kernel"; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x94>; | |
| interrupt-controller; | |
| }; | |
| master-kernel { | |
| qcom,entry-name = "master-kernel"; | |
| #qcom,smem-state-cells = <0x01>; | |
| phandle = <0x95>; | |
| }; | |
| qcom,smp2p-rdbg2-in { | |
| qcom,entry-name = "rdbg"; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x250>; | |
| interrupt-controller; | |
| }; | |
| }; | |
| qcom,mdss_dsi_phy1@ae96400 { | |
| qcom,platform-strength-ctrl = [55 03 55 03 55 03 55 03 55 00]; | |
| reg-names = "dsi_phy\0dyn_refresh_base"; | |
| cell-index = <0x01>; | |
| label = "dsi-phy-1"; | |
| qcom,platform-lane-config = <0xa0a 0xa0a 0xa0a 0xa0a 0x8a8a>; | |
| compatible = "qcom,dsi-phy-v4.1"; | |
| vdda-0p9-supply = <0x7c>; | |
| qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; | |
| reg = <0xae96400 0x7c0 0xae96200 0x100>; | |
| phandle = <0x55a>; | |
| qcom,phy-supply-entries { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,phy-supply-entry@0 { | |
| qcom,supply-disable-load = <0x00>; | |
| qcom,supply-enable-load = <0xb3b0>; | |
| qcom,supply-name = "vdda-0p9"; | |
| qcom,supply-max-voltage = <0xd6d80>; | |
| reg = <0x00>; | |
| qcom,supply-min-voltage = <0xd6d80>; | |
| }; | |
| }; | |
| }; | |
| hwevent { | |
| clock-names = "apb_pclk"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-hwevent"; | |
| compatible = "qcom,coresight-hwevent"; | |
| coresight-csr = <0x1a2>; | |
| }; | |
| qcom,kgsl-hyp { | |
| qcom,pas-id = <0x0d>; | |
| compatible = "qcom,pil-tz-generic"; | |
| phandle = <0x605>; | |
| qcom,firmware-name = "a650_zap"; | |
| }; | |
| tsens@c222000 { | |
| reg-names = "tsens_srot_physical\0tsens_tm_physical"; | |
| interrupts = <0x00 0x1fa 0x04 0x00 0x1fc 0x04>; | |
| #thermal-sensor-cells = <0x01>; | |
| compatible = "qcom,tsens24xx"; | |
| interrupt-names = "tsens-upper-lower\0tsens-critical"; | |
| reg = <0xc222000 0x04 0xc263000 0x1ff>; | |
| phandle = <0x19>; | |
| tsens-reinit-wa; | |
| }; | |
| usb_audio_qmi_dev { | |
| iommus = <0x47 0x180f 0x00>; | |
| qcom,usb-audio-intr-num = <0x02>; | |
| compatible = "qcom,usb-audio-qmi-dev"; | |
| qcom,usb-audio-stream-id = <0x0f>; | |
| qcom,iommu-dma = "disabled"; | |
| }; | |
| qcom,msm-adsprpc-mem { | |
| restrict-access; | |
| memory-region = <0xa0>; | |
| compatible = "qcom,msm-adsprpc-mem-region"; | |
| }; | |
| qcom,msm_hdcp { | |
| compatible = "qcom,msm-hdcp"; | |
| phandle = <0x3a2>; | |
| }; | |
| cti@7720000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| cpu = <0x14>; | |
| coresight-name = "coresight-cti-cpu7"; | |
| compatible = "arm,primecell"; | |
| reg = <0x7720000 0x1000>; | |
| phandle = <0x52f>; | |
| }; | |
| ad-hoc-bus { | |
| reg-names = "aggre1_noc-base\0aggre2_noc-base\0config_noc-base\0dc_noc-base\0mc_virt-base\0gem_noc-base\0mmss_noc-base\0system_noc-base\0ipa_virt-base\0compute_noc-base\0npu_noc-base"; | |
| compatible = "qcom,msm-bus-device"; | |
| reg = <0x16e0000 0x1f180 0x1700000 0x3d180 0x1500000 0x28000 0x90c0000 0x4200 0x9100000 0xae200 0x9100000 0xae200 0x1740000 0x1f080 0x1620000 0x1c200 0x1620000 0x40000 0x1700000 0x3d180 0x9990000 0x1600>; | |
| phandle = <0x3aa>; | |
| mas-qhm-gemnoc-cfg { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x9d>; | |
| qcom,buswidth = <0x04>; | |
| label = "mas-qhm-gemnoc-cfg"; | |
| qcom,connections = <0x102 0x103 0x104>; | |
| phandle = <0x141>; | |
| qcom,bus-dev = <0xfe>; | |
| }; | |
| slv-qns-gemnoc-gc { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2758>; | |
| qcom,buswidth = <0x08>; | |
| label = "slv-qns-gemnoc-gc"; | |
| qcom,connections = <0x14e>; | |
| phandle = <0x12a>; | |
| qcom,bcms = <0x14f>; | |
| qcom,bus-dev = <0x11c>; | |
| }; | |
| mas-qhm-mnoc-cfg { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x67>; | |
| qcom,buswidth = <0x04>; | |
| label = "mas-qhm-mnoc-cfg"; | |
| qcom,connections = <0x10a>; | |
| phandle = <0x13d>; | |
| qcom,bus-dev = <0x10b>; | |
| }; | |
| slv-xs-pcie-1 { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x29a>; | |
| qcom,buswidth = <0x08>; | |
| label = "slv-xs-pcie-1"; | |
| phandle = <0x128>; | |
| qcom,bcms = <0x154>; | |
| qcom,bus-dev = <0x11c>; | |
| }; | |
| mas-qnm-gemnoc { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0xa1>; | |
| qcom,buswidth = <0x10>; | |
| label = "mas-qnm-gemnoc"; | |
| qcom,connections = <0x120 0x121 0x122 0xba 0x123 0x124>; | |
| phandle = <0x142>; | |
| qcom,bcms = <0x125>; | |
| qcom,bus-dev = <0x11c>; | |
| }; | |
| mas-qhm-tsif { | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x52>; | |
| qcom,buswidth = <0x04>; | |
| label = "mas-qhm-tsif"; | |
| qcom,connections = <0xb9>; | |
| qcom,blacklist = <0xba>; | |
| qcom,qport = <0x08>; | |
| phandle = <0x3af>; | |
| qcom,prio = <0x02>; | |
| qcom,bus-dev = <0xb8>; | |
| }; | |
| bcm-alc { | |
| qcom,rscs = <0xb5>; | |
| cell-id = <0x1b7f>; | |
| label = "ALC"; | |
| qcom,bcm-name = "ALC"; | |
| phandle = <0x12b>; | |
| qcom,bcm-dev; | |
| }; | |
| slv-qhs-snoc-cfg { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x282>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-snoc-cfg"; | |
| qcom,connections = <0x13f>; | |
| phandle = <0xce>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| bcm-sn12 { | |
| qcom,rscs = <0xb5>; | |
| cell-id = <0x1b76>; | |
| label = "SN12"; | |
| qcom,bcm-name = "SN12"; | |
| phandle = <0x136>; | |
| qcom,bcm-dev; | |
| }; | |
| bcm-sn0 { | |
| qcom,rscs = <0xb5>; | |
| cell-id = <0x1b6a>; | |
| label = "SN0"; | |
| qcom,bcm-name = "SN0"; | |
| phandle = <0x151>; | |
| qcom,bcm-dev; | |
| }; | |
| slv-qhs-dpm { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x32f>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-dpm"; | |
| phandle = <0x11a>; | |
| qcom,bus-dev = <0x111>; | |
| }; | |
| bcm-acv_display { | |
| qcom,rscs = <0xb6>; | |
| cell-id = <0x697e>; | |
| label = "ACV_DISPLAY"; | |
| qcom,bcm-name = "ACV"; | |
| phandle = <0x15a>; | |
| qcom,bcm-dev; | |
| }; | |
| slv-qns-a2noc-snoc { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2751>; | |
| qcom,buswidth = <0x10>; | |
| label = "slv-qns-a2noc-snoc"; | |
| qcom,connections = <0x137>; | |
| phandle = <0xbf>; | |
| qcom,bus-dev = <0xbe>; | |
| }; | |
| mas-qnm-mnoc-sf { | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x02>; | |
| qcom,node-qos-bcms = <0x1b64 0x00 0x01>; | |
| cell-id = <0x85>; | |
| qcom,buswidth = <0x20>; | |
| label = "mas-qnm-mnoc-sf"; | |
| qcom,forwarding; | |
| qcom,connections = <0xfd 0xf9>; | |
| qcom,qport = <0x03 0x43>; | |
| phandle = <0x14b>; | |
| qcom,prio = <0x00>; | |
| qcom,bus-dev = <0xfe>; | |
| }; | |
| slv-srvc-cnoc { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x286>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-srvc-cnoc"; | |
| phandle = <0xe5>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| slv-qhs-venus-cfg { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x254>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-venus-cfg"; | |
| phandle = <0xe0>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| qcom,disable-ports = <0x05 0x06 0x07>; | |
| node-reg-names = "mmcx"; | |
| mmcx-supply = <0x69>; | |
| }; | |
| mas-qhm-qup0 { | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x97>; | |
| qcom,buswidth = <0x04>; | |
| label = "mas-qhm-qup0"; | |
| qcom,connections = <0xbf>; | |
| qcom,qport = <0x0c>; | |
| phandle = <0x3b6>; | |
| qcom,bcms = <0xbb>; | |
| qcom,prio = <0x02>; | |
| qcom,bus-dev = <0xbe>; | |
| }; | |
| bcm-co0 { | |
| qcom,rscs = <0xb5>; | |
| cell-id = <0x1b81>; | |
| label = "CO0"; | |
| qcom,bcm-name = "CO0"; | |
| phandle = <0x139>; | |
| qcom,bcm-dev; | |
| }; | |
| slv-qhs-pdm { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x267>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-pdm"; | |
| phandle = <0xcf>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| bcm-mm0 { | |
| qcom,rscs = <0xb5>; | |
| cell-id = <0x1b63>; | |
| label = "MM0"; | |
| qcom,bcm-name = "MM0"; | |
| phandle = <0x14a>; | |
| qcom,bcm-dev; | |
| }; | |
| slv-qhs-ipc-router { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x329>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-ipc-router"; | |
| phandle = <0xd9>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| slv-qns-llcc { | |
| qcom,agg-ports = <0x04>; | |
| cell-id = <0x302>; | |
| qcom,buswidth = <0x10>; | |
| label = "slv-qns-llcc"; | |
| qcom,connections = <0x143>; | |
| phandle = <0xfd>; | |
| qcom,bcms = <0x144>; | |
| qcom,bus-dev = <0xfe>; | |
| }; | |
| slv-qhs-ipa { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2a4>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-ipa"; | |
| phandle = <0xe2>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| bcm-cn0 { | |
| qcom,rscs = <0xb5>; | |
| cell-id = <0x1b7c>; | |
| label = "CN0"; | |
| qcom,bcm-name = "CN0"; | |
| phandle = <0xf7>; | |
| qcom,bcm-dev; | |
| }; | |
| bcm-sn9 { | |
| qcom,rscs = <0xb5>; | |
| cell-id = <0x1b73>; | |
| label = "SN9"; | |
| qcom,bcm-name = "SN9"; | |
| phandle = <0x129>; | |
| qcom,bcm-dev; | |
| }; | |
| bcm-sh2 { | |
| qcom,rscs = <0xb5>; | |
| cell-id = <0x1b5d>; | |
| label = "SH2"; | |
| qcom,bcm-name = "SH2"; | |
| phandle = <0xff>; | |
| qcom,bcm-dev; | |
| }; | |
| slv-qhs-pcie0-cfg { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x29b>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-pcie0-cfg"; | |
| phandle = <0xda>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| slv-srvc-odd-gemnoc { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x32a>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-srvc-odd-gemnoc"; | |
| phandle = <0x102>; | |
| qcom,bus-dev = <0xfe>; | |
| }; | |
| slv-qhs-ufs-mem-cfg { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2f5>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-ufs-mem-cfg"; | |
| phandle = <0xcd>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| fab-mc_virt { | |
| qcom,base-name = "mc_virt-base"; | |
| qcom,sbm-offset = <0x00>; | |
| cell-id = <0x1807>; | |
| qcom,bypass-qos-prg; | |
| clocks; | |
| label = "fab-mc_virt"; | |
| qcom,base-offset = <0x00>; | |
| qcom,fab-dev; | |
| phandle = <0x109>; | |
| qcom,qos-off = <0x00>; | |
| }; | |
| mas-qnm-gemnoc-pcie { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x9f>; | |
| qcom,buswidth = <0x08>; | |
| label = "mas-qnm-gemnoc-pcie"; | |
| qcom,connections = <0x126 0x127 0x128>; | |
| phandle = <0x145>; | |
| qcom,bcms = <0x129>; | |
| qcom,bus-dev = <0x11c>; | |
| }; | |
| bcm-mc0_display { | |
| qcom,rscs = <0xb6>; | |
| cell-id = <0x6978>; | |
| label = "MC0_DISPLAY"; | |
| qcom,bcm-name = "MC0"; | |
| phandle = <0x159>; | |
| qcom,bcm-dev; | |
| }; | |
| mas-qxm-mdp0_display { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x4e23>; | |
| qcom,buswidth = <0x20>; | |
| label = "mas-qxm-mdp0_display"; | |
| qcom,connections = <0x130>; | |
| qcom,qport = <0x06>; | |
| phandle = <0x3d3>; | |
| qcom,bcms = <0x132>; | |
| qcom,bus-dev = <0x131>; | |
| }; | |
| slv-qhs-usb3-0 { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x247>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-usb3-0"; | |
| phandle = <0xe4>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| slv-qns-mem-noc-hf { | |
| qcom,agg-ports = <0x02>; | |
| cell-id = <0x305>; | |
| qcom,buswidth = <0x20>; | |
| label = "slv-qns-mem-noc-hf"; | |
| qcom,connections = <0x149>; | |
| phandle = <0x10c>; | |
| qcom,bcms = <0x14a>; | |
| qcom,bus-dev = <0x10b>; | |
| }; | |
| slv-qns-pcie-mem-noc { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2755>; | |
| qcom,buswidth = <0x10>; | |
| label = "slv-qns-pcie-mem-noc"; | |
| qcom,connections = <0x135>; | |
| phandle = <0xc1>; | |
| qcom,bcms = <0x136>; | |
| qcom,bus-dev = <0xbe>; | |
| }; | |
| fab-ipa_virt { | |
| qcom,base-name = "ipa_virt-base"; | |
| qcom,sbm-offset = <0x00>; | |
| cell-id = <0x1809>; | |
| qcom,bypass-qos-prg; | |
| clocks; | |
| label = "fab-ipa_virt"; | |
| qcom,base-offset = <0x00>; | |
| qcom,fab-dev; | |
| phandle = <0x107>; | |
| qcom,qos-off = <0x00>; | |
| }; | |
| slv-qns-cnoc-a2noc { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2d5>; | |
| qcom,buswidth = <0x08>; | |
| label = "slv-qns-cnoc-a2noc"; | |
| qcom,connections = <0x140>; | |
| phandle = <0xf8>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| mas-xm-ufs-mem { | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x7b>; | |
| qcom,buswidth = <0x08>; | |
| label = "mas-xm-ufs-mem"; | |
| qcom,connections = <0xb9>; | |
| qcom,blacklist = <0xba>; | |
| qcom,qport = <0x03>; | |
| phandle = <0x3b2>; | |
| qcom,prio = <0x02>; | |
| qcom,bus-dev = <0xb8>; | |
| qcom,node-qos-clks { | |
| clock-names = "clk-aggre-ufs-phy-axi-no-rate"; | |
| clocks = <0x16 0x06>; | |
| }; | |
| }; | |
| slv-qhs-cpr-mmcx { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x30c>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-cpr-mmcx"; | |
| phandle = <0xdb>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| mas-xm-qdss-dap { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x4c>; | |
| qcom,buswidth = <0x08>; | |
| label = "mas-xm-qdss-dap"; | |
| qcom,connections = <0xc5 0xc6 0xc7 0xc8 0xc9 0xca 0xcb 0xcc 0xcd 0xce 0xcf 0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9 0xf8 0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef 0xf0 0xf1 0xf2 0xf3 0xf4 0xf5>; | |
| qcom,blacklist = <0xf9>; | |
| phandle = <0x3bf>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| slv-qhs-tlmm2 { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2dc>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-tlmm2"; | |
| phandle = <0xca>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| slv-srvc-even-gemnoc { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x320>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-srvc-even-gemnoc"; | |
| phandle = <0x103>; | |
| qcom,bus-dev = <0xfe>; | |
| }; | |
| bcm-sn7 { | |
| qcom,rscs = <0xb5>; | |
| cell-id = <0x1b71>; | |
| label = "SN7"; | |
| qcom,bcm-name = "SN7"; | |
| phandle = <0x11e>; | |
| qcom,bcm-dev; | |
| }; | |
| fab-gem_noc { | |
| qcom,base-name = "gem_noc-base"; | |
| qcom,sbm-offset = <0x00>; | |
| qcom,bus-type = <0x01>; | |
| cell-id = <0x180c>; | |
| clocks; | |
| label = "fab-gem_noc"; | |
| qcom,base-offset = <0x21000>; | |
| qcom,fab-dev; | |
| phandle = <0xfe>; | |
| qcom,qos-off = <0x1000>; | |
| }; | |
| bcm-sh0 { | |
| qcom,rscs = <0xb5>; | |
| cell-id = <0x1b5b>; | |
| label = "SH0"; | |
| qcom,bcm-name = "SH0"; | |
| phandle = <0x144>; | |
| qcom,bcm-dev; | |
| }; | |
| mas-qnm-snoc-gc { | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x86>; | |
| qcom,buswidth = <0x08>; | |
| label = "mas-qnm-snoc-gc"; | |
| qcom,forwarding; | |
| qcom,connections = <0xfd>; | |
| qcom,qport = <0x82>; | |
| phandle = <0x14e>; | |
| qcom,prio = <0x00>; | |
| qcom,bus-dev = <0xfe>; | |
| }; | |
| slv-qns-cnoc { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2734>; | |
| qcom,buswidth = <0x08>; | |
| label = "slv-qns-cnoc"; | |
| qcom,connections = <0x14d>; | |
| phandle = <0xba>; | |
| qcom,bus-dev = <0x11c>; | |
| }; | |
| slv-qhs-mnoc-cfg { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x280>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-mnoc-cfg"; | |
| qcom,connections = <0x13d>; | |
| phandle = <0xcc>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| slv-qhs-a2-noc-cfg { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2b0>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-a2-noc-cfg"; | |
| qcom,connections = <0x13b>; | |
| phandle = <0xd2>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| mas-xm-pcie3-1 { | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x64>; | |
| qcom,buswidth = <0x08>; | |
| label = "mas-xm-pcie3-1"; | |
| qcom,connections = <0xc1>; | |
| qcom,blacklist = <0xba>; | |
| qcom,qport = <0x09>; | |
| phandle = <0x3ba>; | |
| qcom,prio = <0x02>; | |
| qcom,bus-dev = <0xbe>; | |
| }; | |
| mas-qnm-snoc { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2733>; | |
| qcom,buswidth = <0x08>; | |
| label = "mas-qnm-snoc"; | |
| qcom,connections = <0xc5 0xc6 0xc7 0xc8 0xc9 0xca 0xcb 0xcc 0xcd 0xce 0xcf 0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9 0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef 0xf0 0xf1 0xf2 0xf3 0xf4 0xf5>; | |
| phandle = <0x14d>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| slv-qhs-qup2 { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x311>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-qup2"; | |
| phandle = <0xf4>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| mas-qnm-npu { | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x02>; | |
| cell-id = <0x9a>; | |
| qcom,buswidth = <0x20>; | |
| label = "mas-qnm-npu"; | |
| qcom,forwarding; | |
| qcom,connections = <0xc2>; | |
| qcom,qport = <0x06 0x07>; | |
| phandle = <0x3be>; | |
| qcom,bcms = <0xc4>; | |
| qcom,prio = <0x00>; | |
| qcom,bus-dev = <0xc3>; | |
| }; | |
| mas-alm-gpu-tcu { | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x9b>; | |
| qcom,buswidth = <0x08>; | |
| label = "mas-alm-gpu-tcu"; | |
| qcom,connections = <0xfd 0xf9>; | |
| qcom,qport = <0x7f>; | |
| phandle = <0x3c0>; | |
| qcom,bcms = <0xff>; | |
| qcom,prio = <0x01>; | |
| qcom,bus-dev = <0xfe>; | |
| }; | |
| mas-xm-gic { | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x95>; | |
| qcom,buswidth = <0x08>; | |
| label = "mas-xm-gic"; | |
| qcom,forwarding; | |
| qcom,connections = <0x12a>; | |
| qcom,qport = <0x01>; | |
| phandle = <0x3d1>; | |
| qcom,prio = <0x02>; | |
| qcom,bus-dev = <0x11c>; | |
| }; | |
| bcm-acv { | |
| qcom,rscs = <0xb5>; | |
| cell-id = <0x1b7e>; | |
| label = "ACV"; | |
| qcom,bcm-name = "ACV"; | |
| phandle = <0x148>; | |
| qcom,bcm-dev; | |
| }; | |
| fab-system_noc { | |
| qcom,base-name = "system_noc-base"; | |
| qcom,sbm-offset = <0x00>; | |
| qcom,bus-type = <0x01>; | |
| cell-id = <0x400>; | |
| clocks; | |
| label = "fab-system_noc"; | |
| qcom,base-offset = <0x12000>; | |
| qcom,fab-dev; | |
| phandle = <0x11c>; | |
| qcom,qos-off = <0x1000>; | |
| }; | |
| slv-qhs-prng { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x26a>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-prng"; | |
| phandle = <0xec>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| slv-qhs-tlmm0 { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2db>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-tlmm0"; | |
| phandle = <0xc8>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| slv-qns-mem-noc-sf { | |
| qcom,agg-ports = <0x02>; | |
| cell-id = <0x304>; | |
| qcom,buswidth = <0x20>; | |
| label = "slv-qns-mem-noc-sf"; | |
| qcom,connections = <0x14b>; | |
| phandle = <0x10e>; | |
| qcom,bcms = <0x14c>; | |
| qcom,bus-dev = <0x10b>; | |
| }; | |
| slv-qhs-llm { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x331>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-llm"; | |
| phandle = <0x114>; | |
| qcom,bus-dev = <0x111>; | |
| }; | |
| slv-qns-gem-noc-snoc { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2757>; | |
| qcom,buswidth = <0x10>; | |
| label = "slv-qns-gem-noc-snoc"; | |
| qcom,connections = <0x142>; | |
| phandle = <0xf9>; | |
| qcom,bus-dev = <0xfe>; | |
| }; | |
| bcm-sn5 { | |
| qcom,rscs = <0xb5>; | |
| cell-id = <0x1b6f>; | |
| label = "SN5"; | |
| qcom,bcm-name = "SN5"; | |
| phandle = <0x155>; | |
| qcom,bcm-dev; | |
| }; | |
| slv-qhs-tsif { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x23f>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-tsif"; | |
| phandle = <0xe1>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| slv-qhs-dcc-cfg { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2aa>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-dcc-cfg"; | |
| phandle = <0xd7>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| slv-ebi_display { | |
| qcom,agg-ports = <0x04>; | |
| cell-id = <0x5020>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-ebi_display"; | |
| phandle = <0x12e>; | |
| qcom,bcms = <0x159 0x15a>; | |
| qcom,bus-dev = <0x12f>; | |
| }; | |
| slv-qhs-compute-dsp { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2ed>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-compute-dsp"; | |
| phandle = <0xc5>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| bcm-mm0_display { | |
| qcom,rscs = <0xb6>; | |
| cell-id = <0x697a>; | |
| label = "MM0_DISPLAY"; | |
| qcom,bcm-name = "MM0"; | |
| phandle = <0x15c>; | |
| qcom,bcm-dev; | |
| }; | |
| slv-qhs-gpuss-cfg { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x256>; | |
| qcom,buswidth = <0x08>; | |
| label = "slv-qhs-gpuss-cfg"; | |
| phandle = <0xdf>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| mas-qnm-mnoc-hf_display { | |
| qcom,agg-ports = <0x02>; | |
| cell-id = <0x4e21>; | |
| qcom,buswidth = <0x20>; | |
| label = "mas-qnm-mnoc-hf_display"; | |
| qcom,connections = <0x12c>; | |
| qcom,qport = <0x02 0x42>; | |
| phandle = <0x15b>; | |
| qcom,bus-dev = <0x12d>; | |
| }; | |
| slv-qhs-qup0 { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x313>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-qup0"; | |
| phandle = <0xf2>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| slv-srvc-snoc { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x24b>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-srvc-snoc"; | |
| phandle = <0x11b>; | |
| qcom,bus-dev = <0x11c>; | |
| }; | |
| slv-qhs-pcie-modem-cfg { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2ac>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-pcie-modem-cfg"; | |
| phandle = <0xd5>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| slv-qhs-cp { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x32d>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-cp"; | |
| phandle = <0x116>; | |
| qcom,bus-dev = <0x111>; | |
| }; | |
| bcm-ce0 { | |
| qcom,rscs = <0xb5>; | |
| cell-id = <0x1b7a>; | |
| label = "CE0"; | |
| qcom,bcm-name = "CE0"; | |
| phandle = <0xc0>; | |
| qcom,bcm-dev; | |
| }; | |
| fab-mmss_noc_display { | |
| qcom,base-name = "mmss_noc-base"; | |
| qcom,sbm-offset = <0x00>; | |
| qcom,bus-type = <0x01>; | |
| cell-id = <0x6592>; | |
| qcom,bypass-qos-prg; | |
| clocks; | |
| label = "fab-mmss_noc_display"; | |
| qcom,base-offset = <0xa000>; | |
| qcom,fab-dev; | |
| phandle = <0x131>; | |
| qcom,qos-off = <0x800>; | |
| }; | |
| slv-qhs-tcsr { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x26f>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-tcsr"; | |
| phandle = <0xd6>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| slv-qhs-pimem-cfg { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2a9>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-pimem-cfg"; | |
| phandle = <0xf0>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| mas-qnm-gpu { | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x02>; | |
| cell-id = <0x1a>; | |
| qcom,buswidth = <0x20>; | |
| label = "mas-qnm-gpu"; | |
| qcom,forwarding; | |
| qcom,connections = <0xfd 0xf9>; | |
| qcom,qport = <0x01 0x41>; | |
| phandle = <0x3c3>; | |
| qcom,prio = <0x00>; | |
| qcom,bus-dev = <0xfe>; | |
| }; | |
| mas-xm-ufs-card { | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x7a>; | |
| qcom,buswidth = <0x08>; | |
| label = "mas-xm-ufs-card"; | |
| qcom,connections = <0xbf>; | |
| qcom,blacklist = <0xba>; | |
| qcom,qport = <0x04>; | |
| phandle = <0x3bd>; | |
| qcom,prio = <0x02>; | |
| qcom,bus-dev = <0xbe>; | |
| }; | |
| bcm-mc0 { | |
| qcom,rscs = <0xb5>; | |
| cell-id = <0x1b58>; | |
| label = "MC0"; | |
| qcom,bcm-name = "MC0"; | |
| phandle = <0x147>; | |
| qcom,bcm-dev; | |
| }; | |
| slv-qhs-apss { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2a1>; | |
| qcom,buswidth = <0x08>; | |
| label = "slv-qhs-apss"; | |
| phandle = <0x122>; | |
| qcom,bus-dev = <0x11c>; | |
| }; | |
| slv-qhs-pcie1-cfg { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x29c>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-pcie1-cfg"; | |
| phandle = <0xd1>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| slv-qhs-vsense-ctrl-cfg { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2f6>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-vsense-ctrl-cfg"; | |
| phandle = <0xed>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| slv-srvc-noc { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x334>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-srvc-noc"; | |
| phandle = <0x112>; | |
| qcom,bus-dev = <0x111>; | |
| }; | |
| bcm-sn3 { | |
| qcom,rscs = <0xb5>; | |
| cell-id = <0x1b6d>; | |
| label = "SN3"; | |
| qcom,bcm-name = "SN3"; | |
| phandle = <0x153>; | |
| qcom,bcm-dev; | |
| }; | |
| mas-xm-usb3-1 { | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x65>; | |
| qcom,buswidth = <0x08>; | |
| label = "mas-xm-usb3-1"; | |
| qcom,connections = <0xb9>; | |
| qcom,qport = <0x01>; | |
| phandle = <0x3b4>; | |
| qcom,prio = <0x02>; | |
| qcom,bus-dev = <0xb8>; | |
| qcom,node-qos-clks { | |
| clock-names = "clk-usb3-sec-axi-no-rate"; | |
| clocks = <0x16 0x09>; | |
| }; | |
| }; | |
| slv-ebi { | |
| qcom,agg-ports = <0x04>; | |
| cell-id = <0x200>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-ebi"; | |
| phandle = <0x108>; | |
| qcom,bcms = <0x147 0x148>; | |
| qcom,bus-dev = <0x109>; | |
| }; | |
| bcm-sh0_display { | |
| qcom,rscs = <0xb6>; | |
| cell-id = <0x6979>; | |
| label = "SH0_DISPLAY"; | |
| qcom,bcm-name = "SH0"; | |
| phandle = <0x158>; | |
| qcom,bcm-dev; | |
| }; | |
| mas-qnm-video0 { | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x01>; | |
| qcom,node-qos-bcms = <0x1b64 0x00 0x01>; | |
| cell-id = <0x3f>; | |
| qcom,buswidth = <0x20>; | |
| label = "mas-qnm-video0"; | |
| qcom,forwarding; | |
| qcom,connections = <0x10e>; | |
| qcom,qport = <0x0c>; | |
| phandle = <0x3c8>; | |
| qcom,bcms = <0x10f>; | |
| qcom,prio = <0x00>; | |
| qcom,bus-dev = <0x10b>; | |
| }; | |
| mas-qnm-cmpnoc { | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x02>; | |
| cell-id = <0x9e>; | |
| qcom,buswidth = <0x20>; | |
| label = "mas-qnm-cmpnoc"; | |
| qcom,forwarding; | |
| qcom,connections = <0xfd 0xf9>; | |
| qcom,qport = <0x00 0x40>; | |
| phandle = <0x138>; | |
| qcom,bcms = <0x105>; | |
| qcom,prio = <0x00>; | |
| qcom,bus-dev = <0xfe>; | |
| }; | |
| slv-qhs-llcc { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2f8>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-llcc"; | |
| phandle = <0xfb>; | |
| qcom,bus-dev = <0xfc>; | |
| }; | |
| slv-qhs-ahb2phy0 { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x30b>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-ahb2phy0"; | |
| phandle = <0xdd>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| slv-qns-mem-noc-hf_display { | |
| qcom,agg-ports = <0x02>; | |
| cell-id = <0x5023>; | |
| qcom,buswidth = <0x20>; | |
| label = "slv-qns-mem-noc-hf_display"; | |
| qcom,connections = <0x15b>; | |
| phandle = <0x130>; | |
| qcom,bcms = <0x15c>; | |
| qcom,bus-dev = <0x131>; | |
| }; | |
| bcm-mm3 { | |
| qcom,rscs = <0xb5>; | |
| cell-id = <0x1b66>; | |
| label = "MM3"; | |
| qcom,bcm-name = "MM3"; | |
| phandle = <0x10f>; | |
| qcom,bcm-dev; | |
| }; | |
| slv-qhs-cal-dp0 { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x32b>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-cal-dp0"; | |
| phandle = <0x118>; | |
| qcom,bus-dev = <0x111>; | |
| }; | |
| slv-xs-sys-tcu-cfg { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2a0>; | |
| qcom,buswidth = <0x08>; | |
| label = "slv-xs-sys-tcu-cfg"; | |
| phandle = <0x123>; | |
| qcom,bus-dev = <0x11c>; | |
| }; | |
| bcm-mm2_display { | |
| qcom,rscs = <0xb6>; | |
| cell-id = <0x697c>; | |
| label = "MM2_DISPLAY"; | |
| qcom,bcm-name = "MM2"; | |
| phandle = <0x15e>; | |
| qcom,bcm-dev; | |
| }; | |
| mas-qxm-mdp0 { | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x01>; | |
| qcom,node-qos-bcms = <0x1b64 0x00 0x01>; | |
| cell-id = <0x16>; | |
| qcom,buswidth = <0x20>; | |
| label = "mas-qxm-mdp0"; | |
| qcom,forwarding; | |
| qcom,connections = <0x10c>; | |
| qcom,qport = <0x06>; | |
| phandle = <0x3cb>; | |
| qcom,bcms = <0x10d>; | |
| qcom,prio = <0x00>; | |
| qcom,bus-dev = <0x10b>; | |
| }; | |
| slv-qhs-cpr-mx { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x28c>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-cpr-mx"; | |
| phandle = <0xf1>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| mas-qnm-video-cvp { | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x01>; | |
| qcom,node-qos-bcms = <0x1b64 0x00 0x01>; | |
| cell-id = <0x8a>; | |
| qcom,buswidth = <0x20>; | |
| label = "mas-qnm-video-cvp"; | |
| qcom,forwarding; | |
| qcom,connections = <0x10e>; | |
| qcom,qport = <0x0e>; | |
| phandle = <0x3ca>; | |
| qcom,bcms = <0x10f>; | |
| qcom,prio = <0x00>; | |
| qcom,bus-dev = <0x10b>; | |
| }; | |
| slv-qns-gemnoc-sf { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2759>; | |
| qcom,buswidth = <0x10>; | |
| label = "slv-qns-gemnoc-sf"; | |
| qcom,connections = <0x150>; | |
| phandle = <0x11d>; | |
| qcom,bcms = <0x151>; | |
| qcom,bus-dev = <0x11c>; | |
| }; | |
| slv-qns-a1noc-snoc { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x274e>; | |
| qcom,buswidth = <0x10>; | |
| label = "slv-qns-a1noc-snoc"; | |
| qcom,connections = <0x134>; | |
| phandle = <0xb9>; | |
| qcom,bus-dev = <0xb8>; | |
| }; | |
| bcm-qup0 { | |
| qcom,rscs = <0xb5>; | |
| cell-id = <0x1b80>; | |
| label = "QUP0"; | |
| qcom,bcm-name = "QUP0"; | |
| phandle = <0xbb>; | |
| qcom,bcm-dev; | |
| }; | |
| slv-qhs-dma-bwmon { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x32e>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-dma-bwmon"; | |
| phandle = <0x115>; | |
| qcom,bus-dev = <0x111>; | |
| }; | |
| bcm-sn1 { | |
| qcom,rscs = <0xb5>; | |
| cell-id = <0x1b6b>; | |
| label = "SN1"; | |
| qcom,bcm-name = "SN1"; | |
| phandle = <0x152>; | |
| qcom,bcm-dev; | |
| }; | |
| slv-qhs-memnoc { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x314>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-memnoc"; | |
| qcom,connections = <0x141>; | |
| phandle = <0xfa>; | |
| qcom,bus-dev = <0xfc>; | |
| }; | |
| fab-mc_virt_display { | |
| qcom,base-name = "mc_virt-base"; | |
| qcom,sbm-offset = <0x00>; | |
| cell-id = <0x6590>; | |
| qcom,bypass-qos-prg; | |
| clocks; | |
| label = "fab-mc_virt_display"; | |
| qcom,base-offset = <0x00>; | |
| qcom,fab-dev; | |
| phandle = <0x12f>; | |
| qcom,qos-off = <0x00>; | |
| }; | |
| slv-qns-pcie-modem-mem-noc { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x326>; | |
| qcom,buswidth = <0x10>; | |
| label = "slv-qns-pcie-modem-mem-noc"; | |
| qcom,connections = <0x135>; | |
| phandle = <0xbc>; | |
| qcom,bcms = <0x136>; | |
| qcom,bus-dev = <0xb8>; | |
| }; | |
| fab-aggre1_noc { | |
| qcom,base-name = "aggre1_noc-base"; | |
| qcom,sbm-offset = <0x00>; | |
| qcom,bus-type = <0x01>; | |
| cell-id = <0x1802>; | |
| clocks; | |
| label = "fab-aggre1_noc"; | |
| qcom,base-offset = <0x2000>; | |
| qcom,fab-dev; | |
| phandle = <0xb8>; | |
| qcom,qos-off = <0x1000>; | |
| }; | |
| mas-qnm-camnoc-icp { | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x01>; | |
| qcom,node-qos-bcms = <0x1b64 0x00 0x01>; | |
| cell-id = <0xab>; | |
| qcom,buswidth = <0x08>; | |
| label = "mas-qnm-camnoc-icp"; | |
| qcom,forwarding; | |
| qcom,connections = <0x10e>; | |
| qcom,qport = <0x02>; | |
| phandle = <0x3c6>; | |
| qcom,bcms = <0x10f>; | |
| qcom,prio = <0x05>; | |
| qcom,bus-dev = <0x10b>; | |
| }; | |
| mas-qhm-qup1 { | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x98>; | |
| qcom,buswidth = <0x04>; | |
| label = "mas-qhm-qup1"; | |
| qcom,connections = <0xb9>; | |
| qcom,blacklist = <0xba>; | |
| qcom,qport = <0x05>; | |
| phandle = <0x3ad>; | |
| qcom,bcms = <0xbb>; | |
| qcom,prio = <0x02>; | |
| qcom,bus-dev = <0xb8>; | |
| }; | |
| slv-srvc-aggre1-noc { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2e8>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-srvc-aggre1-noc"; | |
| phandle = <0xb7>; | |
| qcom,bus-dev = <0xb8>; | |
| }; | |
| slv-qhs-crypto0-cfg { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x271>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-crypto0-cfg"; | |
| phandle = <0xef>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| mas-xm-sdc4 { | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x50>; | |
| qcom,buswidth = <0x08>; | |
| label = "mas-xm-sdc4"; | |
| qcom,connections = <0xb9>; | |
| qcom,blacklist = <0xba>; | |
| qcom,qport = <0x02>; | |
| phandle = <0x3b1>; | |
| qcom,prio = <0x02>; | |
| qcom,bus-dev = <0xb8>; | |
| }; | |
| mas-qxm-rot_display { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x4e25>; | |
| qcom,buswidth = <0x20>; | |
| label = "mas-qxm-rot_display"; | |
| qcom,connections = <0x133>; | |
| qcom,qport = <0x0a>; | |
| phandle = <0x3d5>; | |
| qcom,bus-dev = <0x131>; | |
| }; | |
| bcm-mm1 { | |
| qcom,rscs = <0xb5>; | |
| cell-id = <0x1b64>; | |
| label = "MM1"; | |
| qcom,bcm-name = "MM1"; | |
| phandle = <0x10d>; | |
| qcom,bcm-dev; | |
| }; | |
| fab-mmss_noc { | |
| qcom,base-name = "mmss_noc-base"; | |
| qcom,sbm-offset = <0x00>; | |
| qcom,bus-type = <0x01>; | |
| cell-id = <0x800>; | |
| clocks; | |
| label = "fab-mmss_noc"; | |
| qcom,base-offset = <0xa000>; | |
| qcom,fab-dev; | |
| phandle = <0x10b>; | |
| qcom,qos-off = <0x800>; | |
| }; | |
| bcm-sh3 { | |
| qcom,rscs = <0xb5>; | |
| cell-id = <0x1b5e>; | |
| label = "SH3"; | |
| qcom,bcm-name = "SH3"; | |
| phandle = <0x105>; | |
| qcom,bcm-dev; | |
| }; | |
| slv-qns-cdsp-mem-noc { | |
| qcom,agg-ports = <0x02>; | |
| cell-id = <0x2756>; | |
| qcom,buswidth = <0x20>; | |
| label = "slv-qns-cdsp-mem-noc"; | |
| qcom,connections = <0x138>; | |
| phandle = <0xc2>; | |
| qcom,bcms = <0x139>; | |
| qcom,bus-dev = <0xc3>; | |
| }; | |
| mas-qxm-rot { | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x01>; | |
| qcom,node-qos-bcms = <0x1b64 0x00 0x01>; | |
| cell-id = <0x19>; | |
| qcom,buswidth = <0x20>; | |
| label = "mas-qxm-rot"; | |
| qcom,forwarding; | |
| qcom,connections = <0x10e>; | |
| qcom,qport = <0x0a>; | |
| phandle = <0x3cd>; | |
| qcom,prio = <0x00>; | |
| qcom,bus-dev = <0x10b>; | |
| }; | |
| slv-srvc-sys-gemnoc { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x316>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-srvc-sys-gemnoc"; | |
| phandle = <0x104>; | |
| qcom,bus-dev = <0xfe>; | |
| }; | |
| slv-xs-pcie-0 { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x299>; | |
| qcom,buswidth = <0x08>; | |
| label = "slv-xs-pcie-0"; | |
| phandle = <0x127>; | |
| qcom,bcms = <0x154>; | |
| qcom,bus-dev = <0x11c>; | |
| }; | |
| bcm-sn11 { | |
| qcom,rscs = <0xb5>; | |
| cell-id = <0x1b75>; | |
| label = "SN11"; | |
| qcom,bcm-name = "SN11"; | |
| phandle = <0x125>; | |
| qcom,bcm-dev; | |
| }; | |
| slv-qxs-pimem { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2c8>; | |
| qcom,buswidth = <0x08>; | |
| label = "slv-qxs-pimem"; | |
| phandle = <0x120>; | |
| qcom,bcms = <0x153>; | |
| qcom,bus-dev = <0x11c>; | |
| }; | |
| mas-alm-sys-tcu { | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x9c>; | |
| qcom,buswidth = <0x08>; | |
| label = "mas-alm-sys-tcu"; | |
| qcom,connections = <0xfd 0xf9>; | |
| qcom,qport = <0x80>; | |
| phandle = <0x3c1>; | |
| qcom,bcms = <0xff>; | |
| qcom,prio = <0x06>; | |
| qcom,bus-dev = <0xfe>; | |
| }; | |
| slv-qhs-usb3-1 { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2ef>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-usb3-1"; | |
| phandle = <0xe7>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| fab-dc_noc { | |
| qcom,base-name = "dc_noc-base"; | |
| qcom,sbm-offset = <0x00>; | |
| qcom,bus-type = <0x01>; | |
| cell-id = <0x1806>; | |
| clocks; | |
| label = "fab-dc_noc"; | |
| qcom,base-offset = <0x00>; | |
| qcom,fab-dev; | |
| phandle = <0xfc>; | |
| qcom,qos-off = <0x00>; | |
| }; | |
| mas-qxm-pimem { | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x8d>; | |
| qcom,buswidth = <0x08>; | |
| label = "mas-qxm-pimem"; | |
| qcom,forwarding; | |
| qcom,connections = <0x12a>; | |
| qcom,qport = <0x00>; | |
| phandle = <0x3d0>; | |
| qcom,prio = <0x02>; | |
| qcom,bus-dev = <0x11c>; | |
| }; | |
| mas-qnm-mnoc-sf_display { | |
| qcom,agg-ports = <0x02>; | |
| cell-id = <0x4e22>; | |
| qcom,buswidth = <0x20>; | |
| label = "mas-qnm-mnoc-sf_display"; | |
| qcom,connections = <0x12c>; | |
| qcom,qport = <0x03 0x43>; | |
| phandle = <0x15d>; | |
| qcom,bus-dev = <0x12d>; | |
| }; | |
| mas-xm-sdc2 { | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x51>; | |
| qcom,buswidth = <0x08>; | |
| label = "mas-xm-sdc2"; | |
| qcom,connections = <0xbf>; | |
| qcom,blacklist = <0xba>; | |
| qcom,qport = <0x03>; | |
| phandle = <0x3bc>; | |
| qcom,prio = <0x02>; | |
| qcom,bus-dev = <0xbe>; | |
| }; | |
| slv-qhs-display-cfg { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x24e>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-display-cfg"; | |
| phandle = <0xd4>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| qcom,disable-ports = <0x03 0x04>; | |
| node-reg-names = "mmcx"; | |
| mmcx-supply = <0x69>; | |
| }; | |
| mas-qhm-cfg { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0xae>; | |
| qcom,buswidth = <0x04>; | |
| label = "mas-qhm-cfg"; | |
| qcom,connections = <0x112 0x113 0x114 0x115 0x116 0x117 0x118 0x119 0x11a>; | |
| phandle = <0x13e>; | |
| qcom,bus-dev = <0x111>; | |
| }; | |
| mas-amm-npu-sys { | |
| qcom,agg-ports = <0x04>; | |
| cell-id = <0xac>; | |
| qcom,buswidth = <0x20>; | |
| label = "mas-amm-npu-sys"; | |
| qcom,connections = <0x110>; | |
| phandle = <0x3ce>; | |
| qcom,bus-dev = <0x111>; | |
| }; | |
| slv-qhs-cx-rdpm { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x328>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-cx-rdpm"; | |
| phandle = <0xd0>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| mas-qhm-qspi { | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0xa5>; | |
| qcom,buswidth = <0x04>; | |
| label = "mas-qhm-qspi"; | |
| qcom,connections = <0xb9>; | |
| qcom,blacklist = <0xba>; | |
| qcom,qport = <0x07>; | |
| phandle = <0x3ac>; | |
| qcom,prio = <0x02>; | |
| qcom,bus-dev = <0xb8>; | |
| }; | |
| slv-srvc-mnoc { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x25b>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-srvc-mnoc"; | |
| phandle = <0x10a>; | |
| qcom,bus-dev = <0x10b>; | |
| }; | |
| slv-qhs-lpass-cfg { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x20a>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-lpass-cfg"; | |
| phandle = <0xe8>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| bcm-sn8 { | |
| qcom,rscs = <0xb5>; | |
| cell-id = <0x1b72>; | |
| label = "SN8"; | |
| qcom,bcm-name = "SN8"; | |
| phandle = <0x11f>; | |
| qcom,bcm-dev; | |
| }; | |
| slv-qhs-a1-noc-cfg { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2af>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-a1-noc-cfg"; | |
| qcom,connections = <0x13a>; | |
| phandle = <0xea>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| bcm-ip0 { | |
| qcom,rscs = <0xb5>; | |
| cell-id = <0x1b7b>; | |
| label = "IP0"; | |
| qcom,bcm-name = "IP0"; | |
| phandle = <0x146>; | |
| qcom,bcm-dev; | |
| }; | |
| mas-qnm-pcie { | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0xaf>; | |
| qcom,buswidth = <0x10>; | |
| label = "mas-qnm-pcie"; | |
| qcom,forwarding; | |
| qcom,connections = <0xfd 0xf9>; | |
| qcom,qport = <0x81>; | |
| phandle = <0x135>; | |
| qcom,prio = <0x00>; | |
| qcom,bus-dev = <0xfe>; | |
| }; | |
| mas-qhm-cnoc-dc-noc { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x7e>; | |
| qcom,buswidth = <0x04>; | |
| label = "mas-qhm-cnoc-dc-noc"; | |
| qcom,connections = <0xfa 0xfb>; | |
| phandle = <0x13c>; | |
| qcom,bus-dev = <0xfc>; | |
| }; | |
| mas-qnm-snoc-sf { | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x87>; | |
| qcom,buswidth = <0x10>; | |
| label = "mas-qnm-snoc-sf"; | |
| qcom,forwarding; | |
| qcom,connections = <0xfd 0xf9 0x100>; | |
| qcom,qport = <0x83>; | |
| phandle = <0x150>; | |
| qcom,prio = <0x00>; | |
| qcom,bus-dev = <0xfe>; | |
| }; | |
| mas-qnm-camnoc-hf { | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x02>; | |
| qcom,node-qos-bcms = <0x1b64 0x00 0x01>; | |
| cell-id = <0xaa>; | |
| qcom,buswidth = <0x20>; | |
| label = "mas-qnm-camnoc-hf"; | |
| qcom,forwarding; | |
| qcom,connections = <0x10c>; | |
| qcom,qport = <0x04 0x05>; | |
| phandle = <0x3c5>; | |
| qcom,bcms = <0x10d>; | |
| qcom,prio = <0x00>; | |
| qcom,bus-dev = <0x10b>; | |
| }; | |
| slv-qhs-ddrss-cfg { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2ee>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-ddrss-cfg"; | |
| qcom,connections = <0x13c>; | |
| phandle = <0xd8>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| slv-xs-qdss-stm { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x24c>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-xs-qdss-stm"; | |
| phandle = <0x124>; | |
| qcom,bcms = <0x156>; | |
| qcom,bus-dev = <0x11c>; | |
| }; | |
| fab-npu_noc { | |
| qcom,base-name = "npu_noc-base"; | |
| qcom,sbm-offset = <0x00>; | |
| qcom,bus-type = <0x01>; | |
| cell-id = <0x180d>; | |
| clocks; | |
| label = "fab-npu_noc"; | |
| qcom,base-offset = <0x00>; | |
| qcom,fab-dev; | |
| phandle = <0x111>; | |
| qcom,qos-off = <0x00>; | |
| }; | |
| mas-qnm-aggre1-noc { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x274f>; | |
| qcom,buswidth = <0x10>; | |
| label = "mas-qnm-aggre1-noc"; | |
| qcom,connections = <0x11d>; | |
| phandle = <0x134>; | |
| qcom,bcms = <0x11e>; | |
| qcom,bus-dev = <0x11c>; | |
| }; | |
| mas-xm-qdss-etr { | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x3c>; | |
| qcom,buswidth = <0x08>; | |
| label = "mas-xm-qdss-etr"; | |
| qcom,connections = <0xbf>; | |
| qcom,blacklist = <0xba>; | |
| qcom,qport = <0x07>; | |
| phandle = <0x3bb>; | |
| qcom,prio = <0x02>; | |
| qcom,bus-dev = <0xbe>; | |
| }; | |
| mas-qxm-mdp1_display { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x4e24>; | |
| qcom,buswidth = <0x20>; | |
| label = "mas-qxm-mdp1_display"; | |
| qcom,connections = <0x130>; | |
| qcom,qport = <0x08>; | |
| phandle = <0x3d4>; | |
| qcom,bcms = <0x132>; | |
| qcom,bus-dev = <0x131>; | |
| }; | |
| slv-qhs-isense { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x330>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-isense"; | |
| phandle = <0x113>; | |
| qcom,bus-dev = <0x111>; | |
| }; | |
| slv-qhs-ufs-card-cfg { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2f4>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-ufs-card-cfg"; | |
| phandle = <0xe6>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| bcm-alc_display { | |
| qcom,rscs = <0xb6>; | |
| cell-id = <0x697f>; | |
| label = "ALC_DISPLAY"; | |
| qcom,bcm-name = "ALC"; | |
| phandle = <0x3ab>; | |
| qcom,bcm-dev; | |
| }; | |
| slv-qhs-tlmm1 { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2f3>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-tlmm1"; | |
| phandle = <0xc7>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| slv-qns-mem-noc-sf_display { | |
| qcom,agg-ports = <0x02>; | |
| cell-id = <0x5022>; | |
| qcom,buswidth = <0x20>; | |
| label = "slv-qns-mem-noc-sf_display"; | |
| qcom,connections = <0x15d>; | |
| phandle = <0x133>; | |
| qcom,bcms = <0x15e>; | |
| qcom,bus-dev = <0x131>; | |
| }; | |
| slv-qhs-cpr-cx { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x28b>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-cpr-cx"; | |
| phandle = <0xe9>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| bcm-sn6 { | |
| qcom,rscs = <0xb5>; | |
| cell-id = <0x1b70>; | |
| label = "SN6"; | |
| qcom,bcm-name = "SN6"; | |
| phandle = <0x154>; | |
| qcom,bcm-dev; | |
| }; | |
| slv-xs-pcie-modem { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2ca>; | |
| qcom,buswidth = <0x08>; | |
| label = "slv-xs-pcie-modem"; | |
| phandle = <0x126>; | |
| qcom,bcms = <0x155>; | |
| qcom,bus-dev = <0x11c>; | |
| }; | |
| slv-qhs-sdc4 { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x261>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-sdc4"; | |
| phandle = <0xc9>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| fab-aggre2_noc { | |
| qcom,base-name = "aggre2_noc-base"; | |
| qcom,sbm-offset = <0x00>; | |
| qcom,bus-type = <0x01>; | |
| cell-id = <0x1803>; | |
| clocks; | |
| label = "fab-aggre2_noc"; | |
| qcom,base-offset = <0x3000>; | |
| qcom,fab-dev; | |
| phandle = <0xbe>; | |
| qcom,qos-off = <0x1000>; | |
| }; | |
| rsc-disp { | |
| qcom,req_state = <0x02>; | |
| cell-id = <0x1f41>; | |
| label = "disp_rsc"; | |
| qcom,rsc-dev; | |
| phandle = <0xb6>; | |
| }; | |
| mas-qxm-crypto { | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x7d>; | |
| qcom,buswidth = <0x08>; | |
| label = "mas-qxm-crypto"; | |
| qcom,forwarding; | |
| qcom,connections = <0xbf>; | |
| qcom,blacklist = <0xba>; | |
| qcom,qport = <0x01>; | |
| phandle = <0x3b7>; | |
| qcom,bcms = <0xc0>; | |
| qcom,prio = <0x02>; | |
| qcom,bus-dev = <0xbe>; | |
| }; | |
| slv-srvc-aggre2-noc { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2ea>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-srvc-aggre2-noc"; | |
| phandle = <0xbd>; | |
| qcom,bus-dev = <0xbe>; | |
| }; | |
| mas-xm-pcie3-0 { | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2d>; | |
| qcom,buswidth = <0x08>; | |
| label = "mas-xm-pcie3-0"; | |
| qcom,connections = <0xc1>; | |
| qcom,blacklist = <0xba>; | |
| qcom,qport = <0x08>; | |
| phandle = <0x3b9>; | |
| qcom,prio = <0x02>; | |
| qcom,bus-dev = <0xbe>; | |
| }; | |
| slv-qhs-qup1 { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x312>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-qup1"; | |
| phandle = <0xf3>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| mas-llcc-mc_display { | |
| qcom,agg-ports = <0x04>; | |
| cell-id = <0x4e20>; | |
| qcom,buswidth = <0x04>; | |
| label = "mas-llcc-mc_display"; | |
| qcom,connections = <0x12e>; | |
| phandle = <0x157>; | |
| qcom,bus-dev = <0x12f>; | |
| }; | |
| mas-qnm-camnoc-sf { | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x02>; | |
| qcom,node-qos-bcms = <0x1b64 0x00 0x01>; | |
| cell-id = <0x89>; | |
| qcom,buswidth = <0x20>; | |
| label = "mas-qnm-camnoc-sf"; | |
| qcom,forwarding; | |
| qcom,connections = <0x10e>; | |
| qcom,qport = <0x00 0x01>; | |
| phandle = <0x3c7>; | |
| qcom,bcms = <0x10f>; | |
| qcom,prio = <0x00>; | |
| qcom,bus-dev = <0x10b>; | |
| }; | |
| mas-qhm-qdss-bam { | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x35>; | |
| qcom,buswidth = <0x04>; | |
| label = "mas-qhm-qdss-bam"; | |
| qcom,connections = <0xbf>; | |
| qcom,blacklist = <0xba>; | |
| qcom,qport = <0x0b>; | |
| phandle = <0x3b5>; | |
| qcom,prio = <0x02>; | |
| qcom,bus-dev = <0xbe>; | |
| }; | |
| mas-qhm-snoc-cfg { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x36>; | |
| qcom,buswidth = <0x04>; | |
| label = "mas-qhm-snoc-cfg"; | |
| qcom,connections = <0x11b>; | |
| phandle = <0x13f>; | |
| qcom,bus-dev = <0x11c>; | |
| }; | |
| slv-qhs-camera-cfg { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x24d>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-camera-cfg"; | |
| phandle = <0xc6>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| qcom,disable-ports = <0x00 0x01 0x02>; | |
| node-reg-names = "mmcx"; | |
| mmcx-supply = <0x69>; | |
| }; | |
| slv-qns-sys-pcie { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x324>; | |
| qcom,buswidth = <0x08>; | |
| label = "slv-qns-sys-pcie"; | |
| qcom,connections = <0x145>; | |
| phandle = <0x100>; | |
| qcom,bus-dev = <0xfe>; | |
| }; | |
| mas-llcc-mc { | |
| qcom,agg-ports = <0x04>; | |
| cell-id = <0x81>; | |
| qcom,buswidth = <0x04>; | |
| label = "mas-llcc-mc"; | |
| qcom,connections = <0x108>; | |
| phandle = <0x143>; | |
| qcom,bus-dev = <0x109>; | |
| }; | |
| bcm-sn4 { | |
| qcom,rscs = <0xb5>; | |
| cell-id = <0x1b6e>; | |
| label = "SN4"; | |
| qcom,bcm-name = "SN4"; | |
| phandle = <0x156>; | |
| qcom,bcm-dev; | |
| }; | |
| slv-qhs-sdc2 { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x260>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-sdc2"; | |
| phandle = <0xcb>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| slv-qhs-qdss-cfg { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x27b>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-qdss-cfg"; | |
| phandle = <0xd3>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| mas-qnm-video1 { | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x01>; | |
| qcom,node-qos-bcms = <0x1b64 0x00 0x01>; | |
| cell-id = <0x40>; | |
| qcom,buswidth = <0x20>; | |
| label = "mas-qnm-video1"; | |
| qcom,forwarding; | |
| qcom,connections = <0x10e>; | |
| qcom,qport = <0x0d>; | |
| phandle = <0x3c9>; | |
| qcom,bcms = <0x10f>; | |
| qcom,prio = <0x00>; | |
| qcom,bus-dev = <0x10b>; | |
| }; | |
| slv-qns-npu-sys { | |
| qcom,agg-ports = <0x02>; | |
| cell-id = <0x333>; | |
| qcom,buswidth = <0x20>; | |
| label = "slv-qns-npu-sys"; | |
| phandle = <0x110>; | |
| qcom,bus-dev = <0x111>; | |
| }; | |
| mas-qhm-a1noc-cfg { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x79>; | |
| qcom,buswidth = <0x04>; | |
| label = "mas-qhm-a1noc-cfg"; | |
| qcom,connections = <0xb7>; | |
| phandle = <0x13a>; | |
| qcom,bus-dev = <0xb8>; | |
| }; | |
| slv-qhs-imem-cfg { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x273>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-imem-cfg"; | |
| phandle = <0xe3>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| slv-qhs-ahb2phy1 { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x327>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-ahb2phy1"; | |
| phandle = <0xde>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| slv-qhs-npu-cfg { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x30e>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-npu-cfg"; | |
| qcom,connections = <0x13e>; | |
| phandle = <0xdc>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| slv-qns-llcc_display { | |
| qcom,agg-ports = <0x04>; | |
| cell-id = <0x5021>; | |
| qcom,buswidth = <0x10>; | |
| label = "slv-qns-llcc_display"; | |
| qcom,connections = <0x157>; | |
| phandle = <0x12c>; | |
| qcom,bcms = <0x158>; | |
| qcom,bus-dev = <0x12d>; | |
| }; | |
| bcm-mm1_display { | |
| qcom,rscs = <0xb6>; | |
| cell-id = <0x697b>; | |
| label = "MM1_DISPLAY"; | |
| qcom,bcm-name = "MM1"; | |
| phandle = <0x132>; | |
| qcom,bcm-dev; | |
| }; | |
| slv-qhs-aoss { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2ec>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-aoss"; | |
| phandle = <0xeb>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| slv-qhs-tcm { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x332>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-tcm"; | |
| phandle = <0x117>; | |
| qcom,bus-dev = <0x111>; | |
| }; | |
| rsc-apps { | |
| qcom,req_state = <0x02>; | |
| cell-id = <0x1f40>; | |
| label = "apps_rsc"; | |
| qcom,rsc-dev; | |
| phandle = <0xb5>; | |
| }; | |
| slv-qhs-cal-dp1 { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x32c>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-cal-dp1"; | |
| phandle = <0x119>; | |
| qcom,bus-dev = <0x111>; | |
| }; | |
| mas-qxm-mdp1 { | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x01>; | |
| qcom,node-qos-bcms = <0x1b64 0x00 0x01>; | |
| cell-id = <0x17>; | |
| qcom,buswidth = <0x20>; | |
| label = "mas-qxm-mdp1"; | |
| qcom,forwarding; | |
| qcom,connections = <0x10c>; | |
| qcom,qport = <0x08>; | |
| phandle = <0x3cc>; | |
| qcom,bcms = <0x10d>; | |
| qcom,prio = <0x00>; | |
| qcom,bus-dev = <0x10b>; | |
| }; | |
| mas-qnm-mnoc-hf { | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x02>; | |
| qcom,node-qos-bcms = <0x1b64 0x00 0x01>; | |
| cell-id = <0x84>; | |
| qcom,buswidth = <0x20>; | |
| label = "mas-qnm-mnoc-hf"; | |
| qcom,forwarding; | |
| qcom,connections = <0xfd>; | |
| qcom,qport = <0x02 0x42>; | |
| phandle = <0x149>; | |
| qcom,prio = <0x00>; | |
| qcom,bus-dev = <0xfe>; | |
| }; | |
| slv-qhs-qspi { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x31b>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-qspi"; | |
| phandle = <0xee>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| mas-amm-npu-sys-cdp-w { | |
| qcom,agg-ports = <0x02>; | |
| cell-id = <0xad>; | |
| qcom,buswidth = <0x10>; | |
| label = "mas-amm-npu-sys-cdp-w"; | |
| qcom,connections = <0x110>; | |
| phandle = <0x3cf>; | |
| qcom,bus-dev = <0x111>; | |
| }; | |
| mas-qxm-ipa { | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x01>; | |
| qcom,node-qos-bcms = <0x1b7b 0x00 0x01>; | |
| cell-id = <0x5a>; | |
| qcom,buswidth = <0x08>; | |
| label = "mas-qxm-ipa"; | |
| qcom,forwarding; | |
| qcom,connections = <0xbf>; | |
| qcom,blacklist = <0xba>; | |
| qcom,defer-init-qos; | |
| qcom,qport = <0x02>; | |
| phandle = <0x3b8>; | |
| qcom,prio = <0x02>; | |
| qcom,bus-dev = <0xbe>; | |
| }; | |
| fab-config_noc { | |
| qcom,base-name = "config_noc-base"; | |
| qcom,sbm-offset = <0x6000>; | |
| qcom,bus-type = <0x01>; | |
| cell-id = <0x1400>; | |
| clocks; | |
| label = "fab-config_noc"; | |
| qcom,base-offset = <0x00>; | |
| qcom,fab-dev; | |
| phandle = <0xf6>; | |
| qcom,qos-off = <0x00>; | |
| }; | |
| mas-qhm-a2noc-cfg { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x7c>; | |
| qcom,buswidth = <0x04>; | |
| label = "mas-qhm-a2noc-cfg"; | |
| qcom,connections = <0xbd>; | |
| phandle = <0x13b>; | |
| qcom,bus-dev = <0xbe>; | |
| }; | |
| fab-gem_noc_display { | |
| qcom,base-name = "gem_noc-base"; | |
| qcom,sbm-offset = <0x00>; | |
| qcom,bus-type = <0x01>; | |
| cell-id = <0x6593>; | |
| qcom,bypass-qos-prg; | |
| clocks; | |
| label = "fab-gem_noc_display"; | |
| qcom,base-offset = <0x21000>; | |
| qcom,fab-dev; | |
| phandle = <0x12d>; | |
| qcom,qos-off = <0x1000>; | |
| }; | |
| bcm-sn2 { | |
| qcom,rscs = <0xb5>; | |
| cell-id = <0x1b6c>; | |
| label = "SN2"; | |
| qcom,bcm-name = "SN2"; | |
| phandle = <0x14f>; | |
| qcom,bcm-dev; | |
| }; | |
| mas-ipa-core-master { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x8f>; | |
| qcom,buswidth = <0x08>; | |
| label = "mas-ipa-core-master"; | |
| qcom,connections = <0x106>; | |
| phandle = <0x3c4>; | |
| qcom,bus-dev = <0x107>; | |
| }; | |
| mas-qnm-aggre2-noc { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2750>; | |
| qcom,buswidth = <0x10>; | |
| label = "mas-qnm-aggre2-noc"; | |
| qcom,connections = <0x11d>; | |
| phandle = <0x137>; | |
| qcom,bcms = <0x11f>; | |
| qcom,bus-dev = <0x11c>; | |
| }; | |
| mas-qnm-cnoc { | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x76>; | |
| qcom,buswidth = <0x08>; | |
| label = "mas-qnm-cnoc"; | |
| qcom,forwarding; | |
| qcom,connections = <0xbf>; | |
| qcom,blacklist = <0xba>; | |
| qcom,qport = <0x00>; | |
| phandle = <0x140>; | |
| qcom,prio = <0x02>; | |
| qcom,bus-dev = <0xbe>; | |
| }; | |
| mas-xm-usb3-0 { | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x3d>; | |
| qcom,buswidth = <0x08>; | |
| label = "mas-xm-usb3-0"; | |
| qcom,connections = <0xb9>; | |
| qcom,qport = <0x00>; | |
| phandle = <0x3b3>; | |
| qcom,prio = <0x02>; | |
| qcom,bus-dev = <0xb8>; | |
| qcom,node-qos-clks { | |
| clock-names = "clk-usb3-prim-axi-no-rate"; | |
| clocks = <0x16 0x08>; | |
| }; | |
| }; | |
| mas-alc { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x90>; | |
| qcom,buswidth = <0x01>; | |
| label = "mas-alc"; | |
| phandle = <0x3d2>; | |
| qcom,bcms = <0x12b>; | |
| qcom,bus-dev = <0x109>; | |
| }; | |
| mas-qhm-qup2 { | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x99>; | |
| qcom,buswidth = <0x04>; | |
| label = "mas-qhm-qup2"; | |
| qcom,connections = <0xb9>; | |
| qcom,blacklist = <0xba>; | |
| qcom,qport = <0x06>; | |
| phandle = <0x3ae>; | |
| qcom,bcms = <0xbb>; | |
| qcom,prio = <0x02>; | |
| qcom,bus-dev = <0xb8>; | |
| }; | |
| mas-chm-apps { | |
| qcom,agg-ports = <0x02>; | |
| cell-id = <0x01>; | |
| qcom,buswidth = <0x20>; | |
| label = "mas-chm-apps"; | |
| qcom,connections = <0xfd 0xf9 0x100>; | |
| phandle = <0x3c2>; | |
| qcom,bcms = <0x101>; | |
| qcom,bus-dev = <0xfe>; | |
| }; | |
| slv-ipa-core-slave { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x309>; | |
| qcom,buswidth = <0x08>; | |
| label = "slv-ipa-core-slave"; | |
| phandle = <0x106>; | |
| qcom,bcms = <0x146>; | |
| qcom,bus-dev = <0x107>; | |
| }; | |
| bcm-co2 { | |
| qcom,rscs = <0xb5>; | |
| cell-id = <0x1b83>; | |
| label = "CO2"; | |
| qcom,bcm-name = "CO2"; | |
| phandle = <0xc4>; | |
| qcom,bcm-dev; | |
| }; | |
| slv-qhs-clk-ctl { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x26c>; | |
| qcom,buswidth = <0x04>; | |
| label = "slv-qhs-clk-ctl"; | |
| phandle = <0xf5>; | |
| qcom,bcms = <0xf7>; | |
| qcom,bus-dev = <0xf6>; | |
| }; | |
| bcm-mm2 { | |
| qcom,rscs = <0xb5>; | |
| cell-id = <0x1b65>; | |
| label = "MM2"; | |
| qcom,bcm-name = "MM2"; | |
| phandle = <0x14c>; | |
| qcom,bcm-dev; | |
| }; | |
| fab-compute_noc { | |
| qcom,base-name = "compute_noc-base"; | |
| qcom,sbm-offset = <0x00>; | |
| qcom,bus-type = <0x01>; | |
| cell-id = <0x180b>; | |
| clocks; | |
| label = "fab-compute_noc"; | |
| qcom,base-offset = <0x33000>; | |
| qcom,fab-dev; | |
| phandle = <0xc3>; | |
| qcom,qos-off = <0x800>; | |
| }; | |
| slv-qxs-imem { | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x249>; | |
| qcom,buswidth = <0x08>; | |
| label = "slv-qxs-imem"; | |
| phandle = <0x121>; | |
| qcom,bcms = <0x152>; | |
| qcom,bus-dev = <0x11c>; | |
| }; | |
| bcm-sh4 { | |
| qcom,rscs = <0xb5>; | |
| cell-id = <0x1b5f>; | |
| label = "SH4"; | |
| qcom,bcm-name = "SH4"; | |
| phandle = <0x101>; | |
| qcom,bcm-dev; | |
| }; | |
| mas-xm-pcie3-modem { | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x6c>; | |
| qcom,buswidth = <0x08>; | |
| label = "mas-xm-pcie3-modem"; | |
| qcom,connections = <0xbc>; | |
| qcom,blacklist = <0xba>; | |
| qcom,qport = <0x04>; | |
| phandle = <0x3b0>; | |
| qcom,prio = <0x02>; | |
| qcom,bus-dev = <0xb8>; | |
| }; | |
| }; | |
| qcom,smp2p_interrupt_rdbg_2_out { | |
| qcom,smem-state-names = "rdbg-smp2p-out"; | |
| compatible = "qcom,smp2p-interrupt-rdbg-2-out"; | |
| qcom,smem-states = <0x24f 0x00>; | |
| }; | |
| cti@6b00000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti-swao_cti0"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6b00000 0x1000>; | |
| phandle = <0x191>; | |
| }; | |
| qcom,spss@1880000 { | |
| clock-names = "xo"; | |
| reg-names = "sp2soc_irq_status\0sp2soc_irq_clr\0sp2soc_irq_mask\0rmb_err\0rmb_err_spare2"; | |
| qcom,spss-scsr-bits = <0x18 0x19>; | |
| qcom,proxy-timeout-ms = <0x2710>; | |
| vdd_mx-uV = <0x180 0x186a0>; | |
| qcom,pil-generic-irq-handler; | |
| memory-region = <0x86>; | |
| interrupts = <0x00 0x160 0x01>; | |
| clocks = <0x15 0x00>; | |
| qcom,signal-aop; | |
| qcom,complete-ramdump; | |
| vdd_mx-supply = <0x6a>; | |
| qcom,pas-id = <0x0e>; | |
| qcom,extra-size = <0x1000>; | |
| compatible = "qcom,pil-tz-generic"; | |
| status = "ok"; | |
| qcom,vdd_cx-uV-uA = <0x180 0x186a0>; | |
| reg = <0x188101c 0x04 0x1881024 0x04 0x1881028 0x04 0x188103c 0x04 0x1882014 0x04>; | |
| mboxes = <0x02 0x00>; | |
| vdd_cx-supply = <0x67>; | |
| qcom,proxy-clock-names = "xo"; | |
| qcom,proxy-reg-names = "vdd_cx"; | |
| qcom,firmware-name = "spss"; | |
| mbox-names = "spss-pil"; | |
| }; | |
| qcom,msm-dai-tdm-sen-tx { | |
| qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
| qcom,msm-cpudai-tdm-data-out = <0x00>; | |
| qcom,msm-cpudai-tdm-data-delay = <0x01>; | |
| qcom,msm-cpudai-tdm-group-port-id = <0x9051>; | |
| qcom,msm-cpudai-tdm-group-num-ports = <0x01>; | |
| qcom,msm-cpudai-tdm-invert-sync = <0x01>; | |
| compatible = "qcom,msm-dai-tdm"; | |
| qcom,msm-cpudai-tdm-group-id = <0x9151>; | |
| phandle = <0x5f1>; | |
| qcom,msm-cpudai-tdm-sync-src = <0x01>; | |
| qcom,msm-cpudai-tdm-clk-internal = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-mode = <0x01>; | |
| qcom,msm-dai-q6-tdm-sen-tx-0 { | |
| qcom,msm-cpudai-tdm-dev-id = <0x9051>; | |
| qcom,msm-cpudai-tdm-data-align = <0x00>; | |
| compatible = "qcom,msm-dai-q6-tdm"; | |
| phandle = <0x314>; | |
| }; | |
| }; | |
| qcom,lpass@17300000 { | |
| qcom,smem-state-names = "qcom,force-stop"; | |
| qcom,smem-id = <0x1a7>; | |
| qcom,sysmon-id = <0x01>; | |
| qcom,vdd_mx-uV-uA = <0x180 0x00>; | |
| qcom,ssctl-instance-id = <0x14>; | |
| clock-names = "xo"; | |
| qcom,proxy-timeout-ms = <0x2710>; | |
| memory-region = <0x93>; | |
| clocks = <0x15 0x00>; | |
| qcom,signal-aop; | |
| qcom,complete-ramdump; | |
| vdd_mx-supply = <0x92>; | |
| qcom,pas-id = <0x01>; | |
| interrupts-extended = <0x76 0x06 0x04 0x94 0x00 0x00 0x94 0x02 0x00 0x94 0x01 0x00 0x94 0x03 0x00>; | |
| compatible = "qcom,pil-tz-generic"; | |
| qcom,vdd_cx-uV-uA = <0x180 0x00>; | |
| interrupt-names = "qcom,wdog\0qcom,err-fatal\0qcom,proxy-unvote\0qcom,err-ready\0qcom,stop-ack"; | |
| reg = <0x17300000 0x100>; | |
| qcom,smem-states = <0x95 0x00>; | |
| mboxes = <0x02 0x00>; | |
| vdd_cx-supply = <0x91>; | |
| qcom,proxy-clock-names = "xo"; | |
| qcom,proxy-reg-names = "vdd_cx\0vdd_mx"; | |
| qcom,firmware-name = "adsp"; | |
| mbox-names = "adsp-pil"; | |
| }; | |
| qcom,pcie@1c00000 { | |
| pinctrl-names = "default\0sleep"; | |
| qcom,vreg-0p9-voltage-level = <0xd6d80 0xd6d80 0x11f1c>; | |
| #address-cells = <0x03>; | |
| dma-coherent; | |
| qcom,drv-l1ss-timeout-us = <0x2710>; | |
| pinctrl-0 = <0x167 0x168 0x169>; | |
| clock-names = "pcie_0_pipe_clk\0pcie_0_ref_clk_src\0pcie_0_aux_clk\0pcie_0_cfg_ahb_clk\0pcie_0_mstr_axi_clk\0pcie_0_slv_axi_clk\0pcie_0_ldo\0pcie_0_slv_q2a_axi_clk\0pcie_tbu_clk\0pcie_phy_refgen_clk\0pcie_ddrss_sf_tbu_clk"; | |
| reg-names = "parf\0phy\0dm_core\0elbi\0iatu\0conf"; | |
| qcom,phy-power-down-offset = <0x840>; | |
| qcom,msm-bus,name = "pcie0"; | |
| qcom,pcie-phy-ver = <0x44e>; | |
| cell-index = <0x00>; | |
| resets = <0x16 0x04 0x16 0x07>; | |
| qcom,bw-scale = <0x40 0x124f800 0x40 0x124f800 0x100 0x5f5e100>; | |
| interrupts = <0x00 0x01 0x02 0x03 0x04>; | |
| clocks = <0x16 0x36 0x15 0x00 0x16 0x32 0x16 0x34 0x16 0x35 0x16 0x37 0x16 0x4a 0x16 0x38 0x16 0x03 0x16 0x2f 0x16 0x17>; | |
| qcom,smmu-sid-base = <0x1c00>; | |
| interrupt-map = <0x00 0x00 0x00 0x00 0x01 0x00 0x8c 0x04 0x00 0x00 0x00 0x01 0x01 0x00 0x95 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0x96 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x97 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0x98 0x04>; | |
| max-clock-frequency-hz = <0x00 0x00 0x124f800 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x5f5e100 0x00>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| #size-cells = <0x02>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| qcom,boot-option = <0x01>; | |
| interrupt-parent = <0x165>; | |
| qcom,vreg-1p8-voltage-level = <0x124f80 0x124f80 0x3e80>; | |
| qcom,l1-2-th-scale = <0x02>; | |
| qcom,phy-status-offset = <0x814>; | |
| interrupt-map-mask = <0x00 0x00 0x00 0xffffffff>; | |
| wake-gpio = <0x66 0x51 0x00>; | |
| vreg-0p9-supply = <0x7c>; | |
| qcom,drv-supported; | |
| compatible = "qcom,pci-msm"; | |
| ranges = <0x1000000 0x00 0x60200000 0x60200000 0x00 0x100000 0x2000000 0x00 0x60300000 0x60300000 0x00 0x3d00000>; | |
| #interrupt-cells = <0x01>; | |
| pinctrl-1 = <0x16a 0x168 0x169>; | |
| interrupt-names = "int_global_int\0int_a\0int_b\0int_c\0int_d"; | |
| vreg-1p8-supply = <0x7d>; | |
| reg = <0x1c00000 0x3000 0x1c06000 0x1000 0x60000000 0xf1d 0x60000f20 0xa8 0x60001000 0x1000 0x60100000 0x100000>; | |
| linux,pci-domain = <0x00>; | |
| phandle = <0x165>; | |
| qcom,msm-bus,vectors-KBps = <0x2d 0x200 0x00 0x00 0x2d 0x200 0x1f4 0x320>; | |
| gdsc-vdd-supply = <0x16b>; | |
| iommu-map = <0x00 0x47 0x1c00 0x01 0x100 0x47 0x1c01 0x01>; | |
| msi-parent = <0x166>; | |
| qcom,no-l0s-supported; | |
| reset-names = "pcie_0_core_reset\0pcie_0_phy_reset"; | |
| qcom,l1-2-th-value = <0x46>; | |
| qcom,ep-latency = <0x0a>; | |
| vreg-cx-supply = <0x67>; | |
| qcom,use-19p2mhz-aux-clk; | |
| perst-gpio = <0x66 0x4f 0x00>; | |
| qcom,vreg-cx-voltage-level = <0xffff 0x100 0x00>; | |
| qcom,phy-status-bit = <0x06>; | |
| qcom,slv-addr-space-size = <0x4000000>; | |
| qcom,phy-sequence = <0x840 0x03 0x00 0x94 0x08 0x00 0x154 0x34 0x00 0x16c 0x08 0x00 0x58 0x0f 0x00 0xa4 0x42 0x00 0x110 0x24 0x00 0x11c 0x03 0x00 0x118 0xb4 0x00 0x10c 0x02 0x00 0x1bc 0x11 0x00 0xbc 0x82 0x00 0xd4 0x03 0x00 0xd0 0x55 0x00 0xcc 0x55 0x00 0xb0 0x1a 0x00 0xac 0x0a 0x00 0xc4 0x68 0x00 0xe0 0x02 0x00 0xdc 0xaa 0x00 0xd8 0xab 0x00 0xb8 0x34 0x00 0xb4 0x14 0x00 0x158 0x01 0x00 0x74 0x06 0x00 0x7c 0x16 0x00 0x84 0x36 0x00 0x78 0x06 0x00 0x80 0x16 0x00 0x88 0x36 0x00 0x1b0 0x1e 0x00 0x1ac 0xca 0x00 0x1b8 0x18 0x00 0x1b4 0xa2 0x00 0x50 0x07 0x00 0x10 0x01 0x00 0x1c 0x31 0x00 0x20 0x01 0x00 0x24 0xde 0x00 0x28 0x07 0x00 0x30 0x4c 0x00 0x34 0x06 0x00 0x29c 0x12 0x00 0x284 0x35 0x00 0x23c 0x11 0x00 0x51c 0x03 0x00 0x518 0x1c 0x00 0x524 0x1e 0x00 0x4e8 0x00 0x00 0x4ec 0x0e 0x00 0x4f0 0x4a 0x00 0x4f4 0x0f 0x00 0x5b4 0x04 0x00 0x434 0x7f 0x00 0x444 0x70 0x00 0x510 0x17 0x00 0x4d4 0x04 0x00 0x4d8 0x07 0x00 0x598 0xd4 0x00 0x59c 0x54 0x00 0x5a0 0xdb 0x00 0x5a4 0x3b 0x00 0x5a8 0x31 0x00 0x584 0x24 0x00 0x588 0xe4 0x00 0x58c 0xec 0x00 0x590 0x3b 0x00 0x594 0x36 0x00 0x570 0x3f 0x00 0x574 0x3f 0x00 0x578 0xff 0x00 0x57c 0x7f 0x00 0x580 0x14 0x00 0x4fc 0x00 0x00 0x4f8 0xc0 0x00 0x460 0x30 0x00 0x464 0x00 0x00 0x5bc 0x0c 0x00 0x4dc 0x1b 0x00 0x408 0x0c 0x00 0x414 0x03 0x00 0x5b8 0x30 0x00 0x9a4 0x01 0x00 0xc90 0x00 0x00 0xc40 0x01 0x00 0xc48 0x01 0x00 0xc50 0x00 0x00 0xcb4 0x33 0x00 0xcbc 0x00 0x00 0xce0 0x58 0x00 0xca4 0x0f 0x00 0x48 0x90 0x00 0xc1c 0xc1 0x00 0x988 0x77 0x00 0x998 0x0b 0x00 0x8dc 0x0d 0x00 0x9ec 0x12 0x00 0x800 0x00 0x00 0x844 0x03 0x00>; | |
| pcie0_rp { | |
| #address-cells = <0x05>; | |
| #size-cells = <0x00>; | |
| reg = <0x00 0x00 0x00 0x00 0x00>; | |
| phandle = <0x3d9>; | |
| cnss_pci { | |
| #address-cells = <0x01>; | |
| memory-region = <0x16d>; | |
| #size-cells = <0x01>; | |
| qcom,iommu-group = <0x16c>; | |
| reg = <0x00 0x00 0x00 0x00 0x00>; | |
| phandle = <0x3da>; | |
| cnss_pci_iommu_group { | |
| qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; | |
| phandle = <0x16c>; | |
| qcom,iommu-pagetable = "coherent"; | |
| qcom,iommu-faults = "stall-disable\0HUPCF\0no-CFRE\0non-fatal"; | |
| qcom,iommu-dma = "fastmap"; | |
| }; | |
| }; | |
| }; | |
| }; | |
| lmh_isense_cdsp { | |
| compatible = "qcom,msm-limits-cdsp"; | |
| }; | |
| spi@990000 { | |
| pinctrl-names = "default\0sleep"; | |
| #address-cells = <0x01>; | |
| pinctrl-0 = <0x299>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| reg-names = "se_phys"; | |
| interrupts = <0x00 0x25d 0x04>; | |
| clocks = <0x16 0x60 0x16 0x84 0x16 0x85>; | |
| #size-cells = <0x00>; | |
| qcom,wrapper-core = <0x274>; | |
| spi-max-frequency = <0x2faf080>; | |
| dma-names = "tx\0rx"; | |
| compatible = "qcom,spi-geni"; | |
| pinctrl-1 = <0x29a>; | |
| status = "disabled"; | |
| reg = <0x990000 0x4000>; | |
| phandle = <0x5ac>; | |
| dmas = <0x280 0x00 0x04 0x01 0x40 0x00 0x280 0x01 0x04 0x01 0x40 0x00>; | |
| }; | |
| qfprom@780000 { | |
| #address-cells = <0x01>; | |
| read-only; | |
| #size-cells = <0x01>; | |
| compatible = "qcom,qfprom"; | |
| ranges; | |
| reg = <0x784000 0x3000>; | |
| phandle = <0x3a9>; | |
| gpu_lm_efuse@5c8 { | |
| reg = <0x5c8 0x04>; | |
| phandle = <0x334>; | |
| }; | |
| gpu_speed_bin@19b { | |
| bits = <0x05 0x03>; | |
| reg = <0x19b 0x01>; | |
| phandle = <0x335>; | |
| }; | |
| }; | |
| qcom,msm-dai-q6-hdmi { | |
| compatible = "qcom,msm-dai-q6-hdmi"; | |
| qcom,msm-dai-q6-dev-id = <0x08>; | |
| phandle = <0x5ce>; | |
| }; | |
| qcom,gdsc@106004 { | |
| qcom,retain-regs; | |
| regulator-name = "pcie_2_gdsc"; | |
| compatible = "qcom,gdsc"; | |
| reg = <0x106004 0x04>; | |
| phandle = <0x178>; | |
| }; | |
| qcom,dsi-display-primary { | |
| pinctrl-names = "panel_active\0panel_suspend"; | |
| avdd-supply = <0x63c>; | |
| qcom,panel-te-source = <0x00>; | |
| pinctrl-0 = <0x40f 0x413>; | |
| clock-names = "mux_byte_clk0\0mux_pixel_clk0\0src_byte_clk0\0src_pixel_clk0\0cphy_byte_clk0\0cphy_pixel_clk0\0shadow_byte_clk0\0shadow_pixel_clk0\0shadow_cphybyte_clk0\0shadow_cphypixel_clk0\0mux_byte_clk1\0mux_pixel_clk1\0src_byte_clk1\0src_pixel_clk1\0cphy_byte_clk1\0cphy_pixel_clk1\0shadow_byte_clk1\0shadow_pixel_clk1\0shadow_cphybyte_clk1\0shadow_cphypixel_clk1"; | |
| clocks = <0x55b 0x06 0x55b 0x09 0x55b 0x03 0x55b 0x08 0x55b 0x12 0x55b 0x15 0x55b 0x0d 0x55b 0x11 0x55b 0x16 0x55b 0x19 0x55c 0x20 0x55c 0x23 0x55c 0x1d 0x55c 0x22 0x55c 0x2c 0x55c 0x2f 0x55c 0x27 0x55c 0x2b 0x55c 0x30 0x55c 0x33>; | |
| label = "primary"; | |
| vdd-supply = <0x80>; | |
| ibb-supply = <0x63e>; | |
| qcom,dsi-phy = <0x559 0x55a>; | |
| compatible = "qcom,dsi-display"; | |
| vddio-supply = <0x7e>; | |
| pinctrl-1 = <0x410 0x414>; | |
| lab-supply = <0x63d>; | |
| phandle = <0x644>; | |
| qcom,dsi-ctrl = <0x557 0x558>; | |
| qcom,dsi-default-panel = <0x63f>; | |
| qcom,mdp = <0x24c>; | |
| qcom,platform-te-gpio = <0x66 0x42 0x00>; | |
| }; | |
| syscon@1880000 { | |
| compatible = "syscon"; | |
| reg = <0x1880000 0x10000>; | |
| phandle = <0x84>; | |
| }; | |
| qrng@793000 { | |
| qcom,msm-rng-iface-clk; | |
| clock-names = "iface_clk"; | |
| qcom,no-qrng-config; | |
| qcom,msm-bus,name = "msm-rng-noc"; | |
| clocks = <0x16 0x50>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| compatible = "qcom,msm-rng"; | |
| reg = <0x793000 0x1000>; | |
| phandle = <0x370>; | |
| qcom,msm-bus,vectors-KBps = <0x01 0x26a 0x00 0x00 0x01 0x26a 0x00 0x493e0>; | |
| }; | |
| qcom,npu-llcc-ddr-bw { | |
| qcom,src-dst-ports = <0x302 0x200>; | |
| governor = "performance"; | |
| compatible = "qcom,devbw-ddr"; | |
| phandle = <0x52>; | |
| operating-points-v2 = <0x51>; | |
| }; | |
| spi@a80000 { | |
| pinctrl-names = "default\0sleep"; | |
| #address-cells = <0x01>; | |
| pinctrl-0 = <0x2b1>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| reg-names = "se_phys"; | |
| interrupts = <0x00 0x161 0x04>; | |
| clocks = <0x16 0x6a 0x16 0x86 0x16 0x87>; | |
| #size-cells = <0x00>; | |
| qcom,wrapper-core = <0x2a3>; | |
| spi-max-frequency = <0x2faf080>; | |
| dma-names = "tx\0rx"; | |
| compatible = "qcom,spi-geni"; | |
| pinctrl-1 = <0x2b1>; | |
| status = "disabled"; | |
| reg = <0xa80000 0x4000>; | |
| phandle = <0x5b7>; | |
| dmas = <0x2a4 0x00 0x00 0x01 0x40 0x00 0x2a4 0x01 0x00 0x01 0x40 0x00>; | |
| }; | |
| i2c@98c000 { | |
| pinctrl-names = "default\0sleep"; | |
| #address-cells = <0x01>; | |
| pinctrl-0 = <0x287>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| interrupts = <0x00 0x25c 0x04>; | |
| clocks = <0x16 0x5e 0x16 0x84 0x16 0x85>; | |
| #size-cells = <0x00>; | |
| qcom,wrapper-core = <0x274>; | |
| dma-names = "tx\0rx"; | |
| compatible = "qcom,i2c-geni"; | |
| pinctrl-1 = <0x288>; | |
| status = "ok"; | |
| reg = <0x98c000 0x4000>; | |
| phandle = <0x5a3>; | |
| dmas = <0x280 0x00 0x03 0x03 0x40 0x00 0x280 0x01 0x03 0x03 0x40 0x00>; | |
| bq27541@55 { | |
| compatible = "ti,bq27541"; | |
| reg = <0x55>; | |
| }; | |
| }; | |
| refgen-regulator@88e7000 { | |
| regulator-enable-ramp-delay = <0x05>; | |
| regulator-name = "refgen"; | |
| compatible = "qcom,refgen-kona-regulator"; | |
| qcom,proxy-consumer-enable; | |
| reg = <0x88e7000 0x84>; | |
| phandle = <0xb4>; | |
| proxy-supply = <0xb4>; | |
| }; | |
| keepalive-opp-table { | |
| compatible = "operating-points-v2"; | |
| phandle = <0x4a>; | |
| opp-1 { | |
| opp-hz = <0x00 0x01>; | |
| }; | |
| }; | |
| cti@6e0d000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti-ddr_dl_1_cti_1"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6e0d000 0x1000>; | |
| phandle = <0x510>; | |
| }; | |
| qcom,msm-dai-tdm-quat-tx { | |
| qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
| qcom,msm-cpudai-tdm-data-out = <0x00>; | |
| qcom,msm-cpudai-tdm-data-delay = <0x01>; | |
| qcom,msm-cpudai-tdm-group-port-id = <0x9031>; | |
| qcom,msm-cpudai-tdm-group-num-ports = <0x01>; | |
| qcom,msm-cpudai-tdm-invert-sync = <0x01>; | |
| compatible = "qcom,msm-dai-tdm"; | |
| qcom,msm-cpudai-tdm-group-id = <0x9131>; | |
| phandle = <0x5ed>; | |
| qcom,msm-cpudai-tdm-sync-src = <0x01>; | |
| qcom,msm-cpudai-tdm-clk-internal = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-mode = <0x01>; | |
| qcom,msm-dai-q6-tdm-quat-tx-0 { | |
| qcom,msm-cpudai-tdm-dev-id = <0x9031>; | |
| qcom,msm-cpudai-tdm-data-align = <0x00>; | |
| compatible = "qcom,msm-dai-q6-tdm"; | |
| phandle = <0x310>; | |
| }; | |
| }; | |
| thermal-zones { | |
| phandle = <0x34a>; | |
| pm8150b_tz { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x64>; | |
| thermal-sensors = <0x62d>; | |
| thermal-governor = "step_wise"; | |
| phandle = <0x6b2>; | |
| wake-capable-sensor; | |
| trips { | |
| trip2 { | |
| temperature = <0x23668>; | |
| hysteresis = <0x00>; | |
| type = "passive"; | |
| }; | |
| trip0 { | |
| temperature = <0x17318>; | |
| hysteresis = <0x00>; | |
| type = "passive"; | |
| phandle = <0x6b3>; | |
| }; | |
| trip1 { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x00>; | |
| type = "passive"; | |
| phandle = <0x6b4>; | |
| }; | |
| }; | |
| }; | |
| cmpss-usr { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x1a 0x06>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| active-config1 { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| apc-0-max-step { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "step_wise"; | |
| wake-capable-sensor; | |
| trips { | |
| silver-trip { | |
| temperature = <0x1d4c0>; | |
| hysteresis = <0x00>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| cpu-0-2-usr { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x19 0x03>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| active-config1 { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| pm8150l-bcl-lvl1 { | |
| polling-delay = <0x00>; | |
| disable-thermal-zone; | |
| polling-delay-passive = <0x64>; | |
| thermal-sensors = <0x634 0x06>; | |
| thermal-governor = "step_wise"; | |
| wake-capable-sensor; | |
| trips { | |
| l-bcl-lvl1 { | |
| temperature = <0x01>; | |
| hysteresis = <0x01>; | |
| type = "passive"; | |
| phandle = <0x690>; | |
| }; | |
| }; | |
| cooling-maps { | |
| vph_cpu6 { | |
| trip = <0x690>; | |
| cooling-device = <0x2f 0x01 0x01>; | |
| }; | |
| vph_gpu1 { | |
| trip = <0x690>; | |
| cooling-device = <0x1c 0x04 0x04>; | |
| }; | |
| vph_cpu7 { | |
| trip = <0x690>; | |
| cooling-device = <0x32 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| cpuss-0-usr { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x19 0x05>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| active-config1 { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| modem-mmw2-usr { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x46 0x6c>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| cpu-1-1-usr { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x19 0x08>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| active-config1 { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| cpu-1-5-usr { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x19 0x0c>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| active-config1 { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| modem-streamer-usr { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x46 0x71>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| cmpss-step { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x1a 0x06>; | |
| thermal-governor = "step_wise"; | |
| wake-capable-sensor; | |
| trips { | |
| cmpss-trip0 { | |
| temperature = <0x186a0>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| phandle = <0x44>; | |
| }; | |
| }; | |
| cooling-maps { | |
| modem-tj-cdev { | |
| trip = <0x44>; | |
| cooling-device = <0x3e 0x03 0x03>; | |
| }; | |
| npu_cdev { | |
| trip = <0x44>; | |
| cooling-device = <0x3f 0xfffffffb 0xfffffffb>; | |
| }; | |
| modem-pa-cdev { | |
| trip = <0x44>; | |
| cooling-device = <0x3d 0x03 0x03>; | |
| }; | |
| cdsp-cdev { | |
| trip = <0x44>; | |
| cooling-device = <0x3c 0x03 0x03>; | |
| }; | |
| gpu-cdev { | |
| trip = <0x44>; | |
| cooling-device = <0x1c 0xfffffffd 0xfffffffd>; | |
| }; | |
| }; | |
| }; | |
| cpu-1-4-step { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x19 0x0b>; | |
| thermal-governor = "step_wise"; | |
| wake-capable-sensor; | |
| trips { | |
| cpu14-config { | |
| temperature = <0x1adb0>; | |
| hysteresis = <0x2710>; | |
| type = "passive"; | |
| phandle = <0x34>; | |
| }; | |
| cpufreq-14-config { | |
| temperature = <0x124f8>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| phandle = <0x33>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cpu14_cdev { | |
| trip = <0x34>; | |
| cooling-device = <0x29 0x01 0x01>; | |
| }; | |
| cpufreq_cdev { | |
| trip = <0x33>; | |
| cooling-device = <0x27 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| skin-therm-usr { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x6a1 0x4d>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| q6-hvx-step { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x1a 0x04>; | |
| thermal-governor = "step_wise"; | |
| wake-capable-sensor; | |
| trips { | |
| q6-hvx-trip0 { | |
| temperature = <0x186a0>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| phandle = <0x42>; | |
| }; | |
| }; | |
| cooling-maps { | |
| modem-tj-cdev { | |
| trip = <0x42>; | |
| cooling-device = <0x3e 0x03 0x03>; | |
| }; | |
| npu_cdev { | |
| trip = <0x42>; | |
| cooling-device = <0x3f 0xfffffffb 0xfffffffb>; | |
| }; | |
| modem-pa-cdev { | |
| trip = <0x42>; | |
| cooling-device = <0x3d 0x03 0x03>; | |
| }; | |
| cdsp-cdev { | |
| trip = <0x42>; | |
| cooling-device = <0x3c 0x03 0x03>; | |
| }; | |
| gpu-cdev { | |
| trip = <0x42>; | |
| cooling-device = <0x1c 0xfffffffd 0xfffffffd>; | |
| }; | |
| }; | |
| }; | |
| modem-mmw0-mod-usr { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x46 0x72>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| q6-hvx-usr { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x1a 0x04>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| active-config1 { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| pm8150l-vph-lvl2 { | |
| polling-delay = <0x00>; | |
| tracks-low; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x634 0x04>; | |
| thermal-governor = "low_limits_cap"; | |
| wake-capable-sensor; | |
| trips { | |
| vph-lvl2 { | |
| temperature = <0x9c4>; | |
| hysteresis = <0xc8>; | |
| type = "passive"; | |
| phandle = <0x6d1>; | |
| }; | |
| }; | |
| }; | |
| modem-1-usr { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x46 0x7d>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| cpu-0-3-step { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x19 0x04>; | |
| thermal-governor = "step_wise"; | |
| wake-capable-sensor; | |
| trips { | |
| cpu03-config { | |
| temperature = <0x1adb0>; | |
| hysteresis = <0x2710>; | |
| type = "passive"; | |
| phandle = <0x24>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cpu03_cdev { | |
| trip = <0x24>; | |
| cooling-device = <0x25 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| pop-mem-step { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x0a>; | |
| thermal-sensors = <0x1a 0x03>; | |
| thermal-governor = "step_wise"; | |
| wake-capable-sensor; | |
| trips { | |
| pop-trip { | |
| temperature = <0x17318>; | |
| hysteresis = <0x00>; | |
| type = "passive"; | |
| phandle = <0x1d>; | |
| }; | |
| }; | |
| cooling-maps { | |
| pop_cdev4 { | |
| trip = <0x1d>; | |
| cooling-device = <0x11 0xffffffff 0xffffffff>; | |
| }; | |
| pop_cdev7 { | |
| trip = <0x1d>; | |
| cooling-device = <0x14 0xffffffff 0xffffffff>; | |
| }; | |
| }; | |
| }; | |
| cwlan-step { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x1a 0x01>; | |
| thermal-governor = "step_wise"; | |
| wake-capable-sensor; | |
| trips { | |
| cwlan-trip0 { | |
| temperature = <0x186a0>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| phandle = <0x3b>; | |
| }; | |
| }; | |
| cooling-maps { | |
| modem-tj-cdev { | |
| trip = <0x3b>; | |
| cooling-device = <0x3e 0x03 0x03>; | |
| }; | |
| npu_cdev { | |
| trip = <0x3b>; | |
| cooling-device = <0x3f 0xfffffffb 0xfffffffb>; | |
| }; | |
| modem-pa-cdev { | |
| trip = <0x3b>; | |
| cooling-device = <0x3d 0x03 0x03>; | |
| }; | |
| cdsp-cdev { | |
| trip = <0x3b>; | |
| cooling-device = <0x3c 0x03 0x03>; | |
| }; | |
| gpu-cdev { | |
| trip = <0x3b>; | |
| cooling-device = <0x1c 0xfffffffd 0xfffffffd>; | |
| }; | |
| }; | |
| }; | |
| pm8150b-vbat-lvl1 { | |
| polling-delay = <0x00>; | |
| tracks-low; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x62e 0x03>; | |
| thermal-governor = "low_limits_cap"; | |
| wake-capable-sensor; | |
| trips { | |
| vbat-lvl1 { | |
| temperature = <0xaf0>; | |
| hysteresis = <0xc8>; | |
| type = "passive"; | |
| phandle = <0x6b8>; | |
| }; | |
| }; | |
| }; | |
| apc-1-max-step { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "step_wise"; | |
| wake-capable-sensor; | |
| trips { | |
| gold-trip { | |
| temperature = <0x1d4c0>; | |
| hysteresis = <0x00>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| ddr-step { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x1a 0x03>; | |
| thermal-governor = "step_wise"; | |
| wake-capable-sensor; | |
| trips { | |
| ddr-trip0 { | |
| temperature = <0x186a0>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| phandle = <0x41>; | |
| }; | |
| }; | |
| cooling-maps { | |
| modem-tj-cdev { | |
| trip = <0x41>; | |
| cooling-device = <0x3e 0x03 0x03>; | |
| }; | |
| npu_cdev { | |
| trip = <0x41>; | |
| cooling-device = <0x3f 0xfffffffb 0xfffffffb>; | |
| }; | |
| modem-pa-cdev { | |
| trip = <0x41>; | |
| cooling-device = <0x3d 0x03 0x03>; | |
| }; | |
| cdsp-cdev { | |
| trip = <0x41>; | |
| cooling-device = <0x3c 0x03 0x03>; | |
| }; | |
| gpu-cdev { | |
| trip = <0x41>; | |
| cooling-device = <0x1c 0xfffffffd 0xfffffffd>; | |
| }; | |
| }; | |
| }; | |
| cpu-1-3-step { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x19 0x0a>; | |
| thermal-governor = "step_wise"; | |
| wake-capable-sensor; | |
| trips { | |
| cpu13-config { | |
| temperature = <0x1adb0>; | |
| hysteresis = <0x2710>; | |
| type = "passive"; | |
| phandle = <0x31>; | |
| }; | |
| cpufreq-13-config { | |
| temperature = <0x124f8>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| phandle = <0x30>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cpu13_cdev { | |
| trip = <0x31>; | |
| cooling-device = <0x32 0x01 0x01>; | |
| }; | |
| cpufreq_cdev { | |
| trip = <0x30>; | |
| cooling-device = <0x27 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| camera-step { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x1a 0x05>; | |
| thermal-governor = "step_wise"; | |
| wake-capable-sensor; | |
| trips { | |
| camera-trip0 { | |
| temperature = <0x186a0>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| phandle = <0x43>; | |
| }; | |
| }; | |
| cooling-maps { | |
| modem-tj-cdev { | |
| trip = <0x43>; | |
| cooling-device = <0x3e 0x03 0x03>; | |
| }; | |
| npu_cdev { | |
| trip = <0x43>; | |
| cooling-device = <0x3f 0xfffffffb 0xfffffffb>; | |
| }; | |
| modem-pa-cdev { | |
| trip = <0x43>; | |
| cooling-device = <0x3d 0x03 0x03>; | |
| }; | |
| cdsp-cdev { | |
| trip = <0x43>; | |
| cooling-device = <0x3c 0x03 0x03>; | |
| }; | |
| gpu-cdev { | |
| trip = <0x43>; | |
| cooling-device = <0x1c 0xfffffffd 0xfffffffd>; | |
| }; | |
| }; | |
| }; | |
| modem-lte-sub6-pa1 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x46 0x64>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| cpu-0-3-usr { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x19 0x04>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| active-config1 { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| cpuss-1-usr { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x19 0x06>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| active-config1 { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| cwlan-usr { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x1a 0x01>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| active-config1 { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| camera-usr { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x1a 0x05>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| active-config1 { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| pm8150l-vph-lvl0 { | |
| polling-delay = <0x00>; | |
| tracks-low; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x634 0x02>; | |
| thermal-governor = "low_limits_cap"; | |
| wake-capable-sensor; | |
| trips { | |
| vph-lvl0 { | |
| temperature = <0xbb8>; | |
| hysteresis = <0xc8>; | |
| type = "passive"; | |
| phandle = <0x6cf>; | |
| }; | |
| }; | |
| }; | |
| pm8150b-bcl-lvl2 { | |
| polling-delay = <0x00>; | |
| disable-thermal-zone; | |
| polling-delay-passive = <0x64>; | |
| thermal-sensors = <0x62e 0x07>; | |
| thermal-governor = "step_wise"; | |
| wake-capable-sensor; | |
| trips { | |
| b-bcl-lvl2 { | |
| temperature = <0x01>; | |
| hysteresis = <0x01>; | |
| type = "passive"; | |
| phandle = <0x68e>; | |
| }; | |
| }; | |
| cooling-maps { | |
| vbat_gpu2 { | |
| trip = <0x68e>; | |
| cooling-device = <0x1c 0xfffffffe 0xfffffffe>; | |
| }; | |
| }; | |
| }; | |
| modem-mmw3-usr { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x46 0x6d>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| cpu-1-2-usr { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x19 0x09>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| active-config1 { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| modem-mmw2-mod-usr { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x46 0x74>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| soc { | |
| polling-delay = <0x00>; | |
| tracks-low; | |
| disable-thermal-zone; | |
| polling-delay-passive = <0x64>; | |
| thermal-sensors = <0x62f>; | |
| thermal-governor = "low_limits_cap"; | |
| wake-capable-sensor; | |
| trips { | |
| soc-trip { | |
| temperature = <0x0a>; | |
| hysteresis = <0x00>; | |
| type = "passive"; | |
| phandle = <0x68b>; | |
| }; | |
| }; | |
| cooling-maps { | |
| soc_cpu7 { | |
| trip = <0x68b>; | |
| cooling-device = <0x32 0x01 0x01>; | |
| }; | |
| soc_cpu5 { | |
| trip = <0x68b>; | |
| cooling-device = <0x2c 0x01 0x01>; | |
| }; | |
| soc_cpu6 { | |
| trip = <0x68b>; | |
| cooling-device = <0x2f 0x01 0x01>; | |
| }; | |
| soc_cpu4 { | |
| trip = <0x68b>; | |
| cooling-device = <0x29 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| cpu-1-6-usr { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x19 0x0d>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| active-config1 { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| pm8150b-ibat-lvl1 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x62e 0x01>; | |
| thermal-governor = "step_wise"; | |
| wake-capable-sensor; | |
| trips { | |
| ibat-lvl1 { | |
| temperature = <0x2710>; | |
| hysteresis = <0xc8>; | |
| type = "passive"; | |
| phandle = <0x6b6>; | |
| }; | |
| }; | |
| }; | |
| video-step { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x1a 0x02>; | |
| thermal-governor = "step_wise"; | |
| wake-capable-sensor; | |
| trips { | |
| video-trip0 { | |
| temperature = <0x186a0>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| phandle = <0x40>; | |
| }; | |
| }; | |
| cooling-maps { | |
| modem-tj-cdev { | |
| trip = <0x40>; | |
| cooling-device = <0x3e 0x03 0x03>; | |
| }; | |
| npu_cdev { | |
| trip = <0x40>; | |
| cooling-device = <0x3f 0xfffffffb 0xfffffffb>; | |
| }; | |
| modem-pa-cdev { | |
| trip = <0x40>; | |
| cooling-device = <0x3d 0x03 0x03>; | |
| }; | |
| cdsp-cdev { | |
| trip = <0x40>; | |
| cooling-device = <0x3c 0x03 0x03>; | |
| }; | |
| gpu-cdev { | |
| trip = <0x40>; | |
| cooling-device = <0x1c 0xfffffffd 0xfffffffd>; | |
| }; | |
| }; | |
| }; | |
| cpu-0-2-step { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x19 0x03>; | |
| thermal-governor = "step_wise"; | |
| wake-capable-sensor; | |
| trips { | |
| cpu02-config { | |
| temperature = <0x1adb0>; | |
| hysteresis = <0x2710>; | |
| type = "passive"; | |
| phandle = <0x22>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cpu02_cdev { | |
| trip = <0x22>; | |
| cooling-device = <0x23 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| pm8150b-bcl-lvl0 { | |
| polling-delay = <0x00>; | |
| disable-thermal-zone; | |
| polling-delay-passive = <0x64>; | |
| thermal-sensors = <0x62e 0x05>; | |
| thermal-governor = "step_wise"; | |
| wake-capable-sensor; | |
| trips { | |
| b-bcl-lvl0 { | |
| temperature = <0x01>; | |
| hysteresis = <0x01>; | |
| type = "passive"; | |
| phandle = <0x68c>; | |
| }; | |
| }; | |
| cooling-maps { | |
| vbat_cpu5 { | |
| trip = <0x68c>; | |
| cooling-device = <0x2c 0x01 0x01>; | |
| }; | |
| vbat_gpu0 { | |
| trip = <0x68c>; | |
| cooling-device = <0x1c 0x02 0x02>; | |
| }; | |
| vbat_cpu4 { | |
| trip = <0x68c>; | |
| cooling-device = <0x29 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| cpu-1-2-step { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x19 0x09>; | |
| thermal-governor = "step_wise"; | |
| wake-capable-sensor; | |
| trips { | |
| cpu12-config { | |
| temperature = <0x1adb0>; | |
| hysteresis = <0x2710>; | |
| type = "passive"; | |
| phandle = <0x2e>; | |
| }; | |
| cpufreq-12-config { | |
| temperature = <0x124f8>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| phandle = <0x2d>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cpu12_cdev { | |
| trip = <0x2e>; | |
| cooling-device = <0x2f 0x01 0x01>; | |
| }; | |
| cpufreq_cdev { | |
| trip = <0x2d>; | |
| cooling-device = <0x27 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| aoss0-usr { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x19 0x00>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| active-config1 { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| pm8150_tz { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x64>; | |
| thermal-sensors = <0x620>; | |
| thermal-governor = "step_wise"; | |
| phandle = <0x6a9>; | |
| wake-capable-sensor; | |
| trips { | |
| trip2 { | |
| temperature = <0x23668>; | |
| hysteresis = <0x00>; | |
| type = "passive"; | |
| }; | |
| trip0 { | |
| temperature = <0x17318>; | |
| hysteresis = <0x00>; | |
| type = "passive"; | |
| phandle = <0x6aa>; | |
| }; | |
| trip1 { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x00>; | |
| type = "passive"; | |
| phandle = <0x6ab>; | |
| }; | |
| }; | |
| }; | |
| pm8150l-bcl-lvl2 { | |
| polling-delay = <0x00>; | |
| disable-thermal-zone; | |
| polling-delay-passive = <0x64>; | |
| thermal-sensors = <0x634 0x07>; | |
| thermal-governor = "step_wise"; | |
| wake-capable-sensor; | |
| trips { | |
| l-bcl-lvl2 { | |
| temperature = <0x01>; | |
| hysteresis = <0x01>; | |
| type = "passive"; | |
| phandle = <0x691>; | |
| }; | |
| }; | |
| cooling-maps { | |
| vph_gpu2 { | |
| trip = <0x691>; | |
| cooling-device = <0x1c 0xfffffffe 0xfffffffe>; | |
| }; | |
| }; | |
| }; | |
| conn-therm-usr { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x6a0 0x4f>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| mmw-pa1-usr { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x6a1 0x4e>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| cpu-0-0-usr { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x19 0x01>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| active-config1 { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| cpu-0-1-step { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x19 0x02>; | |
| thermal-governor = "step_wise"; | |
| wake-capable-sensor; | |
| trips { | |
| cpu01-config { | |
| temperature = <0x1adb0>; | |
| hysteresis = <0x2710>; | |
| type = "passive"; | |
| phandle = <0x20>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cpu01_cdev { | |
| trip = <0x20>; | |
| cooling-device = <0x21 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| modem-mmw0-usr { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x46 0x6a>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| cpu-1-3-usr { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x19 0x0a>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| active-config1 { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| cpu-1-1-step { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x19 0x08>; | |
| thermal-governor = "step_wise"; | |
| wake-capable-sensor; | |
| trips { | |
| cpu11-config { | |
| temperature = <0x1adb0>; | |
| hysteresis = <0x2710>; | |
| type = "passive"; | |
| phandle = <0x2b>; | |
| }; | |
| cpufreq-11-config { | |
| temperature = <0x124f8>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| phandle = <0x2a>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cpu11_cdev { | |
| trip = <0x2b>; | |
| cooling-device = <0x2c 0x01 0x01>; | |
| }; | |
| cpufreq_cdev { | |
| trip = <0x2a>; | |
| cooling-device = <0x27 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| pm8150l_tz { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x64>; | |
| thermal-sensors = <0x633>; | |
| thermal-governor = "step_wise"; | |
| phandle = <0x6ce>; | |
| wake-capable-sensor; | |
| trips { | |
| trip2 { | |
| temperature = <0x23668>; | |
| hysteresis = <0x00>; | |
| type = "passive"; | |
| }; | |
| trip0 { | |
| temperature = <0x17318>; | |
| hysteresis = <0x00>; | |
| type = "passive"; | |
| }; | |
| trip1 { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x00>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| npu-step { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x1a 0x07>; | |
| thermal-governor = "step_wise"; | |
| wake-capable-sensor; | |
| trips { | |
| npu-trip0 { | |
| temperature = <0x186a0>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| phandle = <0x45>; | |
| }; | |
| }; | |
| cooling-maps { | |
| modem-tj-cdev { | |
| trip = <0x45>; | |
| cooling-device = <0x3e 0x03 0x03>; | |
| }; | |
| npu_cdev { | |
| trip = <0x45>; | |
| cooling-device = <0x3f 0xfffffffb 0xfffffffb>; | |
| }; | |
| modem-pa-cdev { | |
| trip = <0x45>; | |
| cooling-device = <0x3d 0x03 0x03>; | |
| }; | |
| cdsp-cdev { | |
| trip = <0x45>; | |
| cooling-device = <0x3c 0x03 0x03>; | |
| }; | |
| gpu-cdev { | |
| trip = <0x45>; | |
| cooling-device = <0x1c 0xfffffffd 0xfffffffd>; | |
| }; | |
| }; | |
| }; | |
| pm8150l-bcl-lvl0 { | |
| polling-delay = <0x00>; | |
| disable-thermal-zone; | |
| polling-delay-passive = <0x64>; | |
| thermal-sensors = <0x634 0x05>; | |
| thermal-governor = "step_wise"; | |
| wake-capable-sensor; | |
| trips { | |
| l-bcl-lvl0 { | |
| temperature = <0x01>; | |
| hysteresis = <0x01>; | |
| type = "passive"; | |
| phandle = <0x68f>; | |
| }; | |
| }; | |
| cooling-maps { | |
| vph_gpu0 { | |
| trip = <0x68f>; | |
| cooling-device = <0x1c 0x02 0x02>; | |
| }; | |
| vph_cpu4 { | |
| trip = <0x68f>; | |
| cooling-device = <0x29 0x01 0x01>; | |
| }; | |
| vph_cpu5 { | |
| trip = <0x68f>; | |
| cooling-device = <0x2c 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| skin-msm-therm-usr { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x6a2 0x4e>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| cpu-1-7-usr { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x19 0x0e>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| active-config1 { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| gpuss-0-usr { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x19 0x0f>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| active-config1 { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| cpu-1-7-step { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x19 0x0e>; | |
| thermal-governor = "step_wise"; | |
| wake-capable-sensor; | |
| trips { | |
| cpu17-config { | |
| temperature = <0x1adb0>; | |
| hysteresis = <0x2710>; | |
| type = "passive"; | |
| phandle = <0x3a>; | |
| }; | |
| cpufreq-17-config { | |
| temperature = <0x124f8>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| phandle = <0x39>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cpu17_cdev { | |
| trip = <0x3a>; | |
| cooling-device = <0x32 0x01 0x01>; | |
| }; | |
| cpufreq_cdev { | |
| trip = <0x39>; | |
| cooling-device = <0x27 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| modem-ambient-usr { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x46 0x7c>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| cpu-0-0-step { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x19 0x01>; | |
| thermal-governor = "step_wise"; | |
| wake-capable-sensor; | |
| trips { | |
| cpu00-config { | |
| temperature = <0x1adb0>; | |
| hysteresis = <0x2710>; | |
| type = "passive"; | |
| phandle = <0x1e>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cpu00_cdev { | |
| trip = <0x1e>; | |
| cooling-device = <0x1f 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| npu-usr { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x1a 0x07>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| active-config1 { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| pm8150b-vbat-lvl2 { | |
| polling-delay = <0x00>; | |
| tracks-low; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x62e 0x04>; | |
| thermal-governor = "low_limits_cap"; | |
| wake-capable-sensor; | |
| trips { | |
| vbat-lvl2 { | |
| temperature = <0xa28>; | |
| hysteresis = <0xc8>; | |
| type = "passive"; | |
| phandle = <0x6b9>; | |
| }; | |
| }; | |
| }; | |
| modem-wifi-usr { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x46 0x7b>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| modem-lte-sub6-pa2 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x46 0x65>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| cpu-1-0-step { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x19 0x07>; | |
| thermal-governor = "step_wise"; | |
| wake-capable-sensor; | |
| trips { | |
| cpu10-config { | |
| temperature = <0x1adb0>; | |
| hysteresis = <0x2710>; | |
| type = "passive"; | |
| phandle = <0x28>; | |
| }; | |
| cpufreq-10-config { | |
| temperature = <0x124f8>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| phandle = <0x26>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cpu10_cdev { | |
| trip = <0x28>; | |
| cooling-device = <0x29 0x01 0x01>; | |
| }; | |
| cpufreq_cdev { | |
| trip = <0x26>; | |
| cooling-device = <0x27 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| modem-mmw1-mod-usr { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x46 0x73>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| pm8150l-vph-lvl1 { | |
| polling-delay = <0x00>; | |
| tracks-low; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x634 0x03>; | |
| thermal-governor = "low_limits_cap"; | |
| wake-capable-sensor; | |
| trips { | |
| vph-lvl1 { | |
| temperature = <0xabe>; | |
| hysteresis = <0xc8>; | |
| type = "passive"; | |
| phandle = <0x6d0>; | |
| }; | |
| }; | |
| }; | |
| video-usr { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x1a 0x02>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| active-config1 { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| mmw-pa2-usr { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x6a2 0x4f>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| cpu-0-1-usr { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x19 0x02>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| active-config1 { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| modem-mmw1-usr { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x46 0x6b>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| xo-therm-usr { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x6a1 0x4c>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| pm8150b-vbat-lvl0 { | |
| polling-delay = <0x00>; | |
| tracks-low; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x62e 0x02>; | |
| thermal-governor = "low_limits_cap"; | |
| wake-capable-sensor; | |
| trips { | |
| vbat-lvl0 { | |
| temperature = <0xbb8>; | |
| hysteresis = <0xc8>; | |
| type = "passive"; | |
| phandle = <0x6b7>; | |
| }; | |
| }; | |
| }; | |
| cpu-1-0-usr { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x19 0x07>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| active-config1 { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| cpu-1-6-step { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x19 0x0d>; | |
| thermal-governor = "step_wise"; | |
| wake-capable-sensor; | |
| trips { | |
| cpu16-config { | |
| temperature = <0x1adb0>; | |
| hysteresis = <0x2710>; | |
| type = "passive"; | |
| phandle = <0x38>; | |
| }; | |
| cpufreq-16-config { | |
| temperature = <0x124f8>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| phandle = <0x37>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cpu16_cdev { | |
| trip = <0x38>; | |
| cooling-device = <0x2f 0x01 0x01>; | |
| }; | |
| cpufreq_cdev { | |
| trip = <0x37>; | |
| cooling-device = <0x27 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| cpu-1-4-usr { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x19 0x0b>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| active-config1 { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| ddr-usr { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x1a 0x03>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| active-config1 { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| camera-therm-usr { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x6a2 0x4d>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| pm8150b-bcl-lvl1 { | |
| polling-delay = <0x00>; | |
| disable-thermal-zone; | |
| polling-delay-passive = <0x64>; | |
| thermal-sensors = <0x62e 0x06>; | |
| thermal-governor = "step_wise"; | |
| wake-capable-sensor; | |
| trips { | |
| b-bcl-lvl1 { | |
| temperature = <0x01>; | |
| hysteresis = <0x01>; | |
| type = "passive"; | |
| phandle = <0x68d>; | |
| }; | |
| }; | |
| cooling-maps { | |
| vbat_cpu6 { | |
| trip = <0x68d>; | |
| cooling-device = <0x2f 0x01 0x01>; | |
| }; | |
| vbat_gpu1 { | |
| trip = <0x68d>; | |
| cooling-device = <0x1c 0x04 0x04>; | |
| }; | |
| vbat_cpu7 { | |
| trip = <0x68d>; | |
| cooling-device = <0x32 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| gpuss-max-step { | |
| polling-delay = <0x64>; | |
| polling-delay-passive = <0x0a>; | |
| thermal-governor = "step_wise"; | |
| wake-capable-sensor; | |
| trips { | |
| gpu-trip0 { | |
| temperature = <0x17318>; | |
| hysteresis = <0x00>; | |
| type = "passive"; | |
| phandle = <0x1b>; | |
| }; | |
| }; | |
| cooling-maps { | |
| gpu_cdev { | |
| trip = <0x1b>; | |
| cooling-device = <0x1c 0xffffffff 0xffffffff>; | |
| }; | |
| }; | |
| }; | |
| modem-skin-usr { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x46 0x6e>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| modem-mmw3-mod-usr { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x46 0x75>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| aoss-1-usr { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x1a 0x00>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| active-config1 { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| gpuss-1-usr { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x1a 0x08>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| active-config1 { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| pm8150b-ibat-lvl0 { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x62e 0x00>; | |
| thermal-governor = "step_wise"; | |
| wake-capable-sensor; | |
| trips { | |
| ibat-lvl0 { | |
| temperature = <0x1194>; | |
| hysteresis = <0xc8>; | |
| type = "passive"; | |
| phandle = <0x6b5>; | |
| }; | |
| }; | |
| }; | |
| modem-0-usr { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x46 0x69>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| cpu-1-5-step { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-sensors = <0x19 0x0c>; | |
| thermal-governor = "step_wise"; | |
| wake-capable-sensor; | |
| trips { | |
| cpu15-config { | |
| temperature = <0x1adb0>; | |
| hysteresis = <0x2710>; | |
| type = "passive"; | |
| phandle = <0x36>; | |
| }; | |
| cpufreq-15-config { | |
| temperature = <0x124f8>; | |
| hysteresis = <0x1388>; | |
| type = "passive"; | |
| phandle = <0x35>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cpufreq_cdev { | |
| trip = <0x35>; | |
| cooling-device = <0x27 0x01 0x01>; | |
| }; | |
| cpu15_cdev { | |
| trip = <0x36>; | |
| cooling-device = <0x2c 0x01 0x01>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| spi@988000 { | |
| pinctrl-names = "default\0sleep"; | |
| #address-cells = <0x01>; | |
| pinctrl-0 = <0x295>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| reg-names = "se_phys"; | |
| interrupts = <0x00 0x25b 0x04>; | |
| clocks = <0x16 0x5c 0x16 0x84 0x16 0x85>; | |
| #size-cells = <0x00>; | |
| qcom,wrapper-core = <0x274>; | |
| spi-max-frequency = <0x2faf080>; | |
| dma-names = "tx\0rx"; | |
| compatible = "qcom,spi-geni"; | |
| pinctrl-1 = <0x296>; | |
| status = "disabled"; | |
| reg = <0x988000 0x4000>; | |
| phandle = <0x5aa>; | |
| dmas = <0x280 0x00 0x02 0x01 0x40 0x00 0x280 0x01 0x02 0x01 0x40 0x00>; | |
| }; | |
| qcom,gdsc@17d058 { | |
| qcom,no-status-check-on-disable; | |
| qcom,gds-timeout = <0x1f4>; | |
| regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc"; | |
| compatible = "qcom,gdsc"; | |
| reg = <0x17d058 0x04>; | |
| phandle = <0x17e>; | |
| }; | |
| cti@6b40000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti-ssc_cortex_m3"; | |
| compatible = "arm,primecell"; | |
| status = "disabled"; | |
| reg = <0x6b40000 0x1000>; | |
| phandle = <0x53b>; | |
| }; | |
| qcom,cam-cpas@ac40000 { | |
| camnoc-bus-width = <0x20>; | |
| client-names = "csiphy0\0csiphy1\0csiphy2\0csiphy3\0csiphy4\0csiphy5\0cci0\0cci1\0csid0\0csid1\0csid2\0csid3\0csid4\0csid5\0csid6\0ife0\0ife1\0ife2\0ife3\0ife4\0ife5\0ife6\0custom0\0ipe0\0cam-cdm-intf0\0cpas-cdm0\0bps0\0icp0\0jpeg-dma0\0jpeg-enc0\0fd0"; | |
| vdd-corners = <0x10 0x30 0x40 0x80 0xc0 0x100 0x140 0x150 0x180 0x1a0>; | |
| clock-names = "gcc_ahb_clk\0gcc_axi_hf_clk\0gcc_axi_sf_clk\0slow_ahb_clk_src\0cpas_ahb_clk\0cpas_core_ahb_clk\0camnoc_axi_clk_src\0camnoc_axi_clk"; | |
| reg-names = "cam_cpas_top\0cam_camnoc"; | |
| qcom,msm-bus,name = "cam_ahb"; | |
| reg-cam-base = <0x40000 0x42000>; | |
| cell-index = <0x00>; | |
| vdd-corner-ahb-mapping = "suspend\0minsvs\0lowsvs\0svs\0svs_l1\0nominal\0nominal\0nominal\0turbo\0turbo"; | |
| control-camnoc-axi-clk; | |
| camss-vdd-supply = <0x253>; | |
| interrupts = <0x00 0x1cb 0x01>; | |
| clocks = <0x16 0x0b 0x16 0x0c 0x16 0x0d 0x6d 0x6d 0x6d 0x0d 0x6d 0x0c 0x6d 0x06 0x6d 0x05>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x08>; | |
| label = "cpas"; | |
| client-id-based; | |
| clock-cntl-level = "suspend\0minsvs\0lowsvs\0svs\0svs_l1\0nominal\0nominal_l1\0turbo"; | |
| compatible = "qcom,cam-cpas"; | |
| src-clock-name = "camnoc_axi_clk_src"; | |
| status = "ok"; | |
| camnoc-axi-clk-bw-margin-perc = <0x14>; | |
| interrupt-names = "cpas_camnoc"; | |
| reg = <0xac40000 0x1000 0xac42000 0x8000>; | |
| regulator-names = "camss-vdd"; | |
| qcom,msm-bus,vectors-KBps = <0x01 0x24d 0x00 0x00 0x01 0x24d 0x00 0x12c00 0x01 0x24d 0x00 0x12c00 0x01 0x24d 0x00 0x249f0 0x01 0x24d 0x00 0x249f0 0x01 0x24d 0x00 0x493e0 0x01 0x24d 0x00 0x493e0 0x01 0x24d 0x00 0x493e0>; | |
| clock-rates = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x124f800 0x00 0x00 0x124f800 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x11e1a300 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x1c9c3800 0x00>; | |
| arch-compat = "cpas_top"; | |
| camnoc-axi-min-ib-bw = <0xb2d05e00>; | |
| camera-bus-nodes { | |
| level1-nodes { | |
| level-index = <0x01>; | |
| camnoc-max-needed; | |
| level1-nrt0-wr0 { | |
| parent-node = <0x262>; | |
| cell-index = <0x0c>; | |
| node-name = "level1-nrt0-wr0"; | |
| traffic-merge-type = <0x00>; | |
| phandle = <0x268>; | |
| }; | |
| level1-rt0-wr2 { | |
| parent-node = <0x260>; | |
| cell-index = <0x0b>; | |
| node-name = "level1-rt0-wr2"; | |
| traffic-merge-type = <0x00>; | |
| phandle = <0x267>; | |
| }; | |
| level1-rt0-wr0 { | |
| parent-node = <0x260>; | |
| cell-index = <0x08>; | |
| node-name = "level1-rt0-wr0"; | |
| traffic-merge-type = <0x00>; | |
| phandle = <0x264>; | |
| }; | |
| level1-nrt0-rd2 { | |
| parent-node = <0x263>; | |
| cell-index = <0x0f>; | |
| node-name = "level1-nrt0-rd2"; | |
| traffic-merge-type = <0x00>; | |
| phandle = <0x26b>; | |
| }; | |
| level1-nrt0-wr1 { | |
| parent-node = <0x262>; | |
| cell-index = <0x0e>; | |
| node-name = "level1-nrt0-wr1"; | |
| traffic-merge-type = <0x00>; | |
| phandle = <0x26a>; | |
| }; | |
| level1-nrt0-rd0 { | |
| parent-node = <0x263>; | |
| cell-index = <0x0d>; | |
| node-name = "level1-nrt0-rd0"; | |
| traffic-merge-type = <0x00>; | |
| phandle = <0x269>; | |
| }; | |
| level1-rt0-wr1 { | |
| parent-node = <0x260>; | |
| cell-index = <0x09>; | |
| node-name = "level1-rt0-wr1"; | |
| traffic-merge-type = <0x00>; | |
| phandle = <0x265>; | |
| }; | |
| level1-rt0-rd0 { | |
| parent-node = <0x261>; | |
| cell-index = <0x0a>; | |
| node-name = "level1-rt0-rd0"; | |
| traffic-merge-type = <0x00>; | |
| phandle = <0x266>; | |
| }; | |
| }; | |
| level2-nodes { | |
| level-index = <0x02>; | |
| camnoc-max-needed; | |
| level2-nrt0-wr { | |
| parent-node = <0x25e>; | |
| cell-index = <0x05>; | |
| node-name = "level2-nrt0-wr"; | |
| traffic-merge-type = <0x01>; | |
| phandle = <0x262>; | |
| }; | |
| level2-rt0-wr { | |
| parent-node = <0x25d>; | |
| cell-index = <0x03>; | |
| node-name = "level2-rt0-wr"; | |
| traffic-merge-type = <0x01>; | |
| phandle = <0x260>; | |
| }; | |
| level2-nrt1-rd { | |
| bus-width-factor = <0x04>; | |
| parent-node = <0x25f>; | |
| cell-index = <0x07>; | |
| node-name = "level2-nrt1-rd"; | |
| traffic-merge-type = <0x00>; | |
| phandle = <0x26c>; | |
| }; | |
| level2-nrt0-rd { | |
| parent-node = <0x25e>; | |
| cell-index = <0x06>; | |
| node-name = "level2-nrt0-rd"; | |
| traffic-merge-type = <0x01>; | |
| phandle = <0x263>; | |
| }; | |
| level2-rt0-rd { | |
| parent-node = <0x25d>; | |
| cell-index = <0x04>; | |
| node-name = "level2-rt0-rd"; | |
| traffic-merge-type = <0x01>; | |
| phandle = <0x261>; | |
| }; | |
| }; | |
| level3-nodes { | |
| level-index = <0x03>; | |
| level3-nrt1-rd-wr-sum { | |
| cell-index = <0x02>; | |
| node-name = "level3-nrt1-rd-wr-sum"; | |
| traffic-merge-type = <0x00>; | |
| qcom,axi-port-name = "cam_sf_icp"; | |
| phandle = <0x25f>; | |
| qcom,axi-port-mnoc { | |
| qcom,msm-bus,name = "cam_sf_icp_mnoc"; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| qcom,msm-bus,vectors-KBps = <0xab 0x200 0x00 0x00 0xab 0x200 0x00 0x00>; | |
| qcom,msm-bus-vector-dyn-vote; | |
| }; | |
| }; | |
| level3-nrt0-rd-wr-sum { | |
| cell-index = <0x01>; | |
| node-name = "level3-nrt0-rd-wr-sum"; | |
| traffic-merge-type = <0x00>; | |
| qcom,axi-port-name = "cam_sf_0"; | |
| phandle = <0x25e>; | |
| qcom,axi-port-mnoc { | |
| qcom,msm-bus,name = "cam_sf_0_mnoc"; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| qcom,msm-bus,vectors-KBps = <0x89 0x200 0x00 0x00 0x89 0x200 0x00 0x00>; | |
| qcom,msm-bus-vector-dyn-vote; | |
| }; | |
| }; | |
| level3-rt0-rd-wr-sum { | |
| ib-bw-voting-needed; | |
| cell-index = <0x00>; | |
| node-name = "level3-rt0-rd-wr-sum"; | |
| traffic-merge-type = <0x00>; | |
| qcom,axi-port-name = "cam_hf_0"; | |
| phandle = <0x25d>; | |
| qcom,axi-port-mnoc { | |
| qcom,msm-bus,name = "cam_hf_0_mnoc"; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| qcom,msm-bus,vectors-KBps = <0xaa 0x200 0x00 0x00 0xaa 0x200 0x00 0x00>; | |
| qcom,msm-bus-vector-dyn-vote; | |
| }; | |
| }; | |
| }; | |
| level0-nodes { | |
| level-index = <0x00>; | |
| icp0-all-rd { | |
| parent-node = <0x26c>; | |
| cell-index = <0x2b>; | |
| node-name = "icp0-all-rd"; | |
| traffic-data = <0x100>; | |
| phandle = <0x58d>; | |
| traffic-transaction-type = <0x00>; | |
| client-name = "icp0"; | |
| }; | |
| ife5-rdi-all-wr { | |
| parent-node = <0x265>; | |
| cell-index = <0x17>; | |
| node-name = "ife5-rdi-all-wr"; | |
| constituent-paths = <0x04 0x05 0x06 0x07>; | |
| traffic-data = <0x105>; | |
| phandle = <0x579>; | |
| traffic-transaction-type = <0x01>; | |
| client-name = "ife5"; | |
| }; | |
| ife0-ubwc-stats-wr { | |
| parent-node = <0x264>; | |
| cell-index = <0x10>; | |
| node-name = "ife0-ubwc-stats-wr"; | |
| constituent-paths = <0x01 0x02 0x03>; | |
| traffic-data = <0x102>; | |
| phandle = <0x572>; | |
| traffic-transaction-type = <0x01>; | |
| client-name = "ife0"; | |
| }; | |
| jpeg-enc0-all-wr { | |
| parent-node = <0x26a>; | |
| cell-index = <0x24>; | |
| node-name = "jpeg-enc0-all-wr"; | |
| traffic-data = <0x100>; | |
| phandle = <0x586>; | |
| traffic-transaction-type = <0x01>; | |
| client-name = "jpeg-enc0"; | |
| }; | |
| custom0-all-wr { | |
| parent-node = <0x267>; | |
| cell-index = <0x1e>; | |
| node-name = "custom0-all-wr"; | |
| traffic-data = <0x100>; | |
| phandle = <0x580>; | |
| traffic-transaction-type = <0x01>; | |
| client-name = "custom0"; | |
| }; | |
| ife3-rdi-all-wr { | |
| parent-node = <0x265>; | |
| cell-index = <0x15>; | |
| node-name = "ife3-rdi-all-wr"; | |
| constituent-paths = <0x04 0x05 0x06 0x07>; | |
| traffic-data = <0x105>; | |
| phandle = <0x577>; | |
| traffic-transaction-type = <0x01>; | |
| client-name = "ife3"; | |
| }; | |
| fd0-all-wr { | |
| parent-node = <0x262>; | |
| cell-index = <0x28>; | |
| node-name = "fd0-all-wr"; | |
| traffic-data = <0x100>; | |
| phandle = <0x58a>; | |
| traffic-transaction-type = <0x01>; | |
| client-name = "fd0"; | |
| }; | |
| bps0-all-wr { | |
| parent-node = <0x268>; | |
| cell-index = <0x20>; | |
| node-name = "bps0-all-wr"; | |
| traffic-data = <0x100>; | |
| phandle = <0x582>; | |
| traffic-transaction-type = <0x01>; | |
| client-name = "bps0"; | |
| }; | |
| ife0-rdi-pixel-raw-wr { | |
| parent-node = <0x267>; | |
| cell-index = <0x1b>; | |
| node-name = "ife0-rdi-pixel-raw-wr"; | |
| constituent-paths = <0x04 0x05 0x06 0x09>; | |
| traffic-data = <0x104>; | |
| phandle = <0x57d>; | |
| traffic-transaction-type = <0x01>; | |
| client-name = "ife0"; | |
| }; | |
| jpeg-dma0-all-wr { | |
| parent-node = <0x26a>; | |
| cell-index = <0x25>; | |
| node-name = "jpeg-dma0-all-wr"; | |
| traffic-data = <0x100>; | |
| phandle = <0x587>; | |
| traffic-transaction-type = <0x01>; | |
| client-name = "jpeg-dma0"; | |
| }; | |
| ife0-rdi-all-rd { | |
| parent-node = <0x266>; | |
| cell-index = <0x18>; | |
| node-name = "ife0-rdi-all-rd"; | |
| constituent-paths = <0x04 0x05 0x06 0x07>; | |
| traffic-data = <0x105>; | |
| phandle = <0x57a>; | |
| traffic-transaction-type = <0x00>; | |
| client-name = "ife0"; | |
| }; | |
| ife6-rdi-all-wr { | |
| parent-node = <0x267>; | |
| cell-index = <0x1d>; | |
| node-name = "ife6-rdi-all-wr"; | |
| constituent-paths = <0x04 0x05 0x06 0x07>; | |
| traffic-data = <0x105>; | |
| phandle = <0x57f>; | |
| traffic-transaction-type = <0x01>; | |
| client-name = "ife6"; | |
| }; | |
| ife1-ubwc-stats-wr { | |
| parent-node = <0x264>; | |
| cell-index = <0x11>; | |
| node-name = "ife1-ubwc-stats-wr"; | |
| constituent-paths = <0x01 0x02 0x03>; | |
| traffic-data = <0x102>; | |
| phandle = <0x573>; | |
| traffic-transaction-type = <0x01>; | |
| client-name = "ife1"; | |
| }; | |
| ife1-linear-pdaf-wr { | |
| parent-node = <0x265>; | |
| cell-index = <0x13>; | |
| node-name = "ife1-linear-pdaf-wr"; | |
| constituent-paths = <0x00 0x08>; | |
| traffic-data = <0x101>; | |
| phandle = <0x575>; | |
| traffic-transaction-type = <0x01>; | |
| client-name = "ife1"; | |
| }; | |
| jpeg-enc0-all-rd { | |
| parent-node = <0x26b>; | |
| cell-index = <0x26>; | |
| node-name = "jpeg-enc0-all-rd"; | |
| traffic-data = <0x100>; | |
| phandle = <0x588>; | |
| traffic-transaction-type = <0x00>; | |
| client-name = "jpeg-enc0"; | |
| }; | |
| custom0-all-rd { | |
| parent-node = <0x266>; | |
| cell-index = <0x1a>; | |
| node-name = "custom0-all-rd"; | |
| traffic-data = <0x100>; | |
| phandle = <0x57c>; | |
| traffic-transaction-type = <0x00>; | |
| client-name = "custom0"; | |
| }; | |
| ipe0-all-wr { | |
| parent-node = <0x268>; | |
| cell-index = <0x1f>; | |
| node-name = "ipe0-all-wr"; | |
| constituent-paths = <0x22 0x23 0x24>; | |
| traffic-data = <0x100>; | |
| phandle = <0x581>; | |
| traffic-transaction-type = <0x01>; | |
| client-name = "ipe0"; | |
| }; | |
| ipe0-in-rd { | |
| parent-node = <0x263>; | |
| cell-index = <0x23>; | |
| node-name = "ipe0-in-rd"; | |
| traffic-data = <0x20>; | |
| phandle = <0x585>; | |
| traffic-transaction-type = <0x00>; | |
| client-name = "ipe0"; | |
| }; | |
| ife4-rdi-all-wr { | |
| parent-node = <0x265>; | |
| cell-index = <0x16>; | |
| node-name = "ife4-rdi-all-wr"; | |
| constituent-paths = <0x04 0x05 0x06 0x07>; | |
| traffic-data = <0x105>; | |
| phandle = <0x578>; | |
| traffic-transaction-type = <0x01>; | |
| client-name = "ife4"; | |
| }; | |
| fd0-all-rd { | |
| parent-node = <0x263>; | |
| cell-index = <0x29>; | |
| node-name = "fd0-all-rd"; | |
| traffic-data = <0x100>; | |
| phandle = <0x58b>; | |
| traffic-transaction-type = <0x00>; | |
| client-name = "fd0"; | |
| }; | |
| bps0-all-rd { | |
| parent-node = <0x269>; | |
| cell-index = <0x22>; | |
| node-name = "bps0-all-rd"; | |
| traffic-data = <0x100>; | |
| phandle = <0x584>; | |
| traffic-transaction-type = <0x00>; | |
| client-name = "bps0"; | |
| }; | |
| ife0-linear-pdaf-wr { | |
| parent-node = <0x265>; | |
| cell-index = <0x12>; | |
| node-name = "ife0-linear-pdaf-wr"; | |
| constituent-paths = <0x00 0x08>; | |
| traffic-data = <0x101>; | |
| phandle = <0x574>; | |
| traffic-transaction-type = <0x01>; | |
| client-name = "ife0"; | |
| }; | |
| ipe0-ref-rd { | |
| parent-node = <0x269>; | |
| cell-index = <0x21>; | |
| node-name = "ipe0-ref-rd"; | |
| traffic-data = <0x21>; | |
| phandle = <0x583>; | |
| traffic-transaction-type = <0x00>; | |
| client-name = "ipe0"; | |
| }; | |
| jpeg-dma0-all-rd { | |
| parent-node = <0x26b>; | |
| cell-index = <0x27>; | |
| node-name = "jpeg-dma0-all-rd"; | |
| traffic-data = <0x100>; | |
| phandle = <0x589>; | |
| traffic-transaction-type = <0x00>; | |
| client-name = "jpeg-dma0"; | |
| }; | |
| ife1-rdi-pixel-raw-wr { | |
| parent-node = <0x267>; | |
| cell-index = <0x1c>; | |
| node-name = "ife1-rdi-pixel-raw-wr"; | |
| constituent-paths = <0x04 0x05 0x06 0x09>; | |
| traffic-data = <0x104>; | |
| phandle = <0x57e>; | |
| traffic-transaction-type = <0x01>; | |
| client-name = "ife1"; | |
| }; | |
| ife1-rdi-all-rd { | |
| parent-node = <0x266>; | |
| cell-index = <0x19>; | |
| node-name = "ife1-rdi-all-rd"; | |
| constituent-paths = <0x04 0x05 0x06 0x07>; | |
| traffic-data = <0x105>; | |
| phandle = <0x57b>; | |
| traffic-transaction-type = <0x00>; | |
| client-name = "ife1"; | |
| }; | |
| ife2-rdi-all-wr { | |
| parent-node = <0x265>; | |
| cell-index = <0x14>; | |
| node-name = "ife2-rdi-all-wr"; | |
| constituent-paths = <0x04 0x05 0x06 0x07>; | |
| traffic-data = <0x105>; | |
| phandle = <0x576>; | |
| traffic-transaction-type = <0x01>; | |
| client-name = "ife2"; | |
| }; | |
| cpas-cdm0-all-rd { | |
| parent-node = <0x263>; | |
| cell-index = <0x2a>; | |
| node-name = "cpas-cdm0-all-rd"; | |
| traffic-data = <0x100>; | |
| phandle = <0x58c>; | |
| traffic-transaction-type = <0x00>; | |
| client-name = "cpas-cdm0"; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,venus@aab0000 { | |
| qcom,ahb-freq = <0xbebc200>; | |
| clock-names = "xo\0core\0ahb"; | |
| qcom,msm-bus,name = "pil-venus"; | |
| qcom,proxy-timeout-ms = <0x64>; | |
| memory-region = <0x9a>; | |
| clocks = <0x6b 0x0f 0x6b 0x05 0x6b 0x00>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| qcom,core-freq = <0xbebc200>; | |
| qcom,complete-ramdump; | |
| qcom,pas-id = <0x09>; | |
| vdd-supply = <0x99>; | |
| compatible = "qcom,pil-tz-generic"; | |
| reg = <0xaab0000 0x2000>; | |
| qcom,msm-bus,vectors-KBps = <0x3f 0x200 0x00 0x00 0x3f 0x200 0x00 0x4a380>; | |
| qcom,proxy-clock-names = "xo\0core\0ahb"; | |
| qcom,proxy-reg-names = "vdd"; | |
| qcom,firmware-name = "venus"; | |
| }; | |
| etm@7440000 { | |
| arm,primecell-periphid = <0xbb95d>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x49 0x00>; | |
| cpu = <0x11>; | |
| qcom,tupwr-disable; | |
| coresight-name = "coresight-etm4"; | |
| compatible = "arm,primecell"; | |
| reg = <0x7440000 0x1000>; | |
| phandle = <0x54b>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x23f>; | |
| phandle = <0x248>; | |
| }; | |
| }; | |
| }; | |
| qcom,cci@ac4f000 { | |
| pinctrl-names = "cam_default\0cam_suspend"; | |
| pinctrl-0 = <0x254 0x255>; | |
| clock-names = "cci_0_clk_src\0cci_0_clk"; | |
| reg-names = "cci"; | |
| reg-cam-base = <0x4f000>; | |
| cell-index = <0x00>; | |
| gpio-req-tbl-num = <0x00 0x01 0x02 0x03>; | |
| interrupts = <0x00 0x1cc 0x01>; | |
| clocks = <0x6d 0x09 0x6d 0x08>; | |
| gdscr-supply = <0x253>; | |
| gpio-req-tbl-label = "CCI_I2C_DATA0\0CCI_I2C_CLK0\0CCI_I2C_DATA1\0CCI_I2C_CLK1"; | |
| clock-cntl-level = "lowsvs"; | |
| compatible = "qcom,cci"; | |
| src-clock-name = "cci_0_clk_src"; | |
| pinctrl-1 = <0x256 0x257>; | |
| status = "ok"; | |
| interrupt-names = "cci"; | |
| reg = <0xac4f000 0x1000>; | |
| regulator-names = "gdscr"; | |
| phandle = <0x563>; | |
| clock-rates = <0x23c3460 0x00>; | |
| gpio-req-tbl-flags = <0x01 0x01 0x01 0x01>; | |
| gpios = <0x66 0x65 0x00 0x66 0x66 0x00 0x66 0x67 0x00 0x66 0x68 0x00>; | |
| qcom,eeprom3 { | |
| rgltr-max-voltage = <0x1b7740 0x2ab980 0x13e5c0 0x00>; | |
| pinctrl-names = "cam_default\0cam_suspend"; | |
| pinctrl-0 = <0x46b 0x499>; | |
| clock-names = "cam_clk"; | |
| cell-index = <0x03>; | |
| gpio-req-tbl-num = <0x00 0x01>; | |
| clocks = <0x6d 0x4b>; | |
| rgltr-load-current = <0x00 0x13880 0x19a28 0x00>; | |
| cam_vio-supply = <0x393>; | |
| rgltr-cntrl-support; | |
| cam_vana-supply = <0x391>; | |
| gpio-req-tbl-label = "CAMIF_MCLK1\0CAM_RESET1"; | |
| cam_vaf-supply = <0x389>; | |
| gpio-reset = <0x01>; | |
| clock-cntl-level = "turbo"; | |
| cam_vdig-supply = <0x390>; | |
| sensor-mode = <0x00>; | |
| cci-master = <0x01>; | |
| gpio-no-mux = <0x00>; | |
| compatible = "qcom,eeprom"; | |
| rgltr-min-voltage = <0x1b7740 0x2ab980 0x124f80 0x00>; | |
| pinctrl-1 = <0x46c 0x49a>; | |
| status = "ok"; | |
| sensor-position = <0x01>; | |
| regulator-names = "cam_vio\0cam_vana\0cam_vdig\0cam_clk"; | |
| phandle = <0x64e>; | |
| cam_clk-supply = <0x253>; | |
| clock-rates = <0x16e3600>; | |
| gpio-req-tbl-flags = <0x01 0x00>; | |
| gpios = <0x66 0x5f 0x00 0x66 0x5c 0x00>; | |
| }; | |
| qcom,i2c_custom_mode { | |
| hw-tsu-sto = <0x28>; | |
| cci-clk-src = <0x23c3460>; | |
| hw-tsp = <0x03>; | |
| hw-trdhld = <0x06>; | |
| hw-thigh = <0x26>; | |
| hw-tlow = <0x38>; | |
| status = "ok"; | |
| hw-thd-dat = <0x16>; | |
| hw-tsu-sta = <0x28>; | |
| hw-scl-stretch-en = <0x01>; | |
| phandle = <0x566>; | |
| hw-tbuf = <0x3e>; | |
| hw-thd-sta = <0x23>; | |
| }; | |
| qcom,i2c_standard_mode { | |
| hw-tsu-sto = <0xcc>; | |
| cci-clk-src = <0x23c3460>; | |
| hw-tsp = <0x03>; | |
| hw-trdhld = <0x06>; | |
| hw-thigh = <0xc9>; | |
| hw-tlow = <0xae>; | |
| status = "ok"; | |
| hw-thd-dat = <0x16>; | |
| hw-tsu-sta = <0xe7>; | |
| hw-scl-stretch-en = <0x00>; | |
| phandle = <0x564>; | |
| hw-tbuf = <0xe3>; | |
| hw-thd-sta = <0xa2>; | |
| }; | |
| qcom,cam-sensor0 { | |
| rgltr-max-voltage = <0x1b7740 0x2ab980 0x124f80 0x00 0x2f5d00>; | |
| pinctrl-names = "cam_default\0cam_suspend"; | |
| eeprom-src = <0x64d>; | |
| pwm-switch; | |
| pinctrl-0 = <0x469 0x477>; | |
| clock-names = "cam_clk"; | |
| cell-index = <0x00>; | |
| gpio-req-tbl-num = <0x00 0x01>; | |
| sensor-position-yaw = <0xb4>; | |
| clocks = <0x6d 0x49>; | |
| rgltr-load-current = <0x00 0x13880 0x19a28 0x00 0x186a0>; | |
| actuator-src = <0x64b>; | |
| cam_vio-supply = <0x393>; | |
| rgltr-cntrl-support; | |
| cam_vana-supply = <0x391>; | |
| gpio-req-tbl-label = "CAMIF_MCLK0\0CAM_RESET0"; | |
| cam_vaf-supply = <0x389>; | |
| gpio-reset = <0x01>; | |
| csiphy-sd-index = <0x00>; | |
| clock-cntl-level = "turbo"; | |
| cam_vdig-supply = <0x38d>; | |
| sensor-mode = <0x00>; | |
| cci-master = <0x00>; | |
| gpio-no-mux = <0x00>; | |
| compatible = "qcom,cam-sensor"; | |
| rgltr-min-voltage = <0x1b7740 0x2ab980 0x124f80 0x00 0x2b9440>; | |
| led-flash-src = <0x64c>; | |
| sensor-position-roll = <0x5a>; | |
| pinctrl-1 = <0x46a 0x478>; | |
| status = "ok"; | |
| reg = <0x00>; | |
| regulator-names = "cam_vio\0cam_vana\0cam_vdig\0cam_clk\0cam_vaf"; | |
| sensor-position-pitch = <0x00>; | |
| cam_clk-supply = <0x253>; | |
| clock-rates = <0x16e3600>; | |
| gpio-req-tbl-flags = <0x01 0x00>; | |
| gpios = <0x66 0x5e 0x00 0x66 0x5d 0x00>; | |
| }; | |
| qcom,actuator0 { | |
| rgltr-max-voltage = "\0/]"; | |
| cell-index = <0x00>; | |
| rgltr-load-current = <0x186a0>; | |
| rgltr-cntrl-support; | |
| cam_vaf-supply = <0x389>; | |
| cci-master = <0x00>; | |
| compatible = "qcom,actuator"; | |
| rgltr-min-voltage = <0x2b9440>; | |
| regulator-names = "cam_vaf"; | |
| phandle = <0x64b>; | |
| }; | |
| qcom,eeprom0 { | |
| rgltr-max-voltage = <0x1b7740 0x2ab980 0x124f80 0x00 0x2f5d00>; | |
| pinctrl-names = "cam_default\0cam_suspend"; | |
| pinctrl-0 = <0x469 0x477>; | |
| clock-names = "cam_clk"; | |
| cell-index = <0x00>; | |
| gpio-req-tbl-num = <0x00 0x01>; | |
| clocks = <0x6d 0x49>; | |
| rgltr-load-current = <0x00 0x13880 0x19a28 0x00 0x186a0>; | |
| cam_vio-supply = <0x393>; | |
| rgltr-cntrl-support; | |
| cam_vana-supply = <0x391>; | |
| gpio-req-tbl-label = "CAMIF_MCLK0\0CAM_RESET0"; | |
| cam_vaf-supply = <0x389>; | |
| gpio-reset = <0x01>; | |
| clock-cntl-level = "turbo"; | |
| cam_vdig-supply = <0x38d>; | |
| sensor-mode = <0x00>; | |
| cci-master = <0x00>; | |
| gpio-no-mux = <0x00>; | |
| compatible = "qcom,eeprom"; | |
| rgltr-min-voltage = <0x1b7740 0x2ab980 0x124f80 0x00 0x2b9440>; | |
| pinctrl-1 = <0x46a 0x478>; | |
| status = "ok"; | |
| sensor-position = <0x00>; | |
| regulator-names = "cam_vio\0cam_vana\0cam_vdig\0cam_clk\0cam_vaf"; | |
| phandle = <0x64d>; | |
| cam_clk-supply = <0x253>; | |
| clock-rates = <0x16e3600>; | |
| gpio-req-tbl-flags = <0x01 0x00>; | |
| gpios = <0x66 0x5e 0x00 0x66 0x5d 0x00>; | |
| }; | |
| qcom,cam-sensor3 { | |
| rgltr-max-voltage = <0x1b7740 0x2dc6c0 0x13e5c0 0x00>; | |
| pinctrl-names = "cam_default\0cam_suspend"; | |
| eeprom-src = <0x64e>; | |
| pwm-switch; | |
| pinctrl-0 = <0x46b 0x499>; | |
| clock-names = "cam_clk"; | |
| cell-index = <0x03>; | |
| gpio-req-tbl-num = <0x00 0x01>; | |
| sensor-position-yaw = <0x00>; | |
| clocks = <0x6d 0x4b>; | |
| rgltr-load-current = <0x00 0x13880 0x19a28 0x00>; | |
| cam_vio-supply = <0x393>; | |
| rgltr-cntrl-support; | |
| cam_vana-supply = <0x391>; | |
| gpio-req-tbl-label = "CAMIF_MCLK1\0CAM_RESET1"; | |
| gpio-reset = <0x01>; | |
| csiphy-sd-index = <0x01>; | |
| clock-cntl-level = "turbo"; | |
| cam_vdig-supply = <0x390>; | |
| sensor-mode = <0x00>; | |
| cci-master = <0x01>; | |
| gpio-no-mux = <0x00>; | |
| compatible = "qcom,cam-sensor"; | |
| rgltr-min-voltage = <0x1b7740 0x2ab980 0x124f80 0x00>; | |
| sensor-position-roll = <0x10e>; | |
| pinctrl-1 = <0x46c 0x49a>; | |
| status = "ok"; | |
| reg = <0x02>; | |
| regulator-names = "cam_vio\0cam_vana\0cam_vdig\0cam_clk"; | |
| sensor-position-pitch = <0x00>; | |
| cam_clk-supply = <0x253>; | |
| clock-rates = <0x16e3600>; | |
| gpio-req-tbl-flags = <0x01 0x00>; | |
| gpios = <0x66 0x5f 0x00 0x66 0x5c 0x00>; | |
| }; | |
| qcom,i2c_fast_plus_mode { | |
| hw-tsu-sto = <0x11>; | |
| cci-clk-src = <0x23c3460>; | |
| hw-tsp = <0x03>; | |
| hw-trdhld = <0x03>; | |
| hw-thigh = <0x10>; | |
| hw-tlow = <0x16>; | |
| status = "ok"; | |
| hw-thd-dat = <0x10>; | |
| hw-tsu-sta = <0x12>; | |
| hw-scl-stretch-en = <0x00>; | |
| phandle = <0x567>; | |
| hw-tbuf = <0x18>; | |
| hw-thd-sta = <0x0f>; | |
| }; | |
| qcom,i2c_fast_mode { | |
| hw-tsu-sto = <0x28>; | |
| cci-clk-src = <0x23c3460>; | |
| hw-tsp = <0x03>; | |
| hw-trdhld = <0x06>; | |
| hw-thigh = <0x26>; | |
| hw-tlow = <0x38>; | |
| status = "ok"; | |
| hw-thd-dat = <0x16>; | |
| hw-tsu-sta = <0x28>; | |
| hw-scl-stretch-en = <0x00>; | |
| phandle = <0x565>; | |
| hw-tbuf = <0x3e>; | |
| hw-thd-sta = <0x23>; | |
| }; | |
| }; | |
| qcom,mdss_mdp@ae00000 { | |
| qcom,sde-safe-lut-macrotile-qseed = <0x00 0xff00>; | |
| qcom,sde-dither-off = <0x30e0 0x30e0 0x30e0 0x30e0 0x30e0 0x30e0>; | |
| qcom,sde-qseed-type = "qseedv3lite"; | |
| qcom,sde-max-per-pipe-bw-kbps = <0x432380 0x432380 0x432380 0x432380 0x432380 0x432380 0x432380 0x432380>; | |
| qcom,sde-smart-dma-rev = "smart_dma_v2p5"; | |
| qcom,sde-qos-cpu-irq-latency = <0x12c>; | |
| qcom,sde-mixer-cwb-pref = "none\0none\0cwb\0cwb\0cwb\0cwb"; | |
| qcom,sde-vbif-off = <0x00>; | |
| qcom,sde-panic-per-pipe; | |
| qcom,sde-danger-lut = <0xff 0xffff 0x00 0x00 0xffff>; | |
| qcom,sde-te2-off = <0x2000 0x2000 0x00 0x00 0x00 0x00>; | |
| qcom,sde-sspp-smart-dma-priority = <0x05 0x06 0x07 0x08 0x01 0x02 0x03 0x04>; | |
| qcom,sde-sspp-qseed-off = <0xa00>; | |
| qcom,sde-ctl-display-pref = "primary\0none\0none\0none\0none"; | |
| qcom,sde-ubwc-swizzle = <0x06>; | |
| qcom,sde-dspp-size = <0x1800>; | |
| qcom,sde-sspp-src-size = <0x1f8>; | |
| clock-max-rate = <0x00 0x00 0x00 0x00 0x1b6b0b00 0x124f800 0x1b6b0b00 0x1b6b0b00>; | |
| qcom,sde-sspp-excl-rect = <0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01>; | |
| qcom,sde-wb-id = <0x02>; | |
| qcom,sde-ubwc-bw-calc-version = <0x01>; | |
| qcom,sde-safe-lut-macrotile = <0x00 0xff00>; | |
| qcom,sde-wb-size = <0x2c8>; | |
| qcom,sde-qos-lut-nrt = <0x00 0x00 0x00>; | |
| connectors = <0x552 0x643 0x644 0x645 0x553>; | |
| qcom,sde-dsc-pair-mask = <0x02 0x01 0x04 0x03>; | |
| qcom,sde-macrotile-mode = <0x01>; | |
| qcom,sde-safe-lut-cwb = <0x00 0x3ff>; | |
| qcom,sde-pp-size = <0xd4>; | |
| qcom,sde-dest-scaler-top-off = <0x61000>; | |
| clock-names = "gcc_iface\0gcc_bus\0gcc_nrt_bus\0iface_clk\0core_clk\0vsync_clk\0lut_clk\0rot_clk"; | |
| reg-names = "mdp_phys\0vbif_phys\0regdma_phys\0sid_phys\0swfuse_phys"; | |
| qcom,sde-qos-lut-macrotile-qseed = <0x00 0x112233 0x66777777>; | |
| qcom,sde-sspp-off = <0x5000 0x7000 0x9000 0xb000 0x25000 0x27000 0x29000 0x2b000>; | |
| qcom,sde-max-dest-scaler-output-linewidth = <0xa00>; | |
| qcom,sde-qos-cpu-mask = <0x03>; | |
| qcom,sde-ctl-off = <0x2000 0x2200 0x2400 0x2600 0x2800 0x2a00>; | |
| qcom,sde-smart-panel-align-mode = <0x0c>; | |
| qcom,sde-dest-scaler-size = <0x800>; | |
| qcom,sde-vbif-qos-nrt-remap = <0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03>; | |
| qcom,sde-cdp-setting = <0x01 0x01 0x01 0x00>; | |
| qcom,sde-reg-dma-trigger-off = <0x119c>; | |
| qcom,sde-dram-channels = <0x02>; | |
| qcom,sde-ctl-size = <0x1dc>; | |
| qcom,sde-csc-type = "csc-10bit"; | |
| interrupts = <0x00 0x53 0x04>; | |
| clocks = <0x16 0x18 0x16 0x19 0x16 0x1a 0x6c 0x00 0x6c 0x2a 0x6c 0x36 0x6c 0x2c 0x6c 0x32>; | |
| qcom,sde-merge-3d-size = <0x100>; | |
| qcom,sde-dsc-off = <0x81000 0x81400 0x81800 0x81c00>; | |
| qcom,sde-vbif-qos-cwb-remap = <0x03 0x03 0x04 0x04 0x05 0x05 0x06 0x03>; | |
| qcom,sde-mixer-pair-mask = <0x02 0x01 0x04 0x03 0x06 0x05>; | |
| qcom,sde-dither-version = <0x10000>; | |
| qcom,sde-min-core-ib-kbps = "\0I>"; | |
| qcom,sde-pp-merge-3d-id = <0x00 0x00 0x01 0x01 0x02 0x02>; | |
| qcom,sde-off = <0x1000>; | |
| qcom,sde-vbif-memtype-0 = <0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03>; | |
| qcom,sde-sspp-clk-ctrl = <0x2ac 0x00 0x2b4 0x00 0x2bc 0x00 0x2c4 0x00 0x2ac 0x08 0x2b4 0x08 0x2bc 0x08 0x2c4 0x08>; | |
| qcom,sde-dspp-top-off = <0x1300>; | |
| qcom,sde-reg-dma-xin-id = <0x07>; | |
| #power-domain-cells = <0x00>; | |
| qcom,sde-dspp-top-size = <0x80>; | |
| qcom,sde-qos-cpu-dma-latency = <0x12c>; | |
| qcom,sde-mixer-blendstages = <0x0b>; | |
| qcom,sde-safe-lut-linear = <0x00 0xfff0>; | |
| qcom,sde-qos-lut-linear = <0x00 0x112222 0x22335777>; | |
| qcom,sde-dsc-size = <0x140>; | |
| qcom,sde-dither-size = <0x20>; | |
| qcom,sde-intf-type = "dp\0dsi\0dsi\0dp"; | |
| qcom,sde-safe-lut-nrt = <0x00 0xffff>; | |
| qcom,sde-mixer-linewidth = <0xa00>; | |
| qcom,sde-max-per-pipe-bw-high-kbps = <0x50df20 0x50df20 0x50df20 0x50df20 0x50df20 0x50df20 0x50df20 0x50df20>; | |
| qcom,sde-dest-scaler-top-size = <0x1c>; | |
| qcom,sde-wb-xin-id = <0x06>; | |
| qcom,sde-uidle-size = <0x70>; | |
| qcom,sde-qos-lut-macrotile = <0x00 0x112233 0x44556677>; | |
| qcom,sde-min-llcc-ib-kbps = <0x00>; | |
| qcom,sde-max-dest-scaler-input-linewidth = <0x800>; | |
| qcom,sde-has-src-split; | |
| qcom,sde-sspp-csc-off = <0x1a00>; | |
| qcom,sde-has-dest-scaler; | |
| compatible = "qcom,sde-kms"; | |
| qcom,sde-pp-off = <0x71000 0x71800 0x72000 0x72800 0x73000 0x73800>; | |
| qcom,sde-dest-scaler-off = <0x800 0x1000>; | |
| qcom,sde-ubwc-version = <0x400>; | |
| #interrupt-cells = <0x01>; | |
| clock-rate = <0x00 0x00 0x00 0x00 0x11e1a300 0x124f800 0x11e1a300 0x124f800>; | |
| qcom,sde-intf-size = <0x2b8>; | |
| qcom,sde-intf-off = <0x6b000 0x6b800 0x6c000 0x6c800>; | |
| qcom,sde-mixer-size = <0x320>; | |
| qcom,sde-mixer-display-pref = "primary\0primary\0none\0none\0none\0none"; | |
| qcom,sde-has-idle-pc; | |
| qcom,sde-wb-clk-ctrl = <0x2bc 0x10>; | |
| qcom,sde-merge-3d-off = "\0\b@\0\0\bA\0\0\bB"; | |
| qcom,sde-min-dram-ib-kbps = "\0\f5"; | |
| reg = <0xae00000 0x84208 0xaeb0000 0x2008 0xaeac000 0x214 0xae8f000 0x2c 0xaf50000 0x38>; | |
| qcom,sde-mixer-off = <0x45000 0x46000 0x47000 0x48000 0x49000 0x4a000>; | |
| qcom,sde-max-bw-low-kbps = <0xd10ba0>; | |
| qcom,sde-pipe-order-version = <0x01>; | |
| qcom,sde-highest-bank-bit = <0x03>; | |
| qcom,sde-vbif-id = <0x00>; | |
| phandle = <0x24c>; | |
| qcom,sde-cdm-size = <0x224>; | |
| qcom,sde-reg-dma-clk-ctrl = <0x2bc 0x14>; | |
| qcom,sde-vbif-qos-rt-remap = <0x03 0x03 0x04 0x04 0x05 0x05 0x06 0x06>; | |
| qcom,sde-qos-lut-cwb = <0x00 0x66666541 0x00>; | |
| qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 0xb0 0xc8 0xe0 0xf8 0x110>; | |
| qcom,sde-uidle-off = <0x80000>; | |
| qcom,sde-num-nrt-paths = <0x00>; | |
| qcom,sde-reg-dma-off = <0x00>; | |
| qcom,sde-cdm-off = <0x7a200>; | |
| qcom,sde-vbif-qos-lutdma-remap = <0x03 0x03 0x03 0x03 0x04 0x04 0x04 0x04>; | |
| qcom,sde-dspp-ltm-version = <0x10000>; | |
| qcom,sde-reg-dma-version = <0x10002>; | |
| qcom,sde-vbif-memtype-1 = <0x03 0x03 0x03 0x03 0x03 0x03>; | |
| qcom,sde-wb-off = <0x66000>; | |
| qcom,sde-dspp-ltm-off = <0x2a000 0x28100>; | |
| qcom,sde-has-cdp; | |
| qcom,sde-sspp-xin-id = <0x00 0x04 0x08 0x0c 0x01 0x05 0x09 0x0d>; | |
| qcom,sde-vbif-size = <0x1040>; | |
| qcom,sde-ubwc-static = <0x01>; | |
| qcom,sde-sspp-linewidth = <0x1000>; | |
| qcom,sde-pp-slave = <0x00 0x00 0x00 0x00 0x00 0x00>; | |
| qcom,sde-wb-linewidth = <0x1000>; | |
| qcom,sde-secure-sid-mask = <0x4000821>; | |
| interrupt-controller; | |
| qcom,sde-dspp-off = <0x55000 0x57000 0x59000 0x5b000>; | |
| qcom,sde-sspp-type = "vig\0vig\0vig\0vig\0dma\0dma\0dma\0dma"; | |
| #cooling-cells = <0x02>; | |
| qcom,sde-len = <0x494>; | |
| qcom,sde-has-dim-layer; | |
| qcom,sde-max-bw-high-kbps = <0xfd4bc0>; | |
| mmcx-supply = <0x69>; | |
| qcom,mdss_dsi_sw43404_amoled_wqhd_cmd { | |
| qcom,ulps-enabled; | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-panel-status-read-length = <0x01>; | |
| qcom,mdss-dsi-panel-name = "sw43404 amoled cmd mode dsi boe panel with DSC"; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0\0src_byte_clk0\0src_pixel_clk0\0shadow_byte_clk0\0shadow_pixel_clk0"; | |
| qcom,mdss-dsi-panel-status-value = <0x9c>; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-bl-max-level = <0x3ff>; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,mdss-dsi-qsync-min-refresh-rate = <0x37>; | |
| qcom,platform-reset-gpio = <0x66 0x4b 0x00>; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,mdss-dsi-panel-test-pin = <0x66 0x2e 0x00>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,dsi-dyn-clk-enable; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-physical-type = "oled"; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,dsi-dyn-clk-list = <0x20ed5435 0x20c6bcfc 0x20a025c3>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| phandle = <0x63f>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,panel-supply-entries = <0x638>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,mdss-dsi-lane-map = "lane_map_0123"; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,platform-te-gpio = <0x66 0x42 0x00>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-brightness-max-level = <0xff>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@1 { | |
| qcom,mdss-dsi-qsync-off-commands = [15 01 00 00 00 00 02 5a 00]; | |
| qcom,partial-update-enabled = "single_roi"; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x32>; | |
| qcom,mdss-dsi-h-pulse-width = <0x0c>; | |
| qcom,mdss-dsi-nolp-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-jitter = <0x04 0x01>; | |
| qcom,mdss-dsi-nolp-command = [05 01 00 00 00 00 02 38 00]; | |
| qcom,mdss-dsi-lp1-command = [05 01 00 00 00 00 02 39 00]; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-qsync-on-commands = [15 01 00 00 00 00 02 5a 01]; | |
| qcom,mdss-dsi-panel-height = <0xb40>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 03 b0 a5 00 39 01 00 00 00 00 03 5c 42 00 07 01 00 00 00 00 02 01 00 0a 01 00 00 00 00 80 11 00 00 89 30 80 0b 40 05 a0 05 a0 02 d0 02 d0 02 00 02 68 00 20 9a db 00 0a 00 0c 00 12 00 0e 18 00 10 f0 03 0c 20 00 06 0b 0b 33 0e 1c 2a 38 46 54 62 69 70 77 79 7b 7d 7e 01 02 01 00 09 40 09 be 19 fc 19 fa 19 f8 1a 38 1a 78 1a b6 2a f6 2b 34 2b 74 3b 74 6b f4 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 39 01 00 00 00 00 03 b0 a5 00 39 01 00 00 00 00 09 f8 00 08 10 08 2d 00 00 2d 15 01 00 00 00 00 02 55 00 05 01 00 00 1e 00 02 11 00 39 01 00 00 00 00 03 b0 a5 00 15 01 00 00 00 00 02 e0 18 39 01 00 00 00 00 0c c0 00 53 6f 51 50 51 34 4f 5a 33 19 05 01 00 00 78 00 02 35 00 05 01 00 00 3c 00 02 29 00 39 01 00 00 00 00 03 b0 a5 00 39 01 00 00 00 00 0c b1 a0 9f 4f 4f 63 0e 0a 10 0e 0a 10 39 01 00 00 00 00 07 e4 30 06 00 40 34 03 39 01 00 00 00 00 03 b0 a5 00 39 01 00 00 00 00 0c b1 a0 9f 4f 4f 63 0e 0a 10 0e 0a 10 39 01 00 00 00 00 07 e4 30 06 00 40 34 03]; | |
| qcom,mdss-dsi-h-front-porch = <0x3c>; | |
| qcom,mdss-dsc-slice-width = <0x2d0>; | |
| qcom,mdss-dsi-h-back-porch = <0x1e>; | |
| qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 03 b0 a5 00 39 01 00 00 00 00 0c b1 a0 9f 4f 4f 63 0e 0a 10 0e 0a 10 39 01 00 00 00 00 07 e4 30 06 00 40 34 03]; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-lp1-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0xb4>; | |
| qcom,mdss-dsi-qsync-off-commands-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x5a0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 13 04 04 1f 1e 05 05 03 02 04 00 12 14]; | |
| qcom,mdss-dsi-v-back-porch = <0x0a>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,panel-roi-alignment = <0x2d0 0xb4 0xb4 0xb4 0x5a0 0xb4>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-qsync-on-commands-state = "dsi_lp_mode"; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@2 { | |
| qcom,mdss-dsi-qsync-off-commands = [15 01 00 00 00 00 02 5a 00]; | |
| qcom,partial-update-enabled = "single_roi"; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x28>; | |
| qcom,mdss-dsi-h-pulse-width = <0x0c>; | |
| qcom,mdss-dsi-nolp-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-jitter = <0x04 0x01>; | |
| qcom,mdss-dsi-nolp-command = [05 01 00 00 00 00 02 38 00]; | |
| qcom,mdss-dsi-lp1-command = [05 01 00 00 00 00 02 39 00]; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-qsync-on-commands = [15 01 00 00 00 00 02 5a 01]; | |
| qcom,mdss-dsi-panel-height = <0xb40>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 03 b0 a5 00 39 01 00 00 00 00 03 5c 42 00 07 01 00 00 00 00 02 01 00 0a 01 00 00 00 00 80 11 00 00 89 30 80 0b 40 05 a0 05 a0 02 d0 02 d0 02 00 02 68 00 20 9a db 00 0a 00 0c 00 12 00 0e 18 00 10 f0 03 0c 20 00 06 0b 0b 33 0e 1c 2a 38 46 54 62 69 70 77 79 7b 7d 7e 01 02 01 00 09 40 09 be 19 fc 19 fa 19 f8 1a 38 1a 78 1a b6 2a f6 2b 34 2b 74 3b 74 6b f4 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 39 01 00 00 00 00 03 b0 a5 00 39 01 00 00 00 00 09 f8 00 08 10 08 2d 00 00 2d 15 01 00 00 00 00 02 55 00 05 01 00 00 1e 00 02 11 00 39 01 00 00 00 00 03 b0 a5 00 15 01 00 00 00 00 02 e0 18 39 01 00 00 00 00 0c c0 00 53 6f 51 50 51 34 4f 5a 33 19 05 01 00 00 78 00 02 35 00 05 01 00 00 3c 00 02 29 00 39 01 00 00 00 00 03 b0 a5 00 39 01 00 00 00 00 0c b1 a0 9f 4f 4f 63 0e 0a 10 0e 0a 10 39 01 00 00 00 00 07 e4 30 06 00 40 34 03 39 01 00 00 00 00 03 b0 a5 00 39 01 00 00 00 00 0c b1 a0 9f 63 4f 63 0e 0a 10 0e 0a 10 39 01 00 00 00 00 07 e4 30 06 00 40 34 03]; | |
| qcom,mdss-dsi-h-front-porch = <0x3c>; | |
| qcom,mdss-dsc-slice-width = <0x2d0>; | |
| qcom,mdss-dsi-h-back-porch = <0x1e>; | |
| qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 03 b0 a5 00 39 01 00 00 00 00 0c b1 a0 9f 63 4f 63 0e 0a 10 0e 0a 10 39 01 00 00 00 00 07 e4 30 06 00 40 34 03]; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-lp1-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0xb4>; | |
| qcom,mdss-dsi-qsync-off-commands-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x5a0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 11 03 04 1e 1e 04 04 02 02 04 00 10 14]; | |
| qcom,mdss-dsi-v-back-porch = <0x0c>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,panel-roi-alignment = <0x2d0 0xb4 0xb4 0xb4 0x5a0 0xb4>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-qsync-on-commands-state = "dsi_lp_mode"; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@0 { | |
| qcom,mdss-dsi-qsync-off-commands = [15 01 00 00 00 00 02 5a 00]; | |
| qcom,partial-update-enabled = "single_roi"; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x0c>; | |
| qcom,mdss-dsi-nolp-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-jitter = <0x06 0x01>; | |
| qcom,mdss-dsi-nolp-command = [05 01 00 00 00 00 02 38 00]; | |
| qcom,mdss-dsi-lp1-command = [05 01 00 00 00 00 02 39 00]; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-qsync-on-commands = [15 01 00 00 00 00 02 5a 01]; | |
| qcom,mdss-dsi-panel-height = <0xb40>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = <0x39010000 0x3b0 0xa5003901 0x00 0x35c4200 0x7010000 0x201 0xa0100 0x80 0x11000089 0x30800b40 0x5a005a0 0x2d002d0 0x2000268 0x209adb 0xa000c 0x12000e 0x180010f0 0x30c2000 0x60b0b33 0xe1c2a38 0x46546269 0x7077797b 0x7d7e0102 0x1000940 0x9be19fc 0x19fa19f8 0x1a381a78 0x1ab62af6 0x2b342b74 0x3b746bf4 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x39010000 0x3b0 0xa5003901 0x00 0x9f80008 0x10082d00 0x2d1501 0x00 0x2550805 0x100001e 0x21100 0x39010000 0x3b0 0xa5001501 0x00 0x2e01839 0x1000000 0xcc000 0x536f5150 0x51344f5a 0x33190501 0x7800 0x2350005 0x100003c 0x22900>; | |
| qcom,mdss-dsi-h-front-porch = <0x3c>; | |
| qcom,mdss-dsc-slice-width = <0x2d0>; | |
| qcom,mdss-dsi-h-back-porch = <0x1e>; | |
| qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 03 b0 a5 00 39 01 00 00 00 00 0c b1 a0 9f 42 4f 63 0e 0a 10 0e 0a 10 39 01 00 00 00 00 07 e4 30 06 00 40 34 03]; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-lp1-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0xb4>; | |
| qcom,mdss-dsi-qsync-off-commands-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x5a0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 1f 1e 05 05 03 02 04 00 12 15]; | |
| qcom,mdss-dsi-v-back-porch = <0x08>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,panel-roi-alignment = <0x2d0 0xb4 0xb4 0xb4 0x5a0 0xb4>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-qsync-on-commands-state = "dsi_lp_mode"; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-mdp-transfer-time-us = <0x3bc4>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_nt35597_wqxga_video_truly { | |
| qcom,dsi-phy-num = <0x00 0x01>; | |
| qcom,mdss-pan-physical-width-dimension = <0x4a>; | |
| qcom,mdss-dsi-panel-name = "Dual nt35597 video mode dsi truly panel without DSC"; | |
| qcom,mdss-dsi-min-refresh-rate = <0x35>; | |
| qcom,mdss-pan-physical-height-dimension = <0x83>; | |
| qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0"; | |
| qcom,mdss-dsi-underflow-color = <0x3ff>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-max-refresh-rate = <0x3c>; | |
| qcom,config-select = <0x63a>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00 0x01>; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,mdss-dsi-pan-enable-dynamic-fps; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x14 0x00 0x14 0x01 0x32>; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| phandle = <0x6d8>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-panel-timings = <0xe2362400 0x666a2838 0x2a030400>; | |
| qcom,display-topology = <0x02 0x00 0x02 0x01 0x00 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 55 15 01 00 00 00 00 02 02 45 15 01 00 00 00 00 02 05 40 15 01 00 00 00 00 02 06 19 15 01 00 00 00 00 02 07 1e 15 01 00 00 00 00 02 0b 73 15 01 00 00 00 00 02 0c 73 15 01 00 00 00 00 02 0e b0 15 01 00 00 00 00 02 0f ae 15 01 00 00 00 00 02 11 b8 15 01 00 00 00 00 02 13 00 15 01 00 00 00 00 02 58 80 15 01 00 00 00 00 02 59 01 15 01 00 00 00 00 02 5a 00 15 01 00 00 00 00 02 5b 01 15 01 00 00 00 00 02 5c 80 15 01 00 00 00 00 02 5d 81 15 01 00 00 00 00 02 5e 00 15 01 00 00 00 00 02 5f 01 15 01 00 00 00 00 02 72 31 15 01 00 00 00 00 02 68 03 15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 1c 15 01 00 00 00 00 02 01 0b 15 01 00 00 00 00 02 02 0c 15 01 00 00 00 00 02 03 01 15 01 00 00 00 00 02 04 0f 15 01 00 00 00 00 02 05 10 15 01 00 00 00 00 02 06 10 15 01 00 00 00 00 02 07 10 15 01 00 00 00 00 02 08 89 15 01 00 00 00 00 02 09 8a 15 01 00 00 00 00 02 0a 13 15 01 00 00 00 00 02 0b 13 15 01 00 00 00 00 02 0c 15 15 01 00 00 00 00 02 0d 15 15 01 00 00 00 00 02 0e 17 15 01 00 00 00 00 02 0f 17 15 01 00 00 00 00 02 10 1c 15 01 00 00 00 00 02 11 0b 15 01 00 00 00 00 02 12 0c 15 01 00 00 00 00 02 13 01 15 01 00 00 00 00 02 14 0f 15 01 00 00 00 00 02 15 10 15 01 00 00 00 00 02 16 10 15 01 00 00 00 00 02 17 10 15 01 00 00 00 00 02 18 89 15 01 00 00 00 00 02 19 8a 15 01 00 00 00 00 02 1a 13 15 01 00 00 00 00 02 1b 13 15 01 00 00 00 00 02 1c 15 15 01 00 00 00 00 02 1d 15 15 01 00 00 00 00 02 1e 17 15 01 00 00 00 00 02 1f 17 15 01 00 00 00 00 02 20 40 15 01 00 00 00 00 02 21 01 15 01 00 00 00 00 02 22 00 15 01 00 00 00 00 02 23 40 15 01 00 00 00 00 02 24 40 15 01 00 00 00 00 02 25 6d 15 01 00 00 00 00 02 26 40 15 01 00 00 00 00 02 27 40 15 01 00 00 00 00 02 e0 00 15 01 00 00 00 00 02 dc 21 15 01 00 00 00 00 02 dd 22 15 01 00 00 00 00 02 de 07 15 01 00 00 00 00 02 df 07 15 01 00 00 00 00 02 e3 6d 15 01 00 00 00 00 02 e1 07 15 01 00 00 00 00 02 e2 07 15 01 00 00 00 00 02 29 d8 15 01 00 00 00 00 02 2a 2a 15 01 00 00 00 00 02 4b 03 15 01 00 00 00 00 02 4c 11 15 01 00 00 00 00 02 4d 10 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 4f 01 15 01 00 00 00 00 02 50 10 15 01 00 00 00 00 02 51 00 15 01 00 00 00 00 02 52 80 15 01 00 00 00 00 02 53 00 15 01 00 00 00 00 02 56 00 15 01 00 00 00 00 02 54 07 15 01 00 00 00 00 02 58 07 15 01 00 00 00 00 02 55 25 15 01 00 00 00 00 02 5b 43 15 01 00 00 00 00 02 5c 00 15 01 00 00 00 00 02 5f 73 15 01 00 00 00 00 02 60 73 15 01 00 00 00 00 02 63 22 15 01 00 00 00 00 02 64 00 15 01 00 00 00 00 02 67 08 15 01 00 00 00 00 02 68 04 15 01 00 00 00 00 02 72 02 15 01 00 00 00 00 02 7a 80 15 01 00 00 00 00 02 7b 91 15 01 00 00 00 00 02 7c d8 15 01 00 00 00 00 02 7d 60 15 01 00 00 00 00 02 7f 15 15 01 00 00 00 00 02 75 15 15 01 00 00 00 00 02 b3 c0 15 01 00 00 00 00 02 b4 00 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 78 00 15 01 00 00 00 00 02 79 00 15 01 00 00 00 00 02 80 00 15 01 00 00 00 00 02 83 00 15 01 00 00 00 00 02 93 0a 15 01 00 00 00 00 02 94 0a 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 9b ff 15 01 00 00 00 00 02 9d b0 15 01 00 00 00 00 02 9f 63 15 01 00 00 00 00 02 98 10 15 01 00 00 00 00 02 ec 00 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 04 3b 03 0a 0a 15 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 e5 01 15 01 00 00 00 00 02 bb 03 15 01 00 00 00 00 02 fb 01 05 01 00 00 78 00 02 11 00 05 01 00 00 78 00 02 29 00]; | |
| qcom,mdss-dsi-h-front-porch = <0x64>; | |
| qcom,mdss-dsi-h-back-porch = <0x20>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 07 05 02 04 00 18 17]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-panel-timings-phy-v2 = <0x231e0708 0x50304a0 0x231e0708 0x50304a0 0x231e0708 0x50304a0 0x231e0708 0x50304a0 0x23180708 0x40304a0>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| config0 { | |
| qcom,split-mode = "dualctl-split"; | |
| phandle = <0x63a>; | |
| }; | |
| }; | |
| qcom,smmu_sde_unsec_cb { | |
| iommus = <0x47 0x820 0x402>; | |
| compatible = "qcom,smmu_sde_unsec"; | |
| qcom,iommu-dma-addr-pool = <0x20000 0xfffe0000>; | |
| phandle = <0x550>; | |
| qcom,iommu-faults = "non-fatal"; | |
| qcom,iommu-earlymap; | |
| }; | |
| qcom,mdss_dsi_rm69380_edo_amoled_cmd_second { | |
| qcom,adjust-timer-wakeup-ms = <0x01>; | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,dsi-phy-num = <0x00 0x01>; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-panel-status-read-length = <0x01>; | |
| qcom,mdss-dsi-panel-name = "rm69380 amoled wqxga cmd mode dsi edo sec panel"; | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0"; | |
| qcom,mdss-dsi-panel-status-value = <0x9c>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00 0x01>; | |
| qcom,mdss-dsi-bl-max-level = <0x7ff>; | |
| qcom,platform-en-gpio = <0x66 0x3c 0x00>; | |
| qcom,platform-reset-gpio = <0x66 0x4b 0x00>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0f 0x00 0x0a 0x01 0x1e>; | |
| qcom,dynamic-mode-switch-type = "dynamic-resolution-switch-immediate"; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,dynamic-mode-switch-enabled; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; | |
| phandle = <0x69a>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,panel-supply-entries = <0x638>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,dcs-cmd-by-left; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,platform-te-gpio = <0x66 0x42 0x00>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@1 { | |
| qcom,display-topology = <0x02 0x00 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x0c>; | |
| qcom,mdss-highlight-off-command = [39 01 00 00 00 00 03 51 07 ff]; | |
| qcom,mdss-dsi-timing-switch-command-state = "dsi_hs_mode"; | |
| qcom,mdss-highlight-off-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-height = <0x640>; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 fe d4 39 01 00 00 00 00 02 00 80 39 01 00 00 00 00 02 fe d0 39 01 00 00 00 00 02 48 00 39 01 00 00 00 00 02 fe 40 39 01 00 00 00 00 02 bd 05 39 01 00 00 00 00 02 fe 00 39 01 00 00 00 00 02 53 28 39 01 00 00 00 00 02 c2 08 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 03 51 07 ff 05 01 00 00 14 00 02 11 00 05 01 00 00 24 00 02 29 00]; | |
| qcom,mdss-dsi-h-front-porch = <0x20>; | |
| qcom,mdss-dsi-h-back-porch = <0x26>; | |
| qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 fe 40 39 01 00 00 00 00 02 bd 05 39 01 00 00 00 00 02 fe 00]; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x500>; | |
| qcom,mdss-dsi-v-pulse-width = <0x04>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 27 0a 0a 1b 25 0a 0b 0a 02 04 00 20 0f]; | |
| qcom,mdss-dsi-v-back-porch = <0x08>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-highlight-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-highlight-on-command = [39 01 00 00 00 00 03 51 0f ff]; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 23 00 02 28 00 05 01 00 00 14 00 02 10 00]; | |
| qcom,mdss-dsi-v-front-porch = <0x14>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@0 { | |
| qcom,display-topology = <0x02 0x00 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x5a>; | |
| qcom,mdss-dsi-h-pulse-width = <0x0c>; | |
| qcom,mdss-highlight-off-command = [39 01 00 00 00 00 03 51 07 ff]; | |
| qcom,mdss-dsi-timing-switch-command-state = "dsi_hs_mode"; | |
| qcom,mdss-highlight-off-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-height = <0x640>; | |
| qcom,mdss-dsi-on-command = <0x39010000 0x2fe 0xd4390100 0x02 0x803901 0x00 0x2fed039 0x1000000 0x24800 0x39010000 0x2fe 0x390100 0x02 0x53283901 0x00 0x2c20839 0x1000000 0x23500 0x39010000 0x351 0x7ff0501 0x1400 0x2110005 0x1000024 0x22900>; | |
| qcom,mdss-dsi-h-front-porch = <0x20>; | |
| qcom,mdss-dsi-h-back-porch = <0x26>; | |
| qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 fe 40 39 01 00 00 00 00 02 bd 01 39 01 00 00 00 00 02 fe 00]; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x500>; | |
| qcom,mdss-dsi-v-pulse-width = <0x04>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 27 0a 0a 1b 25 0a 0b 0a 02 04 00 20 0f]; | |
| qcom,mdss-dsi-v-back-porch = <0x08>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-highlight-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-highlight-on-command = [39 01 00 00 00 00 03 51 0f ff]; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 23 00 02 28 00 05 01 00 00 14 00 02 10 00]; | |
| qcom,mdss-dsi-v-front-porch = <0x14>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_r66451_fhd_plus_144hz_cmd { | |
| qcom,dsi-sec-phy-num = <0x01>; | |
| qcom,ulps-enabled; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-panel-status-read-length = <0x01>; | |
| qcom,dsi-sec-ctrl-num = <0x01>; | |
| qcom,mdss-dsi-panel-name = "r66451 amoled cmd mode dsi visionox panel with DSC"; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0"; | |
| qcom,mdss-dsi-panel-status-value = <0x1c>; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-physical-type = "oled"; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| phandle = <0x6e5>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-lane-map = "lane_map_0123"; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x90>; | |
| qcom,mdss-dsi-h-pulse-width = <0x01>; | |
| qcom,mdss-dsi-panel-jitter = <0x04 0x01>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 e8 00 02 39 01 00 00 00 00 03 e4 00 08 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 32 c4 00 00 00 00 00 00 00 00 10 00 00 02 00 00 00 29 00 01 00 00 00 00 00 00 00 00 00 00 00 22 00 00 00 00 11 00 00 0c 00 00 00 00 30 00 00 00 00 00 00 39 01 00 00 00 00 86 cf 64 0b 00 00 00 00 00 00 08 00 0b 77 01 01 01 01 01 01 02 02 02 02 02 03 00 00 00 00 00 00 00 00 00 00 00 00 02 c9 02 c9 02 c9 03 ff 03 ff 03 ff 00 00 00 00 00 00 00 00 00 00 00 00 02 c9 02 c9 02 c9 03 ff 03 ff 03 ff 01 62 01 62 01 62 01 62 01 62 01 62 01 62 01 62 01 62 01 62 01 62 01 62 19 19 19 19 19 19 19 19 19 19 19 19 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0f f6 0f f6 0f f6 0f f6 0f f6 19 39 01 00 00 00 00 0d d0 44 44 b2 28 00 28 5a 00 5a 0d 17 01 39 01 00 00 00 00 15 d3 49 00 00 01 1a 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9a 39 01 00 00 00 00 1a d7 00 b9 40 00 40 04 00 f0 0f 00 40 00 00 00 00 00 00 19 40 00 40 04 00 f0 0f 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 30 00 30 00 30 00 30 00 30 05 00 00 00 00 00 00 00 00 00 0f 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 0f 00 2f 00 0f 00 20 39 01 00 00 00 00 2b df 50 42 58 81 2d 00 00 00 00 00 00 6b 00 00 00 00 00 00 00 00 01 0f ff d4 0e 00 00 00 00 00 00 0f 53 18 00 0f 00 00 00 00 00 00 39 01 00 00 00 00 02 f7 01 39 01 00 00 00 00 02 b0 80 39 01 00 00 00 00 0a e4 34 b4 00 00 00 30 04 0c e2 39 01 00 00 00 00 02 e6 00 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 df 50 40 39 01 00 00 00 00 06 f3 50 00 00 00 00 39 01 00 00 00 00 02 f2 11 39 01 00 00 00 00 06 f3 01 00 00 00 01 39 01 00 00 00 00 03 f4 00 02 39 01 00 00 00 00 02 f2 19 39 01 00 00 00 00 03 df 50 42 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 05 01 00 00 78 00 01 11 05 01 00 00 00 00 01 29]; | |
| qcom,mdss-dsi-h-front-porch = <0x5f>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x28>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x14>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 19 17 09 09 09 02 04 00 1d 0e]; | |
| qcom,mdss-dsi-v-back-porch = <0x04>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x19>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_xrsmrtvwr_video_jdi { | |
| qcom,dsi-phy-num = <0x00 0x01>; | |
| qcom,mdss-pan-physical-width-dimension = <0x34>; | |
| qcom,mdss-dsi-panel-status-read-length = <0x01>; | |
| qcom,mdss-dsi-panel-name = "Dual Smart XR Viewer LPM029M483A R63455 jdi panel"; | |
| qcom,mdss-dsi-min-refresh-rate = <0x35>; | |
| qcom,mdss-pan-physical-height-dimension = <0x34>; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0"; | |
| qcom,mdss-dsi-panel-status-value = <0x9c>; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-max-refresh-rate = <0x50>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00 0x01>; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x14 0x00 0x14 0x01 0x32>; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-on-check-value = <0x9c>; | |
| phandle = <0x6e4>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,display-topology = <0x02 0x00 0x02 0x01 0x00 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x4b>; | |
| qcom,mdss-dsi-h-pulse-width = <0x14>; | |
| qcom,mdss-dsi-panel-height = <0x5a0>; | |
| qcom,mdss-dsi-on-command = <0x29010000 0x2b0 0x4290100 0x02 0xd6002901 0x00 0xab6306b 0x8006338a 0x1a7a29 0x1000000 0x5b754 0x29 0x1000000 0xdb900 0x8501bf00 0x00 0x8501bf29 0x1000000 0x9c061 0x86580208 0x7004ec29 0x1000000 0x2f11e 0x29010000 0x9c6 0xa005a005 0x439f0543 0x29010000 0x2cd 0x11290100 0x08 0xcf000080 0x46610000 0x29010000 0x7ec 0x18e0000 0x3901 0x00 0x2030039 0x1000000 0x34400 0x390100 0x02 0x35003901 0x00 0x2360039 0x1000000 0x23a77 0x5010000 0x2000229 0x50100 0x800002 0x11002901 0x00 0x2d68029 0x1000000 0x2b003>; | |
| qcom,mdss-dsi-h-front-porch = <0x28>; | |
| qcom,mdss-dsi-h-back-porch = <0x28>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x5a0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x04>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 17 05 05 20 1f 06 06 03 02 04 00 13 15]; | |
| qcom,mdss-dsi-v-back-porch = <0x10>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 32 00 02 34 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-v-front-porch = <0x142>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,smmu_sde_sec_cb { | |
| iommus = <0x47 0x821 0x400>; | |
| compatible = "qcom,smmu_sde_sec"; | |
| qcom,iommu-dma-addr-pool = <0x20000 0xfffe0000>; | |
| phandle = <0x551>; | |
| qcom,iommu-faults = "non-fatal"; | |
| qcom,iommu-vmid = <0x0a>; | |
| }; | |
| qcom,mdss_dsi_sharp_4k_dsc_cmd { | |
| qcom,ulps-enabled; | |
| qcom,adjust-timer-wakeup-ms = <0x01>; | |
| qcom,dsi-phy-num = <0x00 0x01>; | |
| qcom,mdss-pan-physical-width-dimension = <0x47>; | |
| qcom,mdss-dsi-panel-name = "Sharp 4k cmd mode dsc dsi panel"; | |
| qcom,mdss-pan-physical-height-dimension = <0x81>; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0"; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00 0x01>; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x64 0x00 0x64 0x01 0x64>; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| phandle = <0x6d3>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,dcs-cmd-by-left; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,mdss-dsi-panel-jitter = <0x08 0x0a>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-panel-height = <0xf00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 01 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29]; | |
| qcom,mdss-dsi-h-front-porch = <0x1e>; | |
| qcom,mdss-dsc-slice-width = <0x438>; | |
| qcom,mdss-dsi-h-back-porch = <0x64>; | |
| qcom,mdss-dsc-slice-height = <0x20>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 08 05 02 04 00 19 18]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_nt35695b_truly_fhd_cmd { | |
| qcom,dsi-sec-phy-num = <0x01>; | |
| qcom,ulps-enabled; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,dsi-sec-ctrl-num = <0x01>; | |
| qcom,mdss-dsi-panel-name = "nt35695b truly fhd command mode dsi panel"; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-post-init-delay = <0x01>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| phandle = <0x6d9>; | |
| qcom,dsi-select-sec-clocks = "mux_byte_clk1\0mux_pixel_clk1"; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x01 0x00 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x0c>; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsi-on-command = [15 01 00 00 10 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 55 15 01 00 00 00 00 02 02 45 15 01 00 00 00 00 02 03 55 15 01 00 00 00 00 02 05 50 15 01 00 00 00 00 02 06 a8 15 01 00 00 00 00 02 07 ad 15 01 00 00 00 00 02 08 0c 15 01 00 00 00 00 02 0b aa 15 01 00 00 00 00 02 0c aa 15 01 00 00 00 00 02 0e b0 15 01 00 00 00 00 02 0f b3 15 01 00 00 00 00 02 11 28 15 01 00 00 00 00 02 12 10 15 01 00 00 00 00 02 13 01 15 01 00 00 00 00 02 14 4a 15 01 00 00 00 00 02 15 12 15 01 00 00 00 00 02 16 12 15 01 00 00 00 00 02 30 01 15 01 00 00 00 00 02 72 11 15 01 00 00 00 00 02 58 82 15 01 00 00 00 00 02 59 00 15 01 00 00 00 00 02 5a 02 15 01 00 00 00 00 02 5b 00 15 01 00 00 00 00 02 5c 82 15 01 00 00 00 00 02 5d 80 15 01 00 00 00 00 02 5e 02 15 01 00 00 00 00 02 5f 00 15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 0b 15 01 00 00 00 00 02 02 0c 15 01 00 00 00 00 02 03 89 15 01 00 00 00 00 02 04 8a 15 01 00 00 00 00 02 05 0f 15 01 00 00 00 00 02 06 10 15 01 00 00 00 00 02 07 10 15 01 00 00 00 00 02 08 1c 15 01 00 00 00 00 02 09 00 15 01 00 00 00 00 02 0a 00 15 01 00 00 00 00 02 0b 00 15 01 00 00 00 00 02 0c 00 15 01 00 00 00 00 02 0d 13 15 01 00 00 00 00 02 0e 15 15 01 00 00 00 00 02 0f 17 15 01 00 00 00 00 02 10 01 15 01 00 00 00 00 02 11 0b 15 01 00 00 00 00 02 12 0c 15 01 00 00 00 00 02 13 89 15 01 00 00 00 00 02 14 8a 15 01 00 00 00 00 02 15 0f 15 01 00 00 00 00 02 16 10 15 01 00 00 00 00 02 17 10 15 01 00 00 00 00 02 18 1c 15 01 00 00 00 00 02 19 00 15 01 00 00 00 00 02 1a 00 15 01 00 00 00 00 02 1b 00 15 01 00 00 00 00 02 1c 00 15 01 00 00 00 00 02 1d 13 15 01 00 00 00 00 02 1e 15 15 01 00 00 00 00 02 1f 17 15 01 00 00 00 00 02 20 00 15 01 00 00 00 00 02 21 01 15 01 00 00 00 00 02 22 00 15 01 00 00 00 00 02 23 40 15 01 00 00 00 00 02 24 40 15 01 00 00 00 00 02 25 6d 15 01 00 00 00 00 02 26 40 15 01 00 00 00 00 02 27 40 15 01 00 00 00 00 02 29 d8 15 01 00 00 00 00 02 2a 2a 15 01 00 00 00 00 02 4b 03 15 01 00 00 00 00 02 4c 11 15 01 00 00 00 00 02 4d 10 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 4f 01 15 01 00 00 00 00 02 50 10 15 01 00 00 00 00 02 51 00 15 01 00 00 00 00 02 52 80 15 01 00 00 00 00 02 53 00 15 01 00 00 00 00 02 54 07 15 01 00 00 00 00 02 55 25 15 01 00 00 00 00 02 56 00 15 01 00 00 00 00 02 58 07 15 01 00 00 00 00 02 5b 43 15 01 00 00 00 00 02 5c 00 15 01 00 00 00 00 02 5f 73 15 01 00 00 00 00 02 60 73 15 01 00 00 00 00 02 63 22 15 01 00 00 00 00 02 64 00 15 01 00 00 00 00 02 67 08 15 01 00 00 00 00 02 68 04 15 01 00 00 00 00 02 7a 80 15 01 00 00 00 00 02 7b 91 15 01 00 00 00 00 02 7c d8 15 01 00 00 00 00 02 7d 60 15 01 00 00 00 00 02 93 06 15 01 00 00 00 00 02 94 06 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 9b 0f 15 01 00 00 00 00 02 b3 c0 15 01 00 00 00 00 02 b4 00 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 b6 21 15 01 00 00 00 00 02 b7 22 15 01 00 00 00 00 02 b8 07 15 01 00 00 00 00 02 b9 07 15 01 00 00 00 00 02 ba 22 15 01 00 00 00 00 02 bd 20 15 01 00 00 00 00 02 be 07 15 01 00 00 00 00 02 bf 07 15 01 00 00 00 00 02 c1 6d 15 01 00 00 00 00 02 c4 24 15 01 00 00 00 00 02 e3 00 15 01 00 00 00 00 02 ec 00 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bb 10 15 01 00 00 00 00 02 35 00 05 01 00 00 78 00 02 11 00 05 01 00 00 78 00 02 29 00]; | |
| qcom,mdss-dsi-h-front-porch = <0x78>; | |
| qcom,mdss-dsi-h-back-porch = <0x3c>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 08 05 02 04 00 19 17]; | |
| qcom,mdss-dsi-v-back-porch = <0x02>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-v-front-porch = <0x0c>; | |
| qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_sim_dsc_375_cmd { | |
| qcom,ulps-enabled; | |
| qcom,adjust-timer-wakeup-ms = <0x01>; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-panel-name = "Simulator cmd mode DSC 3.75:1 dsi panel"; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,panel-ack-disabled; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,platform-reset-gpio = <0x66 0x4b 0x00>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-te-using-wd; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| phandle = <0x6df>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,panel-supply-entries = <0x638>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@1 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01 0x02 0x02 0x01 0x02 0x01 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x00>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = <0x15010000 0x2bb 0x10150100 0x02 0xb0030501 0x7800 0x1111501 0x00 0x251ff15 0x1000000 0x25324 0x15010000 0x2ff 0x23150100 0x02 0x8051501 0x00 0x2469015 0x1000000 0x2ff10 0x15010000 0x2ff 0xf0150100 0x02 0x92011501 0x00 0x2ff1015 0x1000000 0x23500 0x5010000 0x28000129>; | |
| qcom,mdss-dsi-h-front-porch = <0x00>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x00>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x10>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x00>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 08 05 02 04 00 19 18]; | |
| qcom,mdss-dsi-v-back-porch = <0x00>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x02>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = <0x5010000 0x10000128 0x5010000 0x40000110>; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x00>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@2 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x90>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = <0x15010000 0x2bb 0x10150100 0x02 0xb0030501 0x7800 0x1111501 0x00 0x251ff15 0x1000000 0x25324 0x15010000 0x2ff 0x23150100 0x02 0x8051501 0x00 0x2469015 0x1000000 0x2ff10 0x15010000 0x2ff 0xf0150100 0x02 0x92011501 0x00 0x2ff1015 0x1000000 0x23500 0x5010000 0x28000129>; | |
| qcom,mdss-dsi-h-front-porch = <0x64>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x20>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x10>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 22 20 07 06 04 02 04 00 16 16]; | |
| qcom,mdss-dsi-v-back-porch = <0x08>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x02>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = <0x5010000 0x10000128 0x5010000 0x40000110>; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x0a>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@0 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = <0x15010000 0x2ff 0x20150100 0x02 0xfb011501 0x00 0x2000115 0x1000000 0x20155 0x15010000 0x202 0x45150100 0x02 0x5401501 0x00 0x2061915 0x1000000 0x2071e 0x15010000 0x20b 0x73150100 0x02 0xc731501 0x00 0x20eb015 0x1000000 0x20fae 0x15010000 0x211 0xb8150100 0x02 0x13001501 0x00 0x2588015 0x1000000 0x25901 0x15010000 0x25a 0x150100 0x02 0x5b011501 0x00 0x25c8015 0x1000000 0x25d81 0x15010000 0x25e 0x150100 0x02 0x5f011501 0x00 0x2723115 0x1000000 0x26803 0x15010000 0x2ff 0x24150100 0x02 0xfb011501 0x00 0x2001c15 0x1000000 0x2010b 0x15010000 0x202 0xc150100 0x02 0x3011501 0x00 0x2040f15 0x1000000 0x20510 0x15010000 0x206 0x10150100 0x02 0x7101501 0x00 0x2088915 0x1000000 0x2098a 0x15010000 0x20a 0x13150100 0x02 0xb131501 0x00 0x20c1515 0x1000000 0x20d15 0x15010000 0x20e 0x17150100 0x02 0xf171501 0x00 0x2101c15 0x1000000 0x2110b 0x15010000 0x212 0xc150100 0x02 0x13011501 0x00 0x2140f15 0x1000000 0x21510 0x15010000 0x216 0x10150100 0x02 0x17101501 0x00 0x2188915 0x1000000 0x2198a 0x15010000 0x21a 0x13150100 0x02 0x1b131501 0x00 0x21c1515 0x1000000 0x21d15 0x15010000 0x21e 0x17150100 0x02 0x1f171501 0x00 0x2204015 0x1000000 0x22101 0x15010000 0x222 0x150100 0x02 0x23401501 0x00 0x2244015 0x1000000 0x2256d 0x15010000 0x226 0x40150100 0x02 0x27401501 0x00 0x2e00015 0x1000000 0x2dc21 0x15010000 0x2dd 0x22150100 0x02 0xde071501 0x00 0x2df0715 0x1000000 0x2e36d 0x15010000 0x2e1 0x7150100 0x02 0xe2071501 0x00 0x229d815 0x1000000 0x22a2a 0x15010000 0x24b 0x3150100 0x02 0x4c111501 0x00 0x24d1015 0x1000000 0x24e01 0x15010000 0x24f 0x1150100 0x02 0x50101501 0x00 0x2510015 0x1000000 0x25280 0x15010000 0x253 0x150100 0x02 0x56001501 0x00 0x2540715 0x1000000 0x25807 0x15010000 0x255 0x25150100 0x02 0x5b431501 0x00 0x25c0015 0x1000000 0x25f73 0x15010000 0x260 0x73150100 0x02 0x63221501 0x00 0x2640015 0x1000000 0x26708 0x15010000 0x268 0x4150100 0x02 0x72021501 0x00 0x27a8015 0x1000000 0x27b91 0x15010000 0x27c 0xd8150100 0x02 0x7d601501 0x00 0x27f1515 0x1000000 0x27515 0x15010000 0x2b3 0xc0150100 0x02 0xb4001501 0x00 0x2b50015 0x1000000 0x27800 0x15010000 0x279 0x150100 0x02 0x80001501 0x00 0x2830015 0x1000000 0x2930a 0x15010000 0x294 0xa150100 0x02 0x8a001501 0x00 0x29bff15 0x1000000 0x29db0 0x15010000 0x29f 0x63150100 0x02 0x98101501 0x00 0x2ec0015 0x1000000 0x2ff10 0x39010000 0x11c1 0x9200010 0x2000268 0x1bb000a 0x66704c5 0x39010000 0x3c2 0x10f01501 0x00 0x2c00315 0x1000000 0x43b03 0xa0a1501 0x00 0x2350015 0x1000000 0x2e501 0x15010000 0x2bb 0x10150100 0x02 0xfb010501 0x7800 0x2110005 0x1000078 0x22900>; | |
| qcom,mdss-dsi-h-front-porch = <0x64>; | |
| qcom,mdss-dsc-slice-width = <0x2d0>; | |
| qcom,mdss-dsi-h-back-porch = <0x20>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x10>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x5a0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-on-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 07 05 02 04 00 18 17]; | |
| qcom,mdss-dsi-v-back-porch = <0x08>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x02>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x0a>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_sim_cmd { | |
| qcom,ulps-enabled; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-panel-name = "Simulator cmd mode dsi panel"; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-panel-mode-switch; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,panel-ack-disabled; | |
| qcom,mdss-dsi-t-clk-post = <0x03>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,platform-reset-gpio = <0x66 0x4b 0x00>; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-te-using-wd; | |
| qcom,mdss-dsi-t-clk-pre = <0x27>; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| phandle = <0x6dd>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,panel-supply-entries = <0x638>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@3 { | |
| qcom,partial-update-enabled = "single_roi"; | |
| qcom,mdss-dsi-panel-timings = <0x210909 0x24230808 0x8030400>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01 0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x28>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = <0x29010000 0x2b0 0x3050100 0xa0001 0x150100 0xa0002 0x3a773901 0xa00 0x52a0000 0x4ff3901 0xa00 0x52b0000 0x59f1501 0xa00 0x2350039 0x100000a 0x34400 0x150100 0xa0002 0x51ff1501 0xa00 0x2532415 0x100000a 0x25500 0x5010000 0x78000111 0x5010000 0x10000129>; | |
| qcom,mdss-dsi-h-front-porch = <0x78>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x1cc>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x28>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x28>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 07 05 02 04 00 18 17]; | |
| qcom,mdss-dsi-v-back-porch = <0x64>; | |
| qcom,default-topology-index = <0x01>; | |
| qcom,panel-roi-alignment = <0x21c 0x28 0x21c 0x28 0x21c 0x28>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x2e4>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@1 { | |
| qcom,video-to-cmd-mode-switch-commands = [39 01 00 00 00 00 03 b0 a5 00 07 01 00 00 00 00 02 01 00 39 01 00 00 00 00 06 b2 00 5d 04 80 49 15 01 00 00 00 00 02 3d 11 15 01 00 00 00 00 02 36 00 15 01 00 00 00 00 02 55 0b]; | |
| qcom,partial-update-enabled = "single_roi"; | |
| qcom,mdss-dsi-panel-timings = <0x210909 0x24230808 0x8030400>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01 0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x28>; | |
| qcom,video-to-cmd-mode-switch-commands-state = "dsi_lp_mode"; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-video-mode; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = <0x29010000 0x2b0 0x3050100 0xa0001 0x150100 0xa0002 0x3a773901 0xa00 0x52a0000 0x4ff3901 0xa00 0x52b0000 0x59f1501 0xa00 0x2350039 0x100000a 0x34400 0x150100 0xa0002 0x51ff1501 0xa00 0x2532415 0x100000a 0x25500 0x5010000 0x78000111 0x5010000 0x10000129>; | |
| qcom,mdss-dsi-h-front-porch = <0x78>; | |
| qcom,mdss-dsc-slice-width = <0x2d0>; | |
| qcom,mdss-dsi-h-back-porch = <0x64>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x28>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x5a0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x28>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 07 05 02 04 00 18 17]; | |
| qcom,mdss-dsi-v-back-porch = <0x64>; | |
| qcom,default-topology-index = <0x01>; | |
| qcom,panel-roi-alignment = <0x2d0 0x28 0x2d0 0x28 0x2d0 0x28>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x64>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@4 { | |
| qcom,partial-update-enabled = "single_roi"; | |
| qcom,mdss-dsi-panel-timings = <0x210909 0x24230808 0x8030400>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01 0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x28>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-panel-height = <0x500>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = <0x29010000 0x2b0 0x3050100 0xa0001 0x150100 0xa0002 0x3a773901 0xa00 0x52a0000 0x4ff3901 0xa00 0x52b0000 0x59f1501 0xa00 0x2350039 0x100000a 0x34400 0x150100 0xa0002 0x51ff1501 0xa00 0x2532415 0x100000a 0x25500 0x5010000 0x78000111 0x5010000 0x10000129>; | |
| qcom,mdss-dsi-h-front-porch = <0x64>; | |
| qcom,mdss-dsc-slice-width = <0x168>; | |
| qcom,mdss-dsi-h-back-porch = <0x348>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x28>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x28>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 07 05 02 04 00 18 17]; | |
| qcom,mdss-dsi-v-back-porch = <0x64>; | |
| qcom,default-topology-index = <0x01>; | |
| qcom,panel-roi-alignment = <0x168 0x28 0x168 0x28 0x168 0x28>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x564>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@2 { | |
| qcom,partial-update-enabled = "single_roi"; | |
| qcom,mdss-dsi-panel-timings = <0x210909 0x24230808 0x8030400>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01 0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x28>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = <0x29010000 0x2b0 0x3050100 0xa0001 0x150100 0xa0002 0x3a773901 0xa00 0x52a0000 0x4ff3901 0xa00 0x52b0000 0x59f1501 0xa00 0x2350039 0x100000a 0x34400 0x150100 0xa0002 0x51ff1501 0xa00 0x2532415 0x100000a 0x25500 0x5010000 0x78000111 0x5010000 0x10000129>; | |
| qcom,mdss-dsi-h-front-porch = <0x78>; | |
| qcom,mdss-dsc-slice-width = <0x2d0>; | |
| qcom,mdss-dsi-h-back-porch = <0x64>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x28>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x5a0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x28>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 07 05 02 04 00 18 17]; | |
| qcom,mdss-dsi-v-back-porch = <0x64>; | |
| qcom,default-topology-index = <0x01>; | |
| qcom,panel-roi-alignment = <0x2d0 0x28 0x2d0 0x28 0x2d0 0x28>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x64>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@0 { | |
| qcom,partial-update-enabled = "single_roi"; | |
| qcom,mdss-dsi-panel-timings = <0x210909 0x24230808 0x8030400>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01 0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x28>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,cmd-to-video-mode-switch-commands = [39 01 00 00 00 00 03 b0 a5 00 07 01 00 00 00 00 02 01 00 39 01 00 00 00 00 06 b2 00 5d 04 80 49 15 01 00 00 00 00 02 3d 10 15 01 00 00 00 00 02 36 00 15 01 00 00 00 00 02 55 0c]; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = <0x29010000 0x2b0 0x3050100 0xa0001 0x150100 0xa0002 0x3a773901 0xa00 0x52a0000 0x4ff3901 0xa00 0x52b0000 0x59f1501 0xa00 0x2350039 0x100000a 0x34400 0x150100 0xa0002 0x51ff1501 0xa00 0x2532415 0x100000a 0x25500 0x5010000 0x78000111 0x5010000 0x10000129>; | |
| qcom,mdss-dsi-h-front-porch = <0x78>; | |
| qcom,mdss-dsc-slice-width = <0x2d0>; | |
| qcom,mdss-dsi-h-back-porch = <0x64>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x28>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x5a0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x28>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 07 05 02 04 00 18 17]; | |
| qcom,mdss-dsi-v-back-porch = <0x64>; | |
| qcom,default-topology-index = <0x01>; | |
| qcom,panel-roi-alignment = <0x2d0 0x28 0x2d0 0x28 0x2d0 0x28>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-cmd-mode; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x64>; | |
| qcom,cmd-to-video-mode-switch-commands-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_sw43404_amoled_wqhd_video { | |
| qcom,adjust-timer-wakeup-ms = <0x01>; | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-panel-status-read-length = <0x01>; | |
| qcom,mdss-dsi-panel-name = "sw43404 amoled video mode dsi boe panel with DSC"; | |
| qcom,mdss-dsi-min-refresh-rate = <0x37>; | |
| qcom,esd-check-enabled; | |
| qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0\0src_byte_clk0\0src_pixel_clk0\0shadow_byte_clk0\0shadow_pixel_clk0"; | |
| qcom,mdss-dsi-panel-status-value = <0x9c>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-max-refresh-rate = <0x3c>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-bl-max-level = <0x3ff>; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,platform-reset-gpio = <0x66 0x4b 0x00>; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_hfp"; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,mdss-dsi-panel-test-pin = <0x66 0x2e 0x00>; | |
| qcom,mdss-dsi-pan-enable-dynamic-fps; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,dsi-dyn-clk-enable; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-physical-type = "oled"; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,dsi-dyn-clk-list = <0x1fdf1000 0x1fbd1100 0x1f9b1200>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,dsi-supported-dfps-list = <0x3c 0x39 0x37>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; | |
| phandle = <0x697>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,panel-supply-entries = <0x638>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-brightness-max-level = <0xff>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,display-topology = <0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x0c>; | |
| qcom,mdss-dsi-nolp-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-nolp-command = [05 01 00 00 00 00 02 38 00]; | |
| qcom,mdss-dsi-lp1-command = [05 01 00 00 00 00 02 39 00]; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-panel-height = <0xb40>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = <0x39010000 0x3b0 0xa5000701 0x00 0x2010039 0x1000000 0x6b200 0x5d048049 0x15010000 0x23d 0x10150100 0x02 0x36001501 0x00 0x2550839 0x1000000 0x9f800 0x810082d 0x2d39 0x100003c 0x35100 0x50100 0x500002 0x11003901 0x00 0x3b03404 0x39010000 0x5c1 0x46 0x39010000 0x3b0 0xa5000a01 0x00 0x80110000 0x8930800b 0x4005a002 0xd002d002 0xd0020002 0x6800204e 0xa8000a00 0xc002300 0x1c180010 0xf0030c20 0x60b0b 0x330e1c2a 0x38465462 0x69707779 0x7b7d7e01 0x2010009 0x4009be19 0xfc19fa19 0xf81a381a 0x781ab62a 0xf62b342b 0x743b746b 0xf4000000 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x390100 0x03 0xb0a50015 0x1000000 0x2e018 0x39010000 0xcc0 0x536f51 0x5051344f 0x5a331905 0x1000078 0x22900>; | |
| qcom,mdss-dsi-h-front-porch = <0x0a>; | |
| qcom,mdss-dsc-slice-width = <0x2d0>; | |
| qcom,mdss-dsi-h-back-porch = <0x0a>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-lp1-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsc-slice-height = <0xb4>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x5a0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 1f 1e 05 05 03 02 04 00 12 15]; | |
| qcom,mdss-dsi-v-back-porch = <0x0a>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x02>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x0a>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_ext_bridge_1080p { | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-panel-name = "ext video mode dsi bridge"; | |
| qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0"; | |
| qcom,mdss-dsi-t-clk-post = <0x03>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-ext-bridge-mode; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-force-clock-lane-hs; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-t-clk-pre = <0x24>; | |
| phandle = <0x6db>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_pulse"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,display-topology = <0x01 0x00 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x2c>; | |
| qcom,mdss-dsi-panel-height = <0x438>; | |
| qcom,mdss-dsi-h-front-porch = <0x58>; | |
| qcom,mdss-dsi-h-back-porch = <0x94>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x780>; | |
| qcom,mdss-dsi-v-pulse-width = <0x05>; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 08 05 02 04 00 19 17]; | |
| qcom,mdss-dsi-v-back-porch = <0x24>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-v-front-porch = <0x04>; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_sharp_qsync_wqhd_video { | |
| qcom,adjust-timer-wakeup-ms = <0x01>; | |
| qcom,dsi-phy-num = <0x00 0x01>; | |
| qcom,mdss-pan-physical-width-dimension = <0x4a>; | |
| qcom,mdss-dsi-panel-name = "Sharp 2k video mode qsync dsi panel"; | |
| qcom,mdss-pan-physical-height-dimension = <0x86>; | |
| qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0"; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00 0x01>; | |
| qcom,mdss-dsi-panel-blackness-level = <0x1361>; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x626b50>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| phandle = <0x6d5>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x08>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = <0x39010000 0x2ff 0xd0390100 0x02 0x75403901 0x1000 0x2f14039 0x1000000 0x2ff10 0x39010000 0x1000062c 0x1020408 0x10390100 0x02 0xffd03901 0x00 0x2750039 0x1000010 0x2f100 0x39010000 0x2ff 0x10390100 0x02 0xfb013901 0x00 0x2ba0339 0x1000000 0x2bc08 0x39010000 0x2c0 0x83390100 0x11 0xc1892800 0x8020002 0x6800d500 0xa0db709 0x89390100 0x03 0xc210f039 0x1000000 0x2d500 0x39010000 0x2d6 0x390100 0x02 0xde003901 0x00 0x2e10039 0x1000000 0x2e501 0x39010000 0x2bb 0x3390100 0x02 0xf6703901 0x00 0x2f78039 0x1000000 0x5be00 0x10001039 0x1000000 0x23500 0x39010000 0x244 0x390100 0x02 0xff203901 0x00 0x2fb0139 0x1000000 0x28702 0x39010000 0x25d 0x390100 0x02 0x5e143901 0x00 0x25feb39 0x1000000 0x2ff26 0x39010000 0x2fb 0x1390100 0x02 0x60003901 0x00 0x2620139 0x1000000 0x24000 0x39010000 0x2ff 0x28390100 0x02 0xfb013901 0x00 0x2910239 0x1000000 0x2ffe0 0x39010000 0x2fb 0x1390100 0x02 0x48813901 0x00 0x28e0939 0x1000000 0x2fff0 0x39010000 0x2fb 0x1390100 0x02 0x33203901 0x00 0x2343539 0x1000000 0x2ff10 0x5010000 0x78000111 0x5010000 0x78000129>; | |
| qcom,mdss-dsi-h-front-porch = <0x50>; | |
| qcom,mdss-dsc-slice-width = <0x2d0>; | |
| qcom,mdss-dsi-h-back-porch = <0x0c>; | |
| qcom,mdss-dsc-slice-height = <0x08>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1f 06 06 03 02 04 00 13 15]; | |
| qcom,mdss-dsi-v-back-porch = <0x0e>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bc 00 05 01 00 00 10 00 01 28 05 01 00 00 32 00 01 10]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0xa30>; | |
| qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_ext_bridge_4k_video { | |
| qcom,dsi-phy-num = <0x00 0x01>; | |
| qcom,mdss-dsi-panel-name = "ext 4k video mode dsi bridge"; | |
| qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0"; | |
| qcom,mdss-dsi-t-clk-post = <0x1e>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00 0x01>; | |
| qcom,mdss-dsi-ext-bridge-mode; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-force-clock-lane-hs; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-t-clk-pre = <0x2e>; | |
| phandle = <0x6dc>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_pulse"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,display-topology = <0x02 0x00 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x2c>; | |
| qcom,mdss-dsi-panel-height = <0x870>; | |
| qcom,mdss-dsi-h-front-porch = <0x58>; | |
| qcom,mdss-dsi-h-back-porch = <0xc8>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x780>; | |
| qcom,mdss-dsi-v-pulse-width = <0x0a>; | |
| qcom,mdss-dsi-panel-phy-timings = [00 3a 0f 0f 2e 2b 0f 10 0b 02 04 00 2e 1e]; | |
| qcom,mdss-dsi-v-back-porch = <0x48>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_dual_sim_dsc_375_cmd { | |
| qcom,ulps-enabled; | |
| qcom,dsi-phy-num = <0x00 0x01>; | |
| qcom,mdss-dsi-panel-name = "Sim dual cmd mode DSC 3.75:1 dsi panel"; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,panel-ack-disabled; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00 0x01>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-hor-line-idle = <0x00 0x28 0x100 0x28 0x78 0x80 0x78 0xf0 0x40>; | |
| qcom,platform-reset-gpio = <0x66 0x4b 0x00>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,cmd-sync-wait-broadcast; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-te-using-wd; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| phandle = <0x641>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,panel-supply-entries = <0x638>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@15 { | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x5a>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-panel-height = <0x500>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 01 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29]; | |
| qcom,mdss-dsi-h-front-porch = <0x1e>; | |
| qcom,mdss-dsc-slice-width = <0x168>; | |
| qcom,mdss-dsi-h-back-porch = <0x64>; | |
| qcom,mdss-dsc-slice-height = <0x20>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x168>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 0a 02 02 1c 1c 02 02 01 02 04 00 0b 12]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@7 { | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x78>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 01 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29]; | |
| qcom,mdss-dsi-h-front-porch = <0x1e>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x64>; | |
| qcom,mdss-dsc-slice-height = <0x20>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x21c>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 11 04 04 1e 1e 04 04 02 02 04 00 10 14]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@13 { | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x1e>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-panel-height = <0x500>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 01 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29]; | |
| qcom,mdss-dsi-h-front-porch = <0x1e>; | |
| qcom,mdss-dsc-slice-width = <0x168>; | |
| qcom,mdss-dsi-h-back-porch = <0x64>; | |
| qcom,mdss-dsc-slice-height = <0x20>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x168>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [03 07 00 01 1a 1a 01 01 00 02 04 00 08 11]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@5 { | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 01 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29]; | |
| qcom,mdss-dsi-h-front-porch = <0x1e>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x64>; | |
| qcom,mdss-dsc-slice-height = <0x20>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x21c>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 1c 1c 03 02 01 02 04 00 0c 12]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@11 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x78>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 55 15 01 00 00 00 00 02 02 45 15 01 00 00 00 00 02 05 40 15 01 00 00 00 00 02 06 19 15 01 00 00 00 00 02 07 1e 15 01 00 00 00 00 02 0b 73 15 01 00 00 00 00 02 0c 73 15 01 00 00 00 00 02 0e b0 15 01 00 00 00 00 02 0f ae 15 01 00 00 00 00 02 11 b8 15 01 00 00 00 00 02 13 00 15 01 00 00 00 00 02 58 80 15 01 00 00 00 00 02 59 01 15 01 00 00 00 00 02 5a 00 15 01 00 00 00 00 02 5b 01 15 01 00 00 00 00 02 5c 80 15 01 00 00 00 00 02 5d 81 15 01 00 00 00 00 02 5e 00 15 01 00 00 00 00 02 5f 01 15 01 00 00 00 00 02 72 31 15 01 00 00 00 00 02 68 03 15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 1c 15 01 00 00 00 00 02 01 0b 15 01 00 00 00 00 02 02 0c 15 01 00 00 00 00 02 03 01 15 01 00 00 00 00 02 04 0f 15 01 00 00 00 00 02 05 10 15 01 00 00 00 00 02 06 10 15 01 00 00 00 00 02 07 10 15 01 00 00 00 00 02 08 89 15 01 00 00 00 00 02 09 8a 15 01 00 00 00 00 02 0a 13 15 01 00 00 00 00 02 0b 13 15 01 00 00 00 00 02 0c 15 15 01 00 00 00 00 02 0d 15 15 01 00 00 00 00 02 0e 17 15 01 00 00 00 00 02 0f 17 15 01 00 00 00 00 02 10 1c 15 01 00 00 00 00 02 11 0b 15 01 00 00 00 00 02 12 0c 15 01 00 00 00 00 02 13 01 15 01 00 00 00 00 02 14 0f 15 01 00 00 00 00 02 15 10 15 01 00 00 00 00 02 16 10 15 01 00 00 00 00 02 17 10 15 01 00 00 00 00 02 18 89 15 01 00 00 00 00 02 19 8a 15 01 00 00 00 00 02 1a 13 15 01 00 00 00 00 02 1b 13 15 01 00 00 00 00 02 1c 15 15 01 00 00 00 00 02 1d 15 15 01 00 00 00 00 02 1e 17 15 01 00 00 00 00 02 1f 17 15 01 00 00 00 00 02 20 40 15 01 00 00 00 00 02 21 01 15 01 00 00 00 00 02 22 00 15 01 00 00 00 00 02 23 40 15 01 00 00 00 00 02 24 40 15 01 00 00 00 00 02 25 6d 15 01 00 00 00 00 02 26 40 15 01 00 00 00 00 02 27 40 15 01 00 00 00 00 02 e0 00 15 01 00 00 00 00 02 dc 21 15 01 00 00 00 00 02 dd 22 15 01 00 00 00 00 02 de 07 15 01 00 00 00 00 02 df 07 15 01 00 00 00 00 02 e3 6d 15 01 00 00 00 00 02 e1 07 15 01 00 00 00 00 02 e2 07 15 01 00 00 00 00 02 29 d8 15 01 00 00 00 00 02 2a 2a 15 01 00 00 00 00 02 4b 03 15 01 00 00 00 00 02 4c 11 15 01 00 00 00 00 02 4d 10 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 4f 01 15 01 00 00 00 00 02 50 10 15 01 00 00 00 00 02 51 00 15 01 00 00 00 00 02 52 80 15 01 00 00 00 00 02 53 00 15 01 00 00 00 00 02 56 00 15 01 00 00 00 00 02 54 07 15 01 00 00 00 00 02 58 07 15 01 00 00 00 00 02 55 25 15 01 00 00 00 00 02 5b 43 15 01 00 00 00 00 02 5c 00 15 01 00 00 00 00 02 5f 73 15 01 00 00 00 00 02 60 73 15 01 00 00 00 00 02 63 22 15 01 00 00 00 00 02 64 00 15 01 00 00 00 00 02 67 08 15 01 00 00 00 00 02 68 04 15 01 00 00 00 00 02 72 02 15 01 00 00 00 00 02 7a 80 15 01 00 00 00 00 02 7b 91 15 01 00 00 00 00 02 7c d8 15 01 00 00 00 00 02 7d 60 15 01 00 00 00 00 02 7f 15 15 01 00 00 00 00 02 75 15 15 01 00 00 00 00 02 b3 c0 15 01 00 00 00 00 02 b4 00 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 78 00 15 01 00 00 00 00 02 79 00 15 01 00 00 00 00 02 80 00 15 01 00 00 00 00 02 83 00 15 01 00 00 00 00 02 93 0a 15 01 00 00 00 00 02 94 0a 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 9b ff 15 01 00 00 00 00 02 9d b0 15 01 00 00 00 00 02 9f 63 15 01 00 00 00 00 02 98 10 15 01 00 00 00 00 02 ec 00 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 04 3b 03 0a 0a 15 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 e5 01 15 01 00 00 00 00 02 bb 10 15 01 00 00 00 00 02 fb 01 05 01 00 00 78 00 02 11 00 05 01 00 00 78 00 02 29 00]; | |
| qcom,mdss-dsi-h-front-porch = <0x64>; | |
| qcom,mdss-dsc-slice-width = <0x2d0>; | |
| qcom,mdss-dsi-h-back-porch = <0x20>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x10>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 21 20 07 06 04 02 04 00 15 16]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@3 { | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x78>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-panel-height = <0xf00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 01 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29]; | |
| qcom,mdss-dsi-h-front-porch = <0x1e>; | |
| qcom,mdss-dsc-slice-width = <0x438>; | |
| qcom,mdss-dsi-h-back-porch = <0x64>; | |
| qcom,mdss-dsc-slice-height = <0x20>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 2c 0c 0c 29 27 0c 0c 08 02 04 00 24 1b]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@1 { | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-panel-height = <0xf00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 01 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29]; | |
| qcom,mdss-dsi-h-front-porch = <0x1e>; | |
| qcom,mdss-dsc-slice-width = <0x438>; | |
| qcom,mdss-dsi-h-back-porch = <0x64>; | |
| qcom,mdss-dsc-slice-height = <0x20>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 21 20 06 06 04 02 04 00 15 16]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@16 { | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x78>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-panel-height = <0x500>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 01 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29]; | |
| qcom,mdss-dsi-h-front-porch = <0x1e>; | |
| qcom,mdss-dsc-slice-width = <0x168>; | |
| qcom,mdss-dsi-h-back-porch = <0x64>; | |
| qcom,mdss-dsc-slice-height = <0x20>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x168>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 1c 1c 03 03 01 02 04 00 0c 12]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@8 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x1e>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 55 15 01 00 00 00 00 02 02 45 15 01 00 00 00 00 02 05 40 15 01 00 00 00 00 02 06 19 15 01 00 00 00 00 02 07 1e 15 01 00 00 00 00 02 0b 73 15 01 00 00 00 00 02 0c 73 15 01 00 00 00 00 02 0e b0 15 01 00 00 00 00 02 0f ae 15 01 00 00 00 00 02 11 b8 15 01 00 00 00 00 02 13 00 15 01 00 00 00 00 02 58 80 15 01 00 00 00 00 02 59 01 15 01 00 00 00 00 02 5a 00 15 01 00 00 00 00 02 5b 01 15 01 00 00 00 00 02 5c 80 15 01 00 00 00 00 02 5d 81 15 01 00 00 00 00 02 5e 00 15 01 00 00 00 00 02 5f 01 15 01 00 00 00 00 02 72 31 15 01 00 00 00 00 02 68 03 15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 1c 15 01 00 00 00 00 02 01 0b 15 01 00 00 00 00 02 02 0c 15 01 00 00 00 00 02 03 01 15 01 00 00 00 00 02 04 0f 15 01 00 00 00 00 02 05 10 15 01 00 00 00 00 02 06 10 15 01 00 00 00 00 02 07 10 15 01 00 00 00 00 02 08 89 15 01 00 00 00 00 02 09 8a 15 01 00 00 00 00 02 0a 13 15 01 00 00 00 00 02 0b 13 15 01 00 00 00 00 02 0c 15 15 01 00 00 00 00 02 0d 15 15 01 00 00 00 00 02 0e 17 15 01 00 00 00 00 02 0f 17 15 01 00 00 00 00 02 10 1c 15 01 00 00 00 00 02 11 0b 15 01 00 00 00 00 02 12 0c 15 01 00 00 00 00 02 13 01 15 01 00 00 00 00 02 14 0f 15 01 00 00 00 00 02 15 10 15 01 00 00 00 00 02 16 10 15 01 00 00 00 00 02 17 10 15 01 00 00 00 00 02 18 89 15 01 00 00 00 00 02 19 8a 15 01 00 00 00 00 02 1a 13 15 01 00 00 00 00 02 1b 13 15 01 00 00 00 00 02 1c 15 15 01 00 00 00 00 02 1d 15 15 01 00 00 00 00 02 1e 17 15 01 00 00 00 00 02 1f 17 15 01 00 00 00 00 02 20 40 15 01 00 00 00 00 02 21 01 15 01 00 00 00 00 02 22 00 15 01 00 00 00 00 02 23 40 15 01 00 00 00 00 02 24 40 15 01 00 00 00 00 02 25 6d 15 01 00 00 00 00 02 26 40 15 01 00 00 00 00 02 27 40 15 01 00 00 00 00 02 e0 00 15 01 00 00 00 00 02 dc 21 15 01 00 00 00 00 02 dd 22 15 01 00 00 00 00 02 de 07 15 01 00 00 00 00 02 df 07 15 01 00 00 00 00 02 e3 6d 15 01 00 00 00 00 02 e1 07 15 01 00 00 00 00 02 e2 07 15 01 00 00 00 00 02 29 d8 15 01 00 00 00 00 02 2a 2a 15 01 00 00 00 00 02 4b 03 15 01 00 00 00 00 02 4c 11 15 01 00 00 00 00 02 4d 10 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 4f 01 15 01 00 00 00 00 02 50 10 15 01 00 00 00 00 02 51 00 15 01 00 00 00 00 02 52 80 15 01 00 00 00 00 02 53 00 15 01 00 00 00 00 02 56 00 15 01 00 00 00 00 02 54 07 15 01 00 00 00 00 02 58 07 15 01 00 00 00 00 02 55 25 15 01 00 00 00 00 02 5b 43 15 01 00 00 00 00 02 5c 00 15 01 00 00 00 00 02 5f 73 15 01 00 00 00 00 02 60 73 15 01 00 00 00 00 02 63 22 15 01 00 00 00 00 02 64 00 15 01 00 00 00 00 02 67 08 15 01 00 00 00 00 02 68 04 15 01 00 00 00 00 02 72 02 15 01 00 00 00 00 02 7a 80 15 01 00 00 00 00 02 7b 91 15 01 00 00 00 00 02 7c d8 15 01 00 00 00 00 02 7d 60 15 01 00 00 00 00 02 7f 15 15 01 00 00 00 00 02 75 15 15 01 00 00 00 00 02 b3 c0 15 01 00 00 00 00 02 b4 00 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 78 00 15 01 00 00 00 00 02 79 00 15 01 00 00 00 00 02 80 00 15 01 00 00 00 00 02 83 00 15 01 00 00 00 00 02 93 0a 15 01 00 00 00 00 02 94 0a 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 9b ff 15 01 00 00 00 00 02 9d b0 15 01 00 00 00 00 02 9f 63 15 01 00 00 00 00 02 98 10 15 01 00 00 00 00 02 ec 00 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 04 3b 03 0a 0a 15 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 e5 01 15 01 00 00 00 00 02 bb 10 15 01 00 00 00 00 02 fb 01 05 01 00 00 78 00 02 11 00 05 01 00 00 78 00 02 29 00]; | |
| qcom,mdss-dsi-h-front-porch = <0x64>; | |
| qcom,mdss-dsc-slice-width = <0x2d0>; | |
| qcom,mdss-dsi-h-back-porch = <0x20>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x10>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 0a 02 02 1c 1c 02 02 01 02 04 00 0b 12]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@14 { | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-panel-height = <0x500>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 01 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29]; | |
| qcom,mdss-dsi-h-front-porch = <0x1e>; | |
| qcom,mdss-dsc-slice-width = <0x168>; | |
| qcom,mdss-dsi-h-back-porch = <0x64>; | |
| qcom,mdss-dsc-slice-height = <0x20>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x168>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 1b 1b 01 01 01 02 04 00 0a 11]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@6 { | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x5a>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 01 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29]; | |
| qcom,mdss-dsi-h-front-porch = <0x1e>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x64>; | |
| qcom,mdss-dsc-slice-height = <0x20>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x21c>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 1e 1d 04 03 02 02 04 00 0e 13]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@12 { | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-panel-height = <0x870>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 01 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29]; | |
| qcom,mdss-dsi-h-front-porch = <0x1e>; | |
| qcom,mdss-dsc-slice-width = <0x4ec>; | |
| qcom,mdss-dsi-h-back-porch = <0x64>; | |
| qcom,mdss-dsc-slice-height = <0x438>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x9d8>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 22 21 07 07 04 02 04 00 16 16]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x02>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@4 { | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x1e>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 01 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29]; | |
| qcom,mdss-dsi-h-front-porch = <0x1e>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x64>; | |
| qcom,mdss-dsc-slice-height = <0x20>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x21c>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 1b 1b 01 01 01 02 04 00 0a 11]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@10 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x5a>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 55 15 01 00 00 00 00 02 02 45 15 01 00 00 00 00 02 05 40 15 01 00 00 00 00 02 06 19 15 01 00 00 00 00 02 07 1e 15 01 00 00 00 00 02 0b 73 15 01 00 00 00 00 02 0c 73 15 01 00 00 00 00 02 0e b0 15 01 00 00 00 00 02 0f ae 15 01 00 00 00 00 02 11 b8 15 01 00 00 00 00 02 13 00 15 01 00 00 00 00 02 58 80 15 01 00 00 00 00 02 59 01 15 01 00 00 00 00 02 5a 00 15 01 00 00 00 00 02 5b 01 15 01 00 00 00 00 02 5c 80 15 01 00 00 00 00 02 5d 81 15 01 00 00 00 00 02 5e 00 15 01 00 00 00 00 02 5f 01 15 01 00 00 00 00 02 72 31 15 01 00 00 00 00 02 68 03 15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 1c 15 01 00 00 00 00 02 01 0b 15 01 00 00 00 00 02 02 0c 15 01 00 00 00 00 02 03 01 15 01 00 00 00 00 02 04 0f 15 01 00 00 00 00 02 05 10 15 01 00 00 00 00 02 06 10 15 01 00 00 00 00 02 07 10 15 01 00 00 00 00 02 08 89 15 01 00 00 00 00 02 09 8a 15 01 00 00 00 00 02 0a 13 15 01 00 00 00 00 02 0b 13 15 01 00 00 00 00 02 0c 15 15 01 00 00 00 00 02 0d 15 15 01 00 00 00 00 02 0e 17 15 01 00 00 00 00 02 0f 17 15 01 00 00 00 00 02 10 1c 15 01 00 00 00 00 02 11 0b 15 01 00 00 00 00 02 12 0c 15 01 00 00 00 00 02 13 01 15 01 00 00 00 00 02 14 0f 15 01 00 00 00 00 02 15 10 15 01 00 00 00 00 02 16 10 15 01 00 00 00 00 02 17 10 15 01 00 00 00 00 02 18 89 15 01 00 00 00 00 02 19 8a 15 01 00 00 00 00 02 1a 13 15 01 00 00 00 00 02 1b 13 15 01 00 00 00 00 02 1c 15 15 01 00 00 00 00 02 1d 15 15 01 00 00 00 00 02 1e 17 15 01 00 00 00 00 02 1f 17 15 01 00 00 00 00 02 20 40 15 01 00 00 00 00 02 21 01 15 01 00 00 00 00 02 22 00 15 01 00 00 00 00 02 23 40 15 01 00 00 00 00 02 24 40 15 01 00 00 00 00 02 25 6d 15 01 00 00 00 00 02 26 40 15 01 00 00 00 00 02 27 40 15 01 00 00 00 00 02 e0 00 15 01 00 00 00 00 02 dc 21 15 01 00 00 00 00 02 dd 22 15 01 00 00 00 00 02 de 07 15 01 00 00 00 00 02 df 07 15 01 00 00 00 00 02 e3 6d 15 01 00 00 00 00 02 e1 07 15 01 00 00 00 00 02 e2 07 15 01 00 00 00 00 02 29 d8 15 01 00 00 00 00 02 2a 2a 15 01 00 00 00 00 02 4b 03 15 01 00 00 00 00 02 4c 11 15 01 00 00 00 00 02 4d 10 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 4f 01 15 01 00 00 00 00 02 50 10 15 01 00 00 00 00 02 51 00 15 01 00 00 00 00 02 52 80 15 01 00 00 00 00 02 53 00 15 01 00 00 00 00 02 56 00 15 01 00 00 00 00 02 54 07 15 01 00 00 00 00 02 58 07 15 01 00 00 00 00 02 55 25 15 01 00 00 00 00 02 5b 43 15 01 00 00 00 00 02 5c 00 15 01 00 00 00 00 02 5f 73 15 01 00 00 00 00 02 60 73 15 01 00 00 00 00 02 63 22 15 01 00 00 00 00 02 64 00 15 01 00 00 00 00 02 67 08 15 01 00 00 00 00 02 68 04 15 01 00 00 00 00 02 72 02 15 01 00 00 00 00 02 7a 80 15 01 00 00 00 00 02 7b 91 15 01 00 00 00 00 02 7c d8 15 01 00 00 00 00 02 7d 60 15 01 00 00 00 00 02 7f 15 15 01 00 00 00 00 02 75 15 15 01 00 00 00 00 02 b3 c0 15 01 00 00 00 00 02 b4 00 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 78 00 15 01 00 00 00 00 02 79 00 15 01 00 00 00 00 02 80 00 15 01 00 00 00 00 02 83 00 15 01 00 00 00 00 02 93 0a 15 01 00 00 00 00 02 94 0a 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 9b ff 15 01 00 00 00 00 02 9d b0 15 01 00 00 00 00 02 9f 63 15 01 00 00 00 00 02 98 10 15 01 00 00 00 00 02 ec 00 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 04 3b 03 0a 0a 15 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 e5 01 15 01 00 00 00 00 02 bb 10 15 01 00 00 00 00 02 fb 01 05 01 00 00 78 00 02 11 00 05 01 00 00 78 00 02 29 00]; | |
| qcom,mdss-dsi-h-front-porch = <0x64>; | |
| qcom,mdss-dsc-slice-width = <0x2d0>; | |
| qcom,mdss-dsi-h-back-porch = <0x20>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x10>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 1f 1f 05 05 03 02 04 00 12 15]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@2 { | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x5a>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-panel-height = <0xf00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 01 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29]; | |
| qcom,mdss-dsi-h-front-porch = <0x1e>; | |
| qcom,mdss-dsc-slice-width = <0x438>; | |
| qcom,mdss-dsi-h-back-porch = <0x64>; | |
| qcom,mdss-dsc-slice-height = <0x20>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 25 23 09 09 06 02 04 00 1c 19]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@0 { | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x1e>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-panel-height = <0xf00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 01 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29]; | |
| qcom,mdss-dsi-h-front-porch = <0x1e>; | |
| qcom,mdss-dsc-slice-width = <0x438>; | |
| qcom,mdss-dsi-h-back-porch = <0x64>; | |
| qcom,mdss-dsc-slice-height = <0x20>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 1e 1d 04 04 02 02 04 00 0e 13]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@17 { | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x90>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 01 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29]; | |
| qcom,mdss-dsi-h-front-porch = <0x1e>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x64>; | |
| qcom,mdss-dsc-slice-height = <0x20>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x21c>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 1f 1e 05 05 03 02 04 00 12 14]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@9 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 55 15 01 00 00 00 00 02 02 45 15 01 00 00 00 00 02 05 40 15 01 00 00 00 00 02 06 19 15 01 00 00 00 00 02 07 1e 15 01 00 00 00 00 02 0b 73 15 01 00 00 00 00 02 0c 73 15 01 00 00 00 00 02 0e b0 15 01 00 00 00 00 02 0f ae 15 01 00 00 00 00 02 11 b8 15 01 00 00 00 00 02 13 00 15 01 00 00 00 00 02 58 80 15 01 00 00 00 00 02 59 01 15 01 00 00 00 00 02 5a 00 15 01 00 00 00 00 02 5b 01 15 01 00 00 00 00 02 5c 80 15 01 00 00 00 00 02 5d 81 15 01 00 00 00 00 02 5e 00 15 01 00 00 00 00 02 5f 01 15 01 00 00 00 00 02 72 31 15 01 00 00 00 00 02 68 03 15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 1c 15 01 00 00 00 00 02 01 0b 15 01 00 00 00 00 02 02 0c 15 01 00 00 00 00 02 03 01 15 01 00 00 00 00 02 04 0f 15 01 00 00 00 00 02 05 10 15 01 00 00 00 00 02 06 10 15 01 00 00 00 00 02 07 10 15 01 00 00 00 00 02 08 89 15 01 00 00 00 00 02 09 8a 15 01 00 00 00 00 02 0a 13 15 01 00 00 00 00 02 0b 13 15 01 00 00 00 00 02 0c 15 15 01 00 00 00 00 02 0d 15 15 01 00 00 00 00 02 0e 17 15 01 00 00 00 00 02 0f 17 15 01 00 00 00 00 02 10 1c 15 01 00 00 00 00 02 11 0b 15 01 00 00 00 00 02 12 0c 15 01 00 00 00 00 02 13 01 15 01 00 00 00 00 02 14 0f 15 01 00 00 00 00 02 15 10 15 01 00 00 00 00 02 16 10 15 01 00 00 00 00 02 17 10 15 01 00 00 00 00 02 18 89 15 01 00 00 00 00 02 19 8a 15 01 00 00 00 00 02 1a 13 15 01 00 00 00 00 02 1b 13 15 01 00 00 00 00 02 1c 15 15 01 00 00 00 00 02 1d 15 15 01 00 00 00 00 02 1e 17 15 01 00 00 00 00 02 1f 17 15 01 00 00 00 00 02 20 40 15 01 00 00 00 00 02 21 01 15 01 00 00 00 00 02 22 00 15 01 00 00 00 00 02 23 40 15 01 00 00 00 00 02 24 40 15 01 00 00 00 00 02 25 6d 15 01 00 00 00 00 02 26 40 15 01 00 00 00 00 02 27 40 15 01 00 00 00 00 02 e0 00 15 01 00 00 00 00 02 dc 21 15 01 00 00 00 00 02 dd 22 15 01 00 00 00 00 02 de 07 15 01 00 00 00 00 02 df 07 15 01 00 00 00 00 02 e3 6d 15 01 00 00 00 00 02 e1 07 15 01 00 00 00 00 02 e2 07 15 01 00 00 00 00 02 29 d8 15 01 00 00 00 00 02 2a 2a 15 01 00 00 00 00 02 4b 03 15 01 00 00 00 00 02 4c 11 15 01 00 00 00 00 02 4d 10 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 4f 01 15 01 00 00 00 00 02 50 10 15 01 00 00 00 00 02 51 00 15 01 00 00 00 00 02 52 80 15 01 00 00 00 00 02 53 00 15 01 00 00 00 00 02 56 00 15 01 00 00 00 00 02 54 07 15 01 00 00 00 00 02 58 07 15 01 00 00 00 00 02 55 25 15 01 00 00 00 00 02 5b 43 15 01 00 00 00 00 02 5c 00 15 01 00 00 00 00 02 5f 73 15 01 00 00 00 00 02 60 73 15 01 00 00 00 00 02 63 22 15 01 00 00 00 00 02 64 00 15 01 00 00 00 00 02 67 08 15 01 00 00 00 00 02 68 04 15 01 00 00 00 00 02 72 02 15 01 00 00 00 00 02 7a 80 15 01 00 00 00 00 02 7b 91 15 01 00 00 00 00 02 7c d8 15 01 00 00 00 00 02 7d 60 15 01 00 00 00 00 02 7f 15 15 01 00 00 00 00 02 75 15 15 01 00 00 00 00 02 b3 c0 15 01 00 00 00 00 02 b4 00 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 78 00 15 01 00 00 00 00 02 79 00 15 01 00 00 00 00 02 80 00 15 01 00 00 00 00 02 83 00 15 01 00 00 00 00 02 93 0a 15 01 00 00 00 00 02 94 0a 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 9b ff 15 01 00 00 00 00 02 9d b0 15 01 00 00 00 00 02 9f 63 15 01 00 00 00 00 02 98 10 15 01 00 00 00 00 02 ec 00 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 04 3b 03 0a 0a 15 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 e5 01 15 01 00 00 00 00 02 bb 10 15 01 00 00 00 00 02 fb 01 05 01 00 00 78 00 02 11 00 05 01 00 00 78 00 02 29 00]; | |
| qcom,mdss-dsi-h-front-porch = <0x64>; | |
| qcom,mdss-dsc-slice-width = <0x2d0>; | |
| qcom,mdss-dsi-h-back-porch = <0x20>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x10>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 1e 1d 04 04 02 02 04 00 0f 13]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_sw43404_fhd_plus_cmd { | |
| qcom,ulps-enabled; | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-pan-physical-width-dimension = <0x44>; | |
| qcom,mdss-dsi-panel-status-read-length = <0x01>; | |
| qcom,mdss-dsi-panel-name = "sw43404 amoled boe fhd+ panel with DSC"; | |
| qcom,mdss-pan-physical-height-dimension = <0x8a>; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0"; | |
| qcom,mdss-dsi-panel-status-value = <0x9c>; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-bl-max-level = <0x3ff>; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,platform-reset-gpio = <0x66 0x4b 0x00>; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,mdss-dsi-panel-test-pin = <0x66 0x2e 0x00>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-physical-type = "oled"; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| phandle = <0x698>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,panel-supply-entries = <0x638>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,mdss-dsi-lane-map = "lane_map_0123"; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,platform-te-gpio = <0x66 0x42 0x00>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-brightness-max-level = <0xff>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,partial-update-enabled = "single_roi"; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x02 0x02 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| qcom,mdss-dsi-panel-jitter = <0x03 0x01>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-panel-height = <0x870>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 03 b0 a5 00 07 01 00 00 00 00 02 01 00 0a 01 00 00 00 00 80 11 00 00 89 30 80 08 70 04 38 02 1c 02 1c 02 1c 02 00 02 0e 00 20 34 29 00 07 00 0c 00 2e 00 31 18 00 10 f0 03 0c 20 00 06 0b 0b 33 0e 1c 2a 38 46 54 62 69 70 77 79 7b 7d 7e 01 02 01 00 09 40 09 be 19 fc 19 fa 19 f8 1a 38 1a 78 1a b6 2a f6 2b 34 2b 74 3b 74 6b f4 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 39 01 00 00 00 00 03 b0 a5 00 15 01 00 00 00 00 02 5e 10 39 01 00 00 00 00 06 b9 bf 11 40 00 30 39 01 00 00 00 00 09 f8 00 08 10 08 2d 00 00 2d 15 01 00 00 00 00 02 55 08 05 01 00 00 1e 00 02 11 00 15 01 00 00 78 00 02 3d 01 39 01 00 00 00 00 03 b0 a5 00 05 01 00 00 78 00 02 35 00 05 01 00 00 3c 00 02 29 00]; | |
| qcom,mdss-dsi-h-front-porch = <0xa0>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x48>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x10e>; | |
| qcom,mdss-dsi-panel-clockrate = <0x17d78400>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 12 04 04 1e 1e 04 05 02 03 04 00 11 14]; | |
| qcom,mdss-dsi-v-back-porch = <0x08>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,panel-roi-alignment = <0x21c 0x10e 0x10e 0x10e 0x438 0x10e>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_sim_video { | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-panel-name = "Simulator video mode dsi panel"; | |
| qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,panel-ack-disabled; | |
| qcom,mdss-dsi-t-clk-post = <0x04>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,platform-reset-gpio = <0x66 0x4b 0x00>; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x00 0x00 0x00 0x01 0x00>; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-t-clk-pre = <0x1b>; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| phandle = <0x6de>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,panel-supply-entries = <0x638>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-panel-timings = <0x00 0x00 0x00>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x01 0x00 0x01 0x02 0x00 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x08>; | |
| qcom,mdss-dsi-panel-height = <0x1e0>; | |
| qcom,mdss-dsi-on-command = [32 01 00 00 00 00 02 00 00]; | |
| qcom,mdss-dsi-h-front-porch = <0x08>; | |
| qcom,mdss-dsi-h-back-porch = <0x08>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x280>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 07 05 02 04 00 18 17]; | |
| qcom,mdss-dsi-v-back-porch = <0x06>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [22 01 00 00 00 00 02 00 00]; | |
| qcom,mdss-dsi-v-front-porch = <0x06>; | |
| qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,platform-supply-entries { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,platform-supply-entry@0 { | |
| qcom,supply-disable-load = <0x00>; | |
| qcom,supply-enable-load = <0x00>; | |
| qcom,supply-name = "mmcx"; | |
| qcom,supply-max-voltage = <0x00>; | |
| reg = <0x00>; | |
| qcom,supply-min-voltage = <0x00>; | |
| }; | |
| }; | |
| qcom,sde-reg-bus { | |
| qcom,msm-bus,name = "mdss_reg"; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x04>; | |
| qcom,msm-bus,vectors-KBps = <0x01 0x24e 0x00 0x00 0x01 0x24e 0x00 0x12c00 0x01 0x24e 0x00 0x249f0 0x01 0x24e 0x00 0x493e0>; | |
| }; | |
| qcom,sde-limits { | |
| qcom,sde-bw-limits { | |
| qcom,sde-limit-ids = <0x01 0x02 0x04 0x08 0x10>; | |
| qcom,sde-limit-cases = "per_vig_pipe\0per_dma_pipe\0total_max_bw\0camera_concurrency\0cwb_concurrency"; | |
| qcom,sde-limit-name = "sde_bwlimit_usecases"; | |
| qcom,sde-limit-values = <0x01 0x50df20 0x11 0x50df20 0x09 0x432380 0x19 0x432380 0x02 0x50df20 0x12 0x50df20 0x0a 0x432380 0x1a 0x432380 0x04 0xfd4bc0 0x14 0xfd4bc0 0x0c 0xd10ba0 0x1c 0xd10ba0>; | |
| }; | |
| qcom,sde-linewidth-limits { | |
| qcom,sde-limit-ids = <0x01 0x02 0x04 0x08>; | |
| qcom,sde-limit-cases = "vig\0dma\0scale\0inline_rot"; | |
| qcom,sde-limit-name = "sspp_linewidth_usecases"; | |
| qcom,sde-limit-values = <0x01 0x1000 0x05 0xa00 0x02 0x1000 0x09 0x440>; | |
| }; | |
| }; | |
| qcom,mdss_dsi_dual_sim_cmd { | |
| qcom,ulps-enabled; | |
| qcom,dsi-phy-num = <0x00 0x01>; | |
| qcom,mdss-dsi-panel-name = "Sim dual cmd mode dsi panel"; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,panel-ack-disabled; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00 0x01>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-hor-line-idle = <0x00 0x28 0x100 0x28 0x78 0x80 0x78 0xf0 0x40>; | |
| qcom,mdss-dsi-qsync-min-refresh-rate = <0x2d>; | |
| qcom,platform-reset-gpio = <0x66 0x4b 0x00>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,cmd-sync-wait-broadcast; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-te-using-wd; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| phandle = <0x6e1>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,panel-supply-entries = <0x638>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@1 { | |
| qcom,mdss-dsi-qsync-off-commands = [15 01 00 00 00 00 02 51 00]; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x02 0x00 0x02 0x01 0x00 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| qcom,mdss-dsi-qsync-on-commands = [15 01 00 00 00 00 02 51 00]; | |
| qcom,mdss-dsi-panel-height = <0x5a0>; | |
| qcom,mdss-dsi-on-command = <0x5010000 0x129>; | |
| qcom,mdss-dsi-h-front-porch = <0x78>; | |
| qcom,mdss-dsi-h-back-porch = <0x2c>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsi-qsync-off-commands-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x500>; | |
| qcom,mdss-dsi-v-pulse-width = <0x04>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 07 05 02 04 00 18 17]; | |
| qcom,mdss-dsi-v-back-porch = <0x04>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 05 01 00 00 00 00 02 10 00]; | |
| qcom,mdss-dsi-qsync-on-commands-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@2 { | |
| qcom,mdss-dsi-qsync-off-commands = [15 01 00 00 00 00 02 51 00]; | |
| qcom,display-topology = <0x02 0x00 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x28>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,mdss-dsi-qsync-on-commands = [15 01 00 00 00 00 02 51 00]; | |
| qcom,mdss-dsi-panel-height = <0xf00>; | |
| qcom,mdss-dsi-on-command = <0x5010000 0x129>; | |
| qcom,mdss-dsi-h-front-porch = <0x1e>; | |
| qcom,mdss-dsi-h-back-porch = <0x64>; | |
| qcom,mdss-dsi-qsync-off-commands-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 08 05 02 04 00 19 18]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 05 01 00 00 00 00 02 10 00]; | |
| qcom,mdss-dsi-qsync-on-commands-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@0 { | |
| qcom,mdss-dsi-qsync-off-commands = [15 01 00 00 00 00 02 51 00]; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x02 0x00 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x78>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,mdss-dsi-qsync-on-commands = [15 01 00 00 00 00 02 51 00]; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsi-on-command = <0x5010000 0x129>; | |
| qcom,mdss-dsi-h-front-porch = <0x1c>; | |
| qcom,mdss-dsi-h-back-porch = <0x04>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsi-qsync-off-commands-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x21c>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 24 09 09 26 24 09 09 06 02 04 00 18 17]; | |
| qcom,mdss-dsi-v-back-porch = <0x0c>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 05 01 00 00 00 00 02 10 00]; | |
| qcom,mdss-dsi-qsync-on-commands-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-v-front-porch = <0x0c>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_rm69380_edo_amoled_cmd { | |
| qcom,adjust-timer-wakeup-ms = <0x01>; | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,dsi-phy-num = <0x00 0x01>; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-panel-status-read-length = <0x01>; | |
| qcom,mdss-dsi-panel-name = "rm69380 amoled wqxga cmd mode dsi edo panel"; | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0"; | |
| qcom,mdss-dsi-panel-status-value = <0x9c>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00 0x01>; | |
| qcom,mdss-dsi-bl-max-level = <0x7ff>; | |
| qcom,platform-en-gpio = <0x66 0x3c 0x00>; | |
| qcom,platform-reset-gpio = <0x66 0x4b 0x00>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0f 0x00 0x0a 0x01 0x1e>; | |
| qcom,dynamic-mode-switch-type = "dynamic-resolution-switch-immediate"; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,dynamic-mode-switch-enabled; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; | |
| phandle = <0x699>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,panel-supply-entries = <0x638>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,dcs-cmd-by-left; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,platform-te-gpio = <0x66 0x42 0x00>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@1 { | |
| qcom,display-topology = <0x02 0x00 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x0c>; | |
| qcom,mdss-highlight-off-command = [39 01 00 00 00 00 03 51 07 ff]; | |
| qcom,mdss-dsi-timing-switch-command-state = "dsi_hs_mode"; | |
| qcom,mdss-highlight-off-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-height = <0x640>; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 fe d4 39 01 00 00 00 00 02 00 80 39 01 00 00 00 00 02 fe d0 39 01 00 00 00 00 02 48 00 39 01 00 00 00 00 02 fe 26 39 01 00 00 00 00 02 75 3f 39 01 00 00 00 00 02 1d 1a 39 01 00 00 00 00 02 fe 40 39 01 00 00 00 00 02 bd 05 39 01 00 00 00 00 02 fe 00 39 01 00 00 00 00 02 53 28 39 01 00 00 00 00 02 c2 08 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 03 51 07 ff 05 01 00 00 14 00 02 11 00 05 01 00 00 24 00 02 29 00]; | |
| qcom,mdss-dsi-h-front-porch = <0x20>; | |
| qcom,mdss-dsi-h-back-porch = <0x26>; | |
| qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 fe 40 39 01 00 00 00 00 02 bd 05 39 01 00 00 00 00 02 fe 00]; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x500>; | |
| qcom,mdss-dsi-v-pulse-width = <0x04>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 27 0a 0a 1b 25 0a 0b 0a 02 04 00 20 0f]; | |
| qcom,mdss-dsi-v-back-porch = <0x08>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-highlight-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-highlight-on-command = [39 01 00 00 00 00 03 51 0f ff]; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 23 00 02 28 00 05 01 00 00 14 00 02 10 00]; | |
| qcom,mdss-dsi-v-front-porch = <0x14>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@0 { | |
| qcom,display-topology = <0x02 0x00 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x5a>; | |
| qcom,mdss-dsi-h-pulse-width = <0x0c>; | |
| qcom,mdss-highlight-off-command = [39 01 00 00 00 00 03 51 07 ff]; | |
| qcom,mdss-dsi-timing-switch-command-state = "dsi_hs_mode"; | |
| qcom,mdss-highlight-off-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-height = <0x640>; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 fe d4 39 01 00 00 00 00 02 00 80 39 01 00 00 00 00 02 fe d0 39 01 00 00 00 00 02 48 00 39 01 00 00 00 00 02 fe 26 39 01 00 00 00 00 02 75 3f 39 01 00 00 00 00 02 1d 1a 39 01 00 00 00 00 02 fe 00 39 01 00 00 00 00 02 53 28 39 01 00 00 00 00 02 c2 08 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 03 51 07 ff 05 01 00 00 14 00 02 11 00 05 01 00 00 24 00 02 29 00]; | |
| qcom,mdss-dsi-h-front-porch = <0x20>; | |
| qcom,mdss-dsi-h-back-porch = <0x26>; | |
| qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 fe 40 39 01 00 00 00 00 02 bd 01 39 01 00 00 00 00 02 fe 00]; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x500>; | |
| qcom,mdss-dsi-v-pulse-width = <0x04>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 27 0a 0a 1b 25 0a 0b 0a 02 04 00 20 0f]; | |
| qcom,mdss-dsi-v-back-porch = <0x08>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-highlight-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-highlight-on-command = [39 01 00 00 00 00 03 51 0f ff]; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 23 00 02 28 00 05 01 00 00 14 00 02 10 00]; | |
| qcom,mdss-dsi-v-front-porch = <0x14>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_sim_dsc_10b_cmd { | |
| qcom,ulps-enabled; | |
| qcom,adjust-timer-wakeup-ms = <0x01>; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-dsi-panel-name = "Simulator cmd mode DSC3:1 10bit dsi panel"; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,panel-ack-disabled; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,platform-reset-gpio = <0x66 0x4b 0x00>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-te-using-wd; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| phandle = <0x6e0>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,panel-supply-entries = <0x638>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-bpp = <0x1e>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@1 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01 0x02 0x02 0x01 0x02 0x01 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x00>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x0a>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = <0x15010000 0x2bb 0x10150100 0x02 0xb0030501 0x7800 0x1111501 0x00 0x251ff15 0x1000000 0x25324 0x15010000 0x2ff 0x23150100 0x02 0x8051501 0x00 0x2469015 0x1000000 0x2ff10 0x15010000 0x2ff 0xf0150100 0x02 0x92011501 0x00 0x2ff1015 0x1000000 0x23500 0x5010000 0x28000129>; | |
| qcom,mdss-dsi-h-front-porch = <0x00>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x00>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x10>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x00>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 08 05 02 04 00 19 18]; | |
| qcom,mdss-dsi-v-back-porch = <0x00>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x02>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = <0x5010000 0x10000128 0x5010000 0x40000110>; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x00>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@2 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x5a>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x0a>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = <0x15010000 0x2ff 0x20150100 0x02 0xfb011501 0x00 0x2000115 0x1000000 0x20155 0x15010000 0x202 0x45150100 0x02 0x5401501 0x00 0x2061915 0x1000000 0x2071e 0x15010000 0x20b 0x73150100 0x02 0xc731501 0x00 0x20eb015 0x1000000 0x20fae 0x15010000 0x211 0xb8150100 0x02 0x13001501 0x00 0x2588015 0x1000000 0x25901 0x15010000 0x25a 0x150100 0x02 0x5b011501 0x00 0x25c8015 0x1000000 0x25d81 0x15010000 0x25e 0x150100 0x02 0x5f011501 0x00 0x2723115 0x1000000 0x26803 0x15010000 0x2ff 0x24150100 0x02 0xfb011501 0x00 0x2001c15 0x1000000 0x2010b 0x15010000 0x202 0xc150100 0x02 0x3011501 0x00 0x2040f15 0x1000000 0x20510 0x15010000 0x206 0x10150100 0x02 0x7101501 0x00 0x2088915 0x1000000 0x2098a 0x15010000 0x20a 0x13150100 0x02 0xb131501 0x00 0x20c1515 0x1000000 0x20d15 0x15010000 0x20e 0x17150100 0x02 0xf171501 0x00 0x2101c15 0x1000000 0x2110b 0x15010000 0x212 0xc150100 0x02 0x13011501 0x00 0x2140f15 0x1000000 0x21510 0x15010000 0x216 0x10150100 0x02 0x17101501 0x00 0x2188915 0x1000000 0x2198a 0x15010000 0x21a 0x13150100 0x02 0x1b131501 0x00 0x21c1515 0x1000000 0x21d15 0x15010000 0x21e 0x17150100 0x02 0x1f171501 0x00 0x2204015 0x1000000 0x22101 0x15010000 0x222 0x150100 0x02 0x23401501 0x00 0x2244015 0x1000000 0x2256d 0x15010000 0x226 0x40150100 0x02 0x27401501 0x00 0x2e00015 0x1000000 0x2dc21 0x15010000 0x2dd 0x22150100 0x02 0xde071501 0x00 0x2df0715 0x1000000 0x2e36d 0x15010000 0x2e1 0x7150100 0x02 0xe2071501 0x00 0x229d815 0x1000000 0x22a2a 0x15010000 0x24b 0x3150100 0x02 0x4c111501 0x00 0x24d1015 0x1000000 0x24e01 0x15010000 0x24f 0x1150100 0x02 0x50101501 0x00 0x2510015 0x1000000 0x25280 0x15010000 0x253 0x150100 0x02 0x56001501 0x00 0x2540715 0x1000000 0x25807 0x15010000 0x255 0x25150100 0x02 0x5b431501 0x00 0x25c0015 0x1000000 0x25f73 0x15010000 0x260 0x73150100 0x02 0x63221501 0x00 0x2640015 0x1000000 0x26708 0x15010000 0x268 0x4150100 0x02 0x72021501 0x00 0x27a8015 0x1000000 0x27b91 0x15010000 0x27c 0xd8150100 0x02 0x7d601501 0x00 0x27f1515 0x1000000 0x27515 0x15010000 0x2b3 0xc0150100 0x02 0xb4001501 0x00 0x2b50015 0x1000000 0x27800 0x15010000 0x279 0x150100 0x02 0x80001501 0x00 0x2830015 0x1000000 0x2930a 0x15010000 0x294 0xa150100 0x02 0x8a001501 0x00 0x29bff15 0x1000000 0x29db0 0x15010000 0x29f 0x63150100 0x02 0x98101501 0x00 0x2ec0015 0x1000000 0x2ff10 0x39010000 0x11c1 0x9200010 0x2000268 0x1bb000a 0x66704c5 0x39010000 0x3c2 0x10f01501 0x00 0x2c00315 0x1000000 0x43b03 0xa0a1501 0x00 0x2350015 0x1000000 0x2e501 0x15010000 0x2bb 0x10150100 0x02 0xfb010501 0x7800 0x2110005 0x1000078 0x22900>; | |
| qcom,mdss-dsi-h-front-porch = <0x64>; | |
| qcom,mdss-dsc-slice-width = <0x2d0>; | |
| qcom,mdss-dsi-h-back-porch = <0x20>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x10>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x5a0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-on-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 07 05 02 04 00 18 17]; | |
| qcom,mdss-dsi-v-back-porch = <0x08>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x02>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x0a>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| timing@0 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x0a>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = <0x15010000 0x2ff 0x20150100 0x02 0xfb011501 0x00 0x2000115 0x1000000 0x20155 0x15010000 0x202 0x45150100 0x02 0x5401501 0x00 0x2061915 0x1000000 0x2071e 0x15010000 0x20b 0x73150100 0x02 0xc731501 0x00 0x20eb015 0x1000000 0x20fae 0x15010000 0x211 0xb8150100 0x02 0x13001501 0x00 0x2588015 0x1000000 0x25901 0x15010000 0x25a 0x150100 0x02 0x5b011501 0x00 0x25c8015 0x1000000 0x25d81 0x15010000 0x25e 0x150100 0x02 0x5f011501 0x00 0x2723115 0x1000000 0x26803 0x15010000 0x2ff 0x24150100 0x02 0xfb011501 0x00 0x2001c15 0x1000000 0x2010b 0x15010000 0x202 0xc150100 0x02 0x3011501 0x00 0x2040f15 0x1000000 0x20510 0x15010000 0x206 0x10150100 0x02 0x7101501 0x00 0x2088915 0x1000000 0x2098a 0x15010000 0x20a 0x13150100 0x02 0xb131501 0x00 0x20c1515 0x1000000 0x20d15 0x15010000 0x20e 0x17150100 0x02 0xf171501 0x00 0x2101c15 0x1000000 0x2110b 0x15010000 0x212 0xc150100 0x02 0x13011501 0x00 0x2140f15 0x1000000 0x21510 0x15010000 0x216 0x10150100 0x02 0x17101501 0x00 0x2188915 0x1000000 0x2198a 0x15010000 0x21a 0x13150100 0x02 0x1b131501 0x00 0x21c1515 0x1000000 0x21d15 0x15010000 0x21e 0x17150100 0x02 0x1f171501 0x00 0x2204015 0x1000000 0x22101 0x15010000 0x222 0x150100 0x02 0x23401501 0x00 0x2244015 0x1000000 0x2256d 0x15010000 0x226 0x40150100 0x02 0x27401501 0x00 0x2e00015 0x1000000 0x2dc21 0x15010000 0x2dd 0x22150100 0x02 0xde071501 0x00 0x2df0715 0x1000000 0x2e36d 0x15010000 0x2e1 0x7150100 0x02 0xe2071501 0x00 0x229d815 0x1000000 0x22a2a 0x15010000 0x24b 0x3150100 0x02 0x4c111501 0x00 0x24d1015 0x1000000 0x24e01 0x15010000 0x24f 0x1150100 0x02 0x50101501 0x00 0x2510015 0x1000000 0x25280 0x15010000 0x253 0x150100 0x02 0x56001501 0x00 0x2540715 0x1000000 0x25807 0x15010000 0x255 0x25150100 0x02 0x5b431501 0x00 0x25c0015 0x1000000 0x25f73 0x15010000 0x260 0x73150100 0x02 0x63221501 0x00 0x2640015 0x1000000 0x26708 0x15010000 0x268 0x4150100 0x02 0x72021501 0x00 0x27a8015 0x1000000 0x27b91 0x15010000 0x27c 0xd8150100 0x02 0x7d601501 0x00 0x27f1515 0x1000000 0x27515 0x15010000 0x2b3 0xc0150100 0x02 0xb4001501 0x00 0x2b50015 0x1000000 0x27800 0x15010000 0x279 0x150100 0x02 0x80001501 0x00 0x2830015 0x1000000 0x2930a 0x15010000 0x294 0xa150100 0x02 0x8a001501 0x00 0x29bff15 0x1000000 0x29db0 0x15010000 0x29f 0x63150100 0x02 0x98101501 0x00 0x2ec0015 0x1000000 0x2ff10 0x39010000 0x11c1 0x9200010 0x2000268 0x1bb000a 0x66704c5 0x39010000 0x3c2 0x10f01501 0x00 0x2c00315 0x1000000 0x43b03 0xa0a1501 0x00 0x2350015 0x1000000 0x2e501 0x15010000 0x2bb 0x10150100 0x02 0xfb010501 0x7800 0x2110005 0x1000078 0x22900>; | |
| qcom,mdss-dsi-h-front-porch = <0x64>; | |
| qcom,mdss-dsc-slice-width = <0x2d0>; | |
| qcom,mdss-dsi-h-back-porch = <0x20>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x10>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x5a0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-on-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 07 05 02 04 00 18 17]; | |
| qcom,mdss-dsi-v-back-porch = <0x08>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x02>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsi-v-front-porch = <0x0a>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_sharp_qsync_wqhd_cmd { | |
| qcom,adjust-timer-wakeup-ms = <0x01>; | |
| qcom,dsi-phy-num = <0x00 0x01>; | |
| qcom,mdss-pan-physical-width-dimension = <0x4a>; | |
| qcom,mdss-dsi-panel-name = "Sharp 2k cmd mode qsync dsi panel"; | |
| qcom,mdss-pan-physical-height-dimension = <0x86>; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-panel-mode-switch; | |
| qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0"; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00 0x01>; | |
| qcom,mdss-dsi-panel-blackness-level = <0x1361>; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x626b50>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-schedule-line = <0x05>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| phandle = <0x640>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@7 { | |
| qcom,partial-update-enabled = "single_roi"; | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x5a>; | |
| qcom,mdss-dsi-h-pulse-width = <0x08>; | |
| qcom,mdss-dsi-panel-jitter = <0x03 0x01>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 40 39 01 00 00 10 00 02 f1 40 39 01 00 00 00 00 02 ff 10 39 01 00 00 10 00 06 2c 01 02 04 08 10 39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 00 39 01 00 00 10 00 02 f1 00 39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 ba 03 39 01 00 00 00 00 02 bc 08 39 01 00 00 00 00 02 c0 85 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 0e 00 bb 00 07 0d b7 0c b7 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 d5 00 39 01 00 00 00 00 02 d6 00 39 01 00 00 00 00 02 de 00 39 01 00 00 00 00 02 e1 00 39 01 00 00 00 00 02 e5 01 39 01 00 00 00 00 02 bb 10 39 01 00 00 00 00 02 f6 70 39 01 00 00 00 00 02 f7 80 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 44 00 39 01 00 00 00 00 02 ff 20 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 87 02 39 01 00 00 00 00 02 5d 00 39 01 00 00 00 00 02 5e 14 39 01 00 00 00 00 02 5f eb 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 14 00 39 01 00 00 00 00 02 15 10 39 01 00 00 00 00 02 16 03 39 01 00 00 00 00 02 17 70 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 01 39 01 00 00 00 00 02 40 00 39 01 00 00 00 00 02 ff 28 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 91 02 39 01 00 00 00 00 02 ff e0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 48 81 39 01 00 00 00 00 02 8e 09 39 01 00 00 00 00 02 ff f0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 33 20 39 01 00 00 00 00 02 34 35 39 01 00 00 00 00 02 ff 10 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29]; | |
| qcom,mdss-dsi-h-front-porch = <0x50>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x0c>; | |
| qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 c0 85 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 0e 00 bb 00 07 0d b7 0c b7 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 16 03 39 01 00 00 00 00 02 17 70 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 02 15 01 00 00 00 00 02 ff 10 05 01 00 00 00 00 01 28 05 01 00 00 00 00 01 29]; | |
| qcom,mdss-dsc-slice-height = <0x08>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x21c>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 1c 1c 03 02 01 02 04 00 0c 12]; | |
| qcom,mdss-dsi-v-back-porch = <0x0e>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,panel-roi-alignment = <0x21c 0x08 0x08 0x08 0x438 0x08>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bc 00 05 01 00 00 10 00 01 28 05 01 00 00 32 00 01 10]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x10>; | |
| qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; | |
| }; | |
| timing@5 { | |
| qcom,video-to-cmd-mode-switch-commands = [39 00 00 00 00 00 02 ff 10 39 00 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 bb 10]; | |
| qcom,video-to-cmd-mode-post-switch-commands-state = "dsi_lp_mode"; | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x78>; | |
| qcom,mdss-dsi-h-pulse-width = <0x08>; | |
| qcom,video-to-cmd-mode-switch-commands-state = "dsi_lp_mode"; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-video-mode; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = <0x39010000 0x2ff 0xd0390100 0x02 0x75403901 0x1000 0x2f14039 0x1000000 0x2ff10 0x39010000 0x1000062c 0x1020408 0x10390100 0x02 0xffd03901 0x00 0x2750039 0x1000010 0x2f100 0x39010000 0x2ff 0x10390100 0x02 0xfb013901 0x00 0x2ba0339 0x1000000 0x2bc08 0x39010000 0x2c0 0x83390100 0x11 0xc1892800 0x8020002 0x6800d500 0xa0db709 0x89390100 0x03 0xc210f039 0x1000000 0x2d500 0x39010000 0x2d6 0x390100 0x02 0xde003901 0x00 0x2e10039 0x1000000 0x2e501 0x39010000 0x2bb 0x3390100 0x02 0xf6703901 0x00 0x2f78039 0x1000000 0x5be00 0x10001039 0x1000000 0x23500 0x39010000 0x244 0x390100 0x02 0xff203901 0x00 0x2fb0139 0x1000000 0x28702 0x39010000 0x25d 0x390100 0x02 0x5e143901 0x00 0x25feb39 0x1000000 0x2ff26 0x39010000 0x2fb 0x1390100 0x02 0x60003901 0x00 0x2620139 0x1000000 0x24000 0x39010000 0x2ff 0x28390100 0x02 0xfb013901 0x00 0x2910239 0x1000000 0x2ffe0 0x39010000 0x2fb 0x1390100 0x02 0x48813901 0x00 0x28e0939 0x1000000 0x2fff0 0x39010000 0x2fb 0x1390100 0x02 0x33203901 0x00 0x2343539 0x1000000 0x2ff10 0x5010000 0x78000111 0x5010000 0x78000129>; | |
| qcom,mdss-dsi-h-front-porch = <0x14>; | |
| qcom,mdss-dsc-slice-width = <0x2d0>; | |
| qcom,mdss-dsi-h-back-porch = <0x0c>; | |
| qcom,mdss-dsc-slice-height = <0x08>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1f 06 06 03 02 04 00 13 15]; | |
| qcom,mdss-dsi-v-back-porch = <0x0e>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bc 00 05 01 00 00 10 00 01 28 05 01 00 00 32 00 01 10]; | |
| qcom,video-to-cmd-mode-post-switch-commands = [39 00 00 00 00 00 02 ff 10 39 00 00 00 00 00 02 fb 01 39 00 00 00 00 00 02 bb 10 39 00 00 00 00 00 02 ff 26 39 00 00 00 00 00 02 fb 01 39 00 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x10>; | |
| qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; | |
| }; | |
| timing@3 { | |
| qcom,partial-update-enabled = "single_roi"; | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x5a>; | |
| qcom,mdss-dsi-h-pulse-width = <0x08>; | |
| qcom,mdss-dsi-panel-jitter = <0x03 0x01>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 40 39 01 00 00 10 00 02 f1 40 39 01 00 00 00 00 02 ff 10 39 01 00 00 10 00 06 2c 01 02 04 08 10 39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 00 39 01 00 00 10 00 02 f1 00 39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 ba 03 39 01 00 00 00 00 02 bc 08 39 01 00 00 00 00 02 c0 83 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 68 00 d5 00 0a 0d b7 09 89 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 d5 00 39 01 00 00 00 00 02 d6 00 39 01 00 00 00 00 02 de 00 39 01 00 00 00 00 02 e1 00 39 01 00 00 00 00 02 e5 01 39 01 00 00 00 00 02 bb 10 39 01 00 00 00 00 02 f6 70 39 01 00 00 00 00 02 f7 80 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 44 00 39 01 00 00 00 00 02 ff 20 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 87 02 39 01 00 00 00 00 02 5d 00 39 01 00 00 00 00 02 5e 14 39 01 00 00 00 00 02 5f eb 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 14 00 39 01 00 00 00 00 02 15 10 39 01 00 00 00 00 02 16 03 39 01 00 00 00 00 02 17 70 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 01 39 01 00 00 00 00 02 40 00 39 01 00 00 00 00 02 ff 28 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 91 02 39 01 00 00 00 00 02 ff e0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 48 81 39 01 00 00 00 00 02 8e 09 39 01 00 00 00 00 02 ff f0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 33 20 39 01 00 00 00 00 02 34 35 39 01 00 00 00 00 02 ff 10 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29]; | |
| qcom,mdss-dsi-h-front-porch = <0x14>; | |
| qcom,mdss-dsc-slice-width = <0x2d0>; | |
| qcom,mdss-dsi-h-back-porch = <0x0c>; | |
| qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 c0 83 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 68 00 d5 00 0a 0d b7 09 89 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 16 03 39 01 00 00 00 00 02 17 70 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 02 15 01 00 00 00 00 02 ff 10 05 01 00 00 00 00 01 28 05 01 00 00 00 00 01 29]; | |
| qcom,mdss-dsc-slice-height = <0x08>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 10 03 03 1e 1e 04 04 02 02 04 00 0f 13]; | |
| qcom,mdss-dsi-v-back-porch = <0x0e>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,panel-roi-alignment = <0x2d0 0x08 0x08 0x08 0x5a0 0x08>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bc 00 05 01 00 00 10 00 01 28 05 01 00 00 32 00 01 10]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x10>; | |
| qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; | |
| }; | |
| timing@1 { | |
| qcom,video-to-cmd-mode-switch-commands = [39 00 00 00 00 00 02 ff 10 39 00 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 bb 10]; | |
| qcom,video-to-cmd-mode-post-switch-commands-state = "dsi_lp_mode"; | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x08>; | |
| qcom,video-to-cmd-mode-switch-commands-state = "dsi_lp_mode"; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-video-mode; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = <0x39010000 0x2ff 0xd0390100 0x02 0x75403901 0x1000 0x2f14039 0x1000000 0x2ff10 0x39010000 0x1000062c 0x1020408 0x10390100 0x02 0xffd03901 0x00 0x2750039 0x1000010 0x2f100 0x39010000 0x2ff 0x10390100 0x02 0xfb013901 0x00 0x2ba0339 0x1000000 0x2bc08 0x39010000 0x2c0 0x83390100 0x11 0xc1892800 0x8020002 0x6800d500 0xa0db709 0x89390100 0x03 0xc210f039 0x1000000 0x2d500 0x39010000 0x2d6 0x390100 0x02 0xde003901 0x00 0x2e10039 0x1000000 0x2e501 0x39010000 0x2bb 0x3390100 0x02 0xf6703901 0x00 0x2f78039 0x1000000 0x5be00 0x10001039 0x1000000 0x23500 0x39010000 0x244 0x390100 0x02 0xff203901 0x00 0x2fb0139 0x1000000 0x28702 0x39010000 0x25d 0x390100 0x02 0x5e143901 0x00 0x25feb39 0x1000000 0x2ff26 0x39010000 0x2fb 0x1390100 0x02 0x60003901 0x00 0x2620139 0x1000000 0x24000 0x39010000 0x2ff 0x28390100 0x02 0xfb013901 0x00 0x2910239 0x1000000 0x2ffe0 0x39010000 0x2fb 0x1390100 0x02 0x48813901 0x00 0x28e0939 0x1000000 0x2fff0 0x39010000 0x2fb 0x1390100 0x02 0x33203901 0x00 0x2343539 0x1000000 0x2ff10 0x5010000 0x78000111 0x5010000 0x78000129>; | |
| qcom,mdss-dsi-h-front-porch = <0x50>; | |
| qcom,mdss-dsc-slice-width = <0x2d0>; | |
| qcom,mdss-dsi-h-back-porch = <0x0c>; | |
| qcom,mdss-dsc-slice-height = <0x08>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1f 06 06 03 02 04 00 13 15]; | |
| qcom,mdss-dsi-v-back-porch = <0x0e>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bc 00 05 01 00 00 10 00 01 28 05 01 00 00 32 00 01 10]; | |
| qcom,video-to-cmd-mode-post-switch-commands = [39 00 00 00 00 00 02 ff 10 39 00 00 00 00 00 02 fb 01 39 00 00 00 00 00 02 bb 10 39 00 00 00 00 00 02 ff 26 39 00 00 00 00 00 02 fb 01 39 00 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0xa30>; | |
| qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; | |
| }; | |
| timing@6 { | |
| qcom,partial-update-enabled = "single_roi"; | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x78>; | |
| qcom,mdss-dsi-h-pulse-width = <0x08>; | |
| qcom,mdss-dsi-panel-jitter = <0x03 0x01>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 40 39 01 00 00 10 00 02 f1 40 39 01 00 00 00 00 02 ff 10 39 01 00 00 10 00 06 2c 01 02 04 08 10 39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 00 39 01 00 00 10 00 02 f1 00 39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 ba 03 39 01 00 00 00 00 02 bc 08 39 01 00 00 00 00 02 c0 85 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 0e 00 bb 00 07 0d b7 0c b7 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 d5 00 39 01 00 00 00 00 02 d6 00 39 01 00 00 00 00 02 de 00 39 01 00 00 00 00 02 e1 00 39 01 00 00 00 00 02 e5 01 39 01 00 00 00 00 02 bb 10 39 01 00 00 00 00 02 f6 70 39 01 00 00 00 00 02 f7 80 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 44 00 39 01 00 00 00 00 02 ff 20 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 87 02 39 01 00 00 00 00 02 5d 00 39 01 00 00 00 00 02 5e 14 39 01 00 00 00 00 02 5f eb 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 14 00 39 01 00 00 00 00 02 15 10 39 01 00 00 00 00 02 16 00 39 01 00 00 00 00 02 17 10 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 00 39 01 00 00 00 00 02 40 00 39 01 00 00 00 00 02 ff 28 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 91 02 39 01 00 00 00 00 02 ff e0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 48 81 39 01 00 00 00 00 02 8e 09 39 01 00 00 00 00 02 ff f0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 33 20 39 01 00 00 00 00 02 34 35 39 01 00 00 00 00 02 ff 10 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29]; | |
| qcom,mdss-dsi-h-front-porch = <0x14>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x0c>; | |
| qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 c0 85 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 0e 00 bb 00 07 0d b7 0c b7 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 16 00 39 01 00 00 00 00 02 17 10 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 00 15 01 00 00 00 00 02 ff 10 05 01 00 00 00 00 01 28 05 01 00 00 00 00 01 29]; | |
| qcom,mdss-dsc-slice-height = <0x08>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x21c>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 1e 1d 04 04 02 02 04 00 0e 13]; | |
| qcom,mdss-dsi-v-back-porch = <0x0e>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,panel-roi-alignment = <0x21c 0x08 0x08 0x08 0x438 0x08>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bc 00 05 01 00 00 10 00 01 28 05 01 00 00 32 00 01 10]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x10>; | |
| qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; | |
| }; | |
| timing@4 { | |
| qcom,partial-update-enabled = "single_roi"; | |
| qcom,video-to-cmd-mode-post-switch-commands-state = "dsi_lp_mode"; | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x78>; | |
| qcom,mdss-dsi-h-pulse-width = <0x08>; | |
| qcom,mdss-dsi-panel-jitter = <0x03 0x01>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 40 39 01 00 00 10 00 02 f1 40 39 01 00 00 00 00 02 ff 10 39 01 00 00 10 00 06 2c 01 02 04 08 10 39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 00 39 01 00 00 10 00 02 f1 00 39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 ba 03 39 01 00 00 00 00 02 bc 08 39 01 00 00 00 00 02 c0 83 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 68 00 d5 00 0a 0d b7 09 89 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 d5 00 39 01 00 00 00 00 02 d6 00 39 01 00 00 00 00 02 de 00 39 01 00 00 00 00 02 e1 00 39 01 00 00 00 00 02 e5 01 39 01 00 00 00 00 02 bb 10 39 01 00 00 00 00 02 f6 70 39 01 00 00 00 00 02 f7 80 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 44 00 39 01 00 00 00 00 02 ff 20 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 87 02 39 01 00 00 00 00 02 5d 00 39 01 00 00 00 00 02 5e 14 39 01 00 00 00 00 02 5f eb 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 14 00 39 01 00 00 00 00 02 15 10 39 01 00 00 00 00 02 16 00 39 01 00 00 00 00 02 17 10 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 01 39 01 00 00 00 00 02 40 00 39 01 00 00 00 00 02 ff 28 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 91 02 39 01 00 00 00 00 02 ff e0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 48 81 39 01 00 00 00 00 02 8e 09 39 01 00 00 00 00 02 ff f0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 33 20 39 01 00 00 00 00 02 34 35 39 01 00 00 00 00 02 ff 10 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29]; | |
| qcom,mdss-dsi-h-front-porch = <0x14>; | |
| qcom,mdss-dsc-slice-width = <0x2d0>; | |
| qcom,mdss-dsi-h-back-porch = <0x0c>; | |
| qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 c0 83 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 68 00 d5 00 0a 0d b7 09 89 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 16 00 39 01 00 00 00 00 02 17 10 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 03 15 01 00 00 00 00 02 ff 10 05 01 00 00 00 00 01 28 05 01 00 00 00 00 01 29]; | |
| qcom,mdss-dsc-slice-height = <0x08>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 1f 1e 05 05 03 02 04 00 12 14]; | |
| qcom,mdss-dsi-v-back-porch = <0x0e>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,panel-roi-alignment = <0x2d0 0x08 0x08 0x08 0x5a0 0x08>; | |
| qcom,cmd-to-video-mode-post-switch-commands = [39 00 00 00 00 00 02 ff 10 39 00 00 00 00 00 02 fb 01 39 00 00 00 00 00 02 bb 13 39 00 00 00 00 00 02 ff 26 39 00 00 00 00 00 02 fb 01 39 00 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 06]; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bc 00 05 01 00 00 10 00 01 28 05 01 00 00 32 00 01 10]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x10>; | |
| qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; | |
| }; | |
| timing@2 { | |
| qcom,partial-update-enabled = "single_roi"; | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x08>; | |
| qcom,mdss-dsi-panel-jitter = <0x03 0x01>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 40 39 01 00 00 10 00 02 f1 40 39 01 00 00 00 00 02 ff 10 39 01 00 00 10 00 06 2c 01 02 04 08 10 39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 00 39 01 00 00 10 00 02 f1 00 39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 ba 03 39 01 00 00 00 00 02 bc 08 39 01 00 00 00 00 02 c0 85 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 0e 00 bb 00 07 0d b7 0c b7 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 d5 00 39 01 00 00 00 00 02 d6 00 39 01 00 00 00 00 02 de 00 39 01 00 00 00 00 02 e1 00 39 01 00 00 00 00 02 e5 01 39 01 00 00 00 00 02 bb 10 39 01 00 00 00 00 02 f6 70 39 01 00 00 00 00 02 f7 80 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 44 00 39 01 00 00 00 00 02 ff 20 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 87 02 39 01 00 00 00 00 02 5d 00 39 01 00 00 00 00 02 5e 14 39 01 00 00 00 00 02 5f eb 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 14 00 39 01 00 00 00 00 02 15 10 39 01 00 00 00 00 02 16 0a 39 01 00 00 00 00 02 17 30 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 01 39 01 00 00 00 00 02 40 00 39 01 00 00 00 00 02 ff 28 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 91 02 39 01 00 00 00 00 02 ff e0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 48 81 39 01 00 00 00 00 02 8e 09 39 01 00 00 00 00 02 ff f0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 33 20 39 01 00 00 00 00 02 34 35 39 01 00 00 00 00 02 ff 10 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29]; | |
| qcom,mdss-dsi-h-front-porch = <0x14>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,mdss-dsi-h-back-porch = <0x0c>; | |
| qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 c0 85 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 0e 00 bb 00 07 0d b7 0c b7 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 16 0a 39 01 00 00 00 00 02 17 30 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 01 15 01 00 00 00 00 02 ff 10 05 01 00 00 00 00 01 28 05 01 00 00 00 00 01 29]; | |
| qcom,mdss-dsc-slice-height = <0x08>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x21c>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 0a 01 02 1b 1c 02 02 00 02 04 00 0a 12]; | |
| qcom,mdss-dsi-v-back-porch = <0x0e>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,panel-roi-alignment = <0x21c 0x08 0x08 0x08 0x438 0x08>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bc 00 05 01 00 00 10 00 01 28 05 01 00 00 32 00 01 10]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x10>; | |
| qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; | |
| }; | |
| timing@0 { | |
| qcom,partial-update-enabled = "single_roi"; | |
| qcom,video-to-cmd-mode-post-switch-commands-state = "dsi_lp_mode"; | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x08>; | |
| qcom,mdss-dsi-panel-jitter = <0x03 0x01>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 40 39 01 00 00 10 00 02 f1 40 39 01 00 00 00 00 02 ff 10 39 01 00 00 10 00 06 2c 01 02 04 08 10 39 01 00 00 00 00 02 ff d0 39 01 00 00 00 00 02 75 00 39 01 00 00 10 00 02 f1 00 39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 ba 03 39 01 00 00 00 00 02 bc 08 39 01 00 00 00 00 02 c0 83 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 68 00 d5 00 0a 0d b7 09 89 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 d5 00 39 01 00 00 00 00 02 d6 00 39 01 00 00 00 00 02 de 00 39 01 00 00 00 00 02 e1 00 39 01 00 00 00 00 02 e5 01 39 01 00 00 00 00 02 bb 10 39 01 00 00 00 00 02 f6 70 39 01 00 00 00 00 02 f7 80 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 44 00 39 01 00 00 00 00 02 ff 20 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 87 02 39 01 00 00 00 00 02 5d 00 39 01 00 00 00 00 02 5e 14 39 01 00 00 00 00 02 5f eb 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 14 00 39 01 00 00 00 00 02 15 10 39 01 00 00 00 00 02 16 0a 39 01 00 00 00 00 02 17 30 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 01 39 01 00 00 00 00 02 40 00 39 01 00 00 00 00 02 ff 28 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 91 02 39 01 00 00 00 00 02 ff e0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 48 81 39 01 00 00 00 00 02 8e 09 39 01 00 00 00 00 02 ff f0 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 33 20 39 01 00 00 00 00 02 34 35 39 01 00 00 00 00 02 ff 10 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29]; | |
| qcom,mdss-dsi-h-front-porch = <0x14>; | |
| qcom,mdss-dsc-slice-width = <0x2d0>; | |
| qcom,mdss-dsi-h-back-porch = <0x0c>; | |
| qcom,mdss-dsi-timing-switch-command = [39 01 00 00 00 00 02 ff 10 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 c0 83 39 01 00 00 00 00 11 c1 89 28 00 08 02 00 02 68 00 d5 00 0a 0d b7 09 89 39 01 00 00 00 00 03 c2 10 f0 39 01 00 00 00 00 02 ff 24 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 16 0a 39 01 00 00 00 00 02 17 30 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 01 15 01 00 00 00 00 02 ff 10 05 01 00 00 00 00 01 28 05 01 00 00 00 00 01 29]; | |
| qcom,mdss-dsc-slice-height = <0x08>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 0b 03 02 1d 1c 03 03 01 02 04 00 0c 12]; | |
| qcom,mdss-dsi-v-back-porch = <0x0e>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,panel-roi-alignment = <0x2d0 0x08 0x08 0x08 0x5a0 0x08>; | |
| qcom,cmd-to-video-mode-post-switch-commands = [39 00 00 00 00 00 02 ff 10 39 00 00 00 00 00 02 fb 01 39 00 00 00 00 00 02 bb 13 39 00 00 00 00 00 02 ff 26 39 00 00 00 00 00 02 fb 01 39 00 00 00 00 00 02 60 00 39 01 00 00 00 00 02 62 06]; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-cmd-mode; | |
| qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bc 00 05 01 00 00 10 00 01 28 05 01 00 00 32 00 01 10]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x10>; | |
| qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_sharp_4k_dsc_video { | |
| qcom,adjust-timer-wakeup-ms = <0x01>; | |
| qcom,dsi-phy-num = <0x00 0x01>; | |
| qcom,mdss-pan-physical-width-dimension = <0x47>; | |
| qcom,mdss-dsi-panel-name = "Sharp 4k video mode dsc dsi panel"; | |
| qcom,mdss-pan-physical-height-dimension = <0x81>; | |
| qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0"; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00 0x01>; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x64 0x00 0x64 0x01 0x64>; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| phandle = <0x6d4>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsi-panel-height = <0xf00>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 10 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29]; | |
| qcom,mdss-dsi-h-front-porch = <0x1e>; | |
| qcom,mdss-dsc-slice-width = <0x438>; | |
| qcom,mdss-dsi-h-back-porch = <0x64>; | |
| qcom,mdss-dsc-slice-height = <0x20>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 08 05 02 04 00 19 18]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_nt35695b_truly_fhd_video { | |
| qcom,dsi-sec-phy-num = <0x01>; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,dsi-sec-ctrl-num = <0x01>; | |
| qcom,mdss-dsi-panel-name = "nt35695b truly fhd video mode dsi panel"; | |
| qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-post-init-delay = <0x01>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| phandle = <0x6da>; | |
| qcom,dsi-select-sec-clocks = "mux_byte_clk1\0mux_pixel_clk1"; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x01 0x00 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x0c>; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsi-on-command = [15 01 00 00 10 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 55 15 01 00 00 00 00 02 02 45 15 01 00 00 00 00 02 03 55 15 01 00 00 00 00 02 05 50 15 01 00 00 00 00 02 06 a8 15 01 00 00 00 00 02 07 ad 15 01 00 00 00 00 02 08 0c 15 01 00 00 00 00 02 0b aa 15 01 00 00 00 00 02 0c aa 15 01 00 00 00 00 02 0e b0 15 01 00 00 00 00 02 0f b3 15 01 00 00 00 00 02 11 28 15 01 00 00 00 00 02 12 10 15 01 00 00 00 00 02 13 01 15 01 00 00 00 00 02 14 4a 15 01 00 00 00 00 02 15 12 15 01 00 00 00 00 02 16 12 15 01 00 00 00 00 02 30 01 15 01 00 00 00 00 02 72 11 15 01 00 00 00 00 02 58 82 15 01 00 00 00 00 02 59 00 15 01 00 00 00 00 02 5a 02 15 01 00 00 00 00 02 5b 00 15 01 00 00 00 00 02 5c 82 15 01 00 00 00 00 02 5d 80 15 01 00 00 00 00 02 5e 02 15 01 00 00 00 00 02 5f 00 15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 0b 15 01 00 00 00 00 02 02 0c 15 01 00 00 00 00 02 03 89 15 01 00 00 00 00 02 04 8a 15 01 00 00 00 00 02 05 0f 15 01 00 00 00 00 02 06 10 15 01 00 00 00 00 02 07 10 15 01 00 00 00 00 02 08 1c 15 01 00 00 00 00 02 09 00 15 01 00 00 00 00 02 0a 00 15 01 00 00 00 00 02 0b 00 15 01 00 00 00 00 02 0c 00 15 01 00 00 00 00 02 0d 13 15 01 00 00 00 00 02 0e 15 15 01 00 00 00 00 02 0f 17 15 01 00 00 00 00 02 10 01 15 01 00 00 00 00 02 11 0b 15 01 00 00 00 00 02 12 0c 15 01 00 00 00 00 02 13 89 15 01 00 00 00 00 02 14 8a 15 01 00 00 00 00 02 15 0f 15 01 00 00 00 00 02 16 10 15 01 00 00 00 00 02 17 10 15 01 00 00 00 00 02 18 1c 15 01 00 00 00 00 02 19 00 15 01 00 00 00 00 02 1a 00 15 01 00 00 00 00 02 1b 00 15 01 00 00 00 00 02 1c 00 15 01 00 00 00 00 02 1d 13 15 01 00 00 00 00 02 1e 15 15 01 00 00 00 00 02 1f 17 15 01 00 00 00 00 02 20 00 15 01 00 00 00 00 02 21 01 15 01 00 00 00 00 02 22 00 15 01 00 00 00 00 02 23 40 15 01 00 00 00 00 02 24 40 15 01 00 00 00 00 02 25 6d 15 01 00 00 00 00 02 26 40 15 01 00 00 00 00 02 27 40 15 01 00 00 00 00 02 29 d8 15 01 00 00 00 00 02 2a 2a 15 01 00 00 00 00 02 4b 03 15 01 00 00 00 00 02 4c 11 15 01 00 00 00 00 02 4d 10 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 4f 01 15 01 00 00 00 00 02 50 10 15 01 00 00 00 00 02 51 00 15 01 00 00 00 00 02 52 80 15 01 00 00 00 00 02 53 00 15 01 00 00 00 00 02 54 07 15 01 00 00 00 00 02 55 25 15 01 00 00 00 00 02 56 00 15 01 00 00 00 00 02 58 07 15 01 00 00 00 00 02 5b 43 15 01 00 00 00 00 02 5c 00 15 01 00 00 00 00 02 5f 73 15 01 00 00 00 00 02 60 73 15 01 00 00 00 00 02 63 22 15 01 00 00 00 00 02 64 00 15 01 00 00 00 00 02 67 08 15 01 00 00 00 00 02 68 04 15 01 00 00 00 00 02 7a 80 15 01 00 00 00 00 02 7b 91 15 01 00 00 00 00 02 7c d8 15 01 00 00 00 00 02 7d 60 15 01 00 00 00 00 02 93 06 15 01 00 00 00 00 02 94 06 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 9b 0f 15 01 00 00 00 00 02 b3 c0 15 01 00 00 00 00 02 b4 00 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 b6 21 15 01 00 00 00 00 02 b7 22 15 01 00 00 00 00 02 b8 07 15 01 00 00 00 00 02 b9 07 15 01 00 00 00 00 02 ba 22 15 01 00 00 00 00 02 bd 20 15 01 00 00 00 00 02 be 07 15 01 00 00 00 00 02 bf 07 15 01 00 00 00 00 02 c1 6d 15 01 00 00 00 00 02 c4 24 15 01 00 00 00 00 02 e3 00 15 01 00 00 00 00 02 ec 00 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bb 03 05 01 00 00 78 00 02 11 00 05 01 00 00 78 00 02 29 00]; | |
| qcom,mdss-dsi-h-front-porch = <0x78>; | |
| qcom,mdss-dsi-h-back-porch = <0x3c>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 08 05 02 04 00 19 17]; | |
| qcom,mdss-dsi-v-back-porch = <0x02>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-v-front-porch = <0x0c>; | |
| qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_nt35597_truly_wqxga_cmd { | |
| qcom,ulps-enabled; | |
| qcom,adjust-timer-wakeup-ms = <0x01>; | |
| qcom,dsi-phy-num = <0x00 0x01>; | |
| qcom,mdss-pan-physical-width-dimension = <0x4a>; | |
| qcom,mdss-dsi-panel-name = "Dual nt35597 cmd mode dsi truly panel without DSC"; | |
| qcom,mdss-pan-physical-height-dimension = <0x83>; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,config-select = <0x639>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00 0x01>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| phandle = <0x6d7>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-panel-timings = <0xcd322200 0x60642634 0x29030400>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x02 0x00 0x02 0x01 0x00 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| qcom,mdss-dsi-panel-jitter = <0x01 0x01>; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 55 15 01 00 00 00 00 02 02 45 15 01 00 00 00 00 02 05 40 15 01 00 00 00 00 02 06 19 15 01 00 00 00 00 02 07 1e 15 01 00 00 00 00 02 0b 73 15 01 00 00 00 00 02 0c 73 15 01 00 00 00 00 02 0e b0 15 01 00 00 00 00 02 0f ae 15 01 00 00 00 00 02 11 b8 15 01 00 00 00 00 02 13 00 15 01 00 00 00 00 02 58 80 15 01 00 00 00 00 02 59 01 15 01 00 00 00 00 02 5a 00 15 01 00 00 00 00 02 5b 01 15 01 00 00 00 00 02 5c 80 15 01 00 00 00 00 02 5d 81 15 01 00 00 00 00 02 5e 00 15 01 00 00 00 00 02 5f 01 15 01 00 00 00 00 02 72 31 15 01 00 00 00 00 02 68 03 15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 1c 15 01 00 00 00 00 02 01 0b 15 01 00 00 00 00 02 02 0c 15 01 00 00 00 00 02 03 01 15 01 00 00 00 00 02 04 0f 15 01 00 00 00 00 02 05 10 15 01 00 00 00 00 02 06 10 15 01 00 00 00 00 02 07 10 15 01 00 00 00 00 02 08 89 15 01 00 00 00 00 02 09 8a 15 01 00 00 00 00 02 0a 13 15 01 00 00 00 00 02 0b 13 15 01 00 00 00 00 02 0c 15 15 01 00 00 00 00 02 0d 15 15 01 00 00 00 00 02 0e 17 15 01 00 00 00 00 02 0f 17 15 01 00 00 00 00 02 10 1c 15 01 00 00 00 00 02 11 0b 15 01 00 00 00 00 02 12 0c 15 01 00 00 00 00 02 13 01 15 01 00 00 00 00 02 14 0f 15 01 00 00 00 00 02 15 10 15 01 00 00 00 00 02 16 10 15 01 00 00 00 00 02 17 10 15 01 00 00 00 00 02 18 89 15 01 00 00 00 00 02 19 8a 15 01 00 00 00 00 02 1a 13 15 01 00 00 00 00 02 1b 13 15 01 00 00 00 00 02 1c 15 15 01 00 00 00 00 02 1d 15 15 01 00 00 00 00 02 1e 17 15 01 00 00 00 00 02 1f 17 15 01 00 00 00 00 02 20 40 15 01 00 00 00 00 02 21 01 15 01 00 00 00 00 02 22 00 15 01 00 00 00 00 02 23 40 15 01 00 00 00 00 02 24 40 15 01 00 00 00 00 02 25 6d 15 01 00 00 00 00 02 26 40 15 01 00 00 00 00 02 27 40 15 01 00 00 00 00 02 e0 00 15 01 00 00 00 00 02 dc 21 15 01 00 00 00 00 02 dd 22 15 01 00 00 00 00 02 de 07 15 01 00 00 00 00 02 df 07 15 01 00 00 00 00 02 e3 6d 15 01 00 00 00 00 02 e1 07 15 01 00 00 00 00 02 e2 07 15 01 00 00 00 00 02 29 d8 15 01 00 00 00 00 02 2a 2a 15 01 00 00 00 00 02 4b 03 15 01 00 00 00 00 02 4c 11 15 01 00 00 00 00 02 4d 10 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 4f 01 15 01 00 00 00 00 02 50 10 15 01 00 00 00 00 02 51 00 15 01 00 00 00 00 02 52 80 15 01 00 00 00 00 02 53 00 15 01 00 00 00 00 02 56 00 15 01 00 00 00 00 02 54 07 15 01 00 00 00 00 02 58 07 15 01 00 00 00 00 02 55 25 15 01 00 00 00 00 02 5b 43 15 01 00 00 00 00 02 5c 00 15 01 00 00 00 00 02 5f 73 15 01 00 00 00 00 02 60 73 15 01 00 00 00 00 02 63 22 15 01 00 00 00 00 02 64 00 15 01 00 00 00 00 02 67 08 15 01 00 00 00 00 02 68 04 15 01 00 00 00 00 02 72 02 15 01 00 00 00 00 02 7a 80 15 01 00 00 00 00 02 7b 91 15 01 00 00 00 00 02 7c d8 15 01 00 00 00 00 02 7d 60 15 01 00 00 00 00 02 7f 15 15 01 00 00 00 00 02 75 15 15 01 00 00 00 00 02 b3 c0 15 01 00 00 00 00 02 b4 00 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 78 00 15 01 00 00 00 00 02 79 00 15 01 00 00 00 00 02 80 00 15 01 00 00 00 00 02 83 00 15 01 00 00 00 00 02 93 0a 15 01 00 00 00 00 02 94 0a 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 9b ff 15 01 00 00 00 00 02 9d b0 15 01 00 00 00 00 02 9f 63 15 01 00 00 00 00 02 98 10 15 01 00 00 00 00 02 ec 00 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 04 3b 03 0a 0a 15 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 e5 01 15 01 00 00 00 00 02 bb 10 15 01 00 00 00 00 02 fb 01 05 01 00 00 78 00 02 11 00 05 01 00 00 78 00 02 29 00]; | |
| qcom,mdss-dsi-h-front-porch = <0x64>; | |
| qcom,mdss-dsi-h-back-porch = <0x20>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 07 05 02 04 00 18 17]; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-panel-timings-phy-v2 = <0x231e0708 0x50304a0 0x231e0708 0x50304a0 0x231e0708 0x50304a0 0x231e0708 0x50304a0 0x23180708 0x40304a0>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| config0 { | |
| qcom,split-mode = "dualctl-split"; | |
| phandle = <0x639>; | |
| }; | |
| }; | |
| qcom,sde-sspp-vig-blocks { | |
| qcom,sde-vig-igc = <0x1d00 0x60000>; | |
| qcom,sde-vig-gamut = <0x1d00 0x60000>; | |
| qcom,sde-vig-qseed-size = <0xa0>; | |
| qcom,sde-vig-csc-off = <0x1a00>; | |
| qcom,sde-vig-inverse-pma; | |
| qcom,sde-vig-qseed-off = <0xa00>; | |
| }; | |
| qcom,mdss_dsi_dual_sim_video { | |
| qcom,dsi-phy-num = <0x00 0x01>; | |
| qcom,mdss-dsi-panel-name = "Sim dual video mode dsi panel"; | |
| qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,panel-ack-disabled; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00 0x01>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-qsync-min-refresh-rate = <0x2d>; | |
| qcom,platform-reset-gpio = <0x66 0x4b 0x00>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-panel-broadcast-mode; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x14 0x00 0xc8 0x01 0x14>; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| phandle = <0x6e2>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,panel-supply-entries = <0x638>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-qsync-off-commands = [15 01 00 00 00 00 02 51 00]; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x02 0x00 0x02 0x01 0x00 0x02>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| qcom,mdss-dsi-qsync-on-commands = [15 01 00 00 00 00 02 51 00]; | |
| qcom,mdss-dsi-panel-height = <0x5a0>; | |
| qcom,mdss-dsi-h-front-porch = <0x78>; | |
| qcom,mdss-dsi-h-back-porch = <0x2c>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsi-qsync-off-commands-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x500>; | |
| qcom,mdss-dsi-v-pulse-width = <0x04>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 07 05 02 04 00 18 17]; | |
| qcom,mdss-dsi-v-back-porch = <0x04>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-qsync-on-commands-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,sde-dspp-blocks { | |
| qcom,sde-dspp-memcolor = <0x880 0x10007>; | |
| qcom,sde-dspp-gc = <0x17c0 0x10008>; | |
| qcom,sde-dspp-pcc = <0x1700 0x40000>; | |
| qcom,sde-dspp-igc = <0x00 0x30001>; | |
| qcom,sde-dspp-hist = <0x800 0x10007>; | |
| qcom,sde-dspp-vlut = <0xa00 0x10008>; | |
| qcom,sde-dspp-dither = <0x82c 0x10007>; | |
| qcom,sde-dspp-gamut = <0x1000 0x40002>; | |
| qcom,sde-dspp-sixzone = <0x900 0x10007>; | |
| qcom,sde-dspp-hsic = <0x800 0x10007>; | |
| }; | |
| qcom,mdss_dsi_sim_sec_hd_cmd { | |
| qcom,dsi-sec-phy-num = <0x01>; | |
| qcom,ulps-enabled; | |
| qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,platform-sec-reset-gpio = <0x66 0x80 0x00>; | |
| qcom,dsi-sec-ctrl-num = <0x01>; | |
| qcom,mdss-dsi-panel-name = "sim hd command mode secondary dsi panel"; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,panel-ack-disabled; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-post-init-delay = <0x01>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-bl-max-level = <0x3ff>; | |
| qcom,platform-reset-gpio = <0x66 0x4b 0x00>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,panel-sec-supply-entries = <0x638>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-te-using-wd; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| phandle = <0x6e3>; | |
| qcom,dsi-select-sec-clocks = "mux_byte_clk1\0mux_pixel_clk1"; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,panel-supply-entries = <0x638>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,partial-update-enabled = "single_roi"; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x01 0x00 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x0c>; | |
| qcom,mdss-dsi-panel-height = <0x500>; | |
| qcom,mdss-dsi-on-command = <0x5010000 0x78000111 0x5010000 0x78000129>; | |
| qcom,mdss-dsi-h-front-porch = <0x78>; | |
| qcom,mdss-dsi-h-back-porch = <0x3c>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 08 05 02 04 00 19 17]; | |
| qcom,mdss-dsi-v-back-porch = <0x02>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,panel-roi-alignment = <0x2d0 0x28 0x2d0 0x28 0x2d0 0x28>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-v-front-porch = <0x0c>; | |
| qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; | |
| }; | |
| }; | |
| }; | |
| qcom,sde-data-bus { | |
| qcom,msm-bus,name = "mdss_sde"; | |
| qcom,msm-bus,num-paths = <0x02>; | |
| qcom,msm-bus,num-cases = <0x03>; | |
| qcom,msm-bus,vectors-KBps = <0x16 0x200 0x00 0x00 0x17 0x200 0x00 0x00 0x16 0x200 0x00 0x61a800 0x17 0x200 0x00 0x61a800 0x16 0x200 0x00 0x61a800 0x17 0x200 0x00 0x61a800>; | |
| }; | |
| qcom,sde-sspp-dma-blocks { | |
| dgm@1 { | |
| qcom,sde-dma-igc = <0x1400 0x50000>; | |
| qcom,sde-dma-gc = <0x600 0x50000>; | |
| qcom,sde-dma-csc-off = <0x1200>; | |
| qcom,sde-dma-inverse-pma; | |
| }; | |
| dgm@0 { | |
| qcom,sde-dma-igc = <0x400 0x50000>; | |
| qcom,sde-dma-gc = <0x600 0x50000>; | |
| qcom,sde-dma-csc-off = <0x200>; | |
| qcom,sde-dma-inverse-pma; | |
| }; | |
| }; | |
| qcom,mdss_dsi_sharp_1080p_cmd { | |
| qcom,ulps-enabled; | |
| qcom,dsi-phy-num = <0x00>; | |
| qcom,mdss-pan-physical-width-dimension = <0x40>; | |
| qcom,mdss-dsi-panel-name = "sharp 1080p cmd mode dsi panel"; | |
| qcom,mdss-pan-physical-height-dimension = <0x75>; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,dsi-select-clocks = "mux_byte_clk0\0mux_pixel_clk0"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,dsi-ctrl-num = <0x00>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-panel-clockrate = <0x32a9f880>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| phandle = <0x6d6>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-panel-controller = <0x557>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-panel-destination = "display_1"; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,display-topology = <0x01 0x00 0x01>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsi-on-command = <0x15010000 0x2bb 0x10150100 0x02 0xb0030501 0x7800 0x1111501 0x00 0x251ff15 0x1000000 0x25324 0x15010000 0x2ff 0x23150100 0x02 0x8051501 0x00 0x2469015 0x1000000 0x2ff10 0x15010000 0x2ff 0xf0150100 0x02 0x92011501 0x00 0x2ff1015 0x1000000 0x23500 0x5010000 0x28000129>; | |
| qcom,mdss-dsi-h-front-porch = <0x00>; | |
| qcom,mdss-dsi-h-back-porch = <0x00>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsi-panel-clockrate = <0x35a4e900>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-v-pulse-width = <0x00>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = [00 1e 08 08 24 22 08 08 05 02 04 00 19 18]; | |
| qcom,mdss-dsi-v-back-porch = <0x00>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-off-command = <0x5010000 0x10000128 0x5010000 0x40000110>; | |
| qcom,mdss-dsi-v-front-porch = <0x00>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| }; | |
| }; | |
| }; | |
| }; | |
| jtagmm@7540000 { | |
| clock-names = "core_clk"; | |
| reg-names = "etm-base"; | |
| clocks = <0x49 0x00>; | |
| compatible = "qcom,jtagv8-mm"; | |
| qcom,coresight-jtagmm-cpu = <0x12>; | |
| reg = <0x7540000 0x1000>; | |
| phandle = <0x357>; | |
| }; | |
| qcom,msm-cdsp-loader { | |
| compatible = "qcom,cdsp-loader"; | |
| qcom,proc-img-to-load = "cdsp"; | |
| }; | |
| cti@6c61000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti-mdss_dl_cti"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6c61000 0x1000>; | |
| phandle = <0x536>; | |
| }; | |
| cti@601d000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti13"; | |
| compatible = "arm,primecell"; | |
| reg = <0x601d000 0x1000>; | |
| phandle = <0x525>; | |
| }; | |
| cti@6c4b000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti-npu_q6_cti"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6c4b000 0x1000>; | |
| phandle = <0x539>; | |
| }; | |
| qcom,msm-dai-tdm-sen-rx { | |
| qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
| qcom,msm-cpudai-tdm-data-out = <0x00>; | |
| qcom,msm-cpudai-tdm-data-delay = <0x01>; | |
| qcom,msm-cpudai-tdm-group-port-id = <0x9050>; | |
| qcom,msm-cpudai-tdm-group-num-ports = <0x01>; | |
| qcom,msm-cpudai-tdm-invert-sync = <0x01>; | |
| compatible = "qcom,msm-dai-tdm"; | |
| qcom,msm-cpudai-tdm-group-id = <0x9150>; | |
| phandle = <0x5f0>; | |
| qcom,msm-cpudai-tdm-sync-src = <0x01>; | |
| qcom,msm-cpudai-tdm-clk-internal = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-mode = <0x01>; | |
| qcom,msm-dai-q6-tdm-sen-rx-0 { | |
| qcom,msm-cpudai-tdm-dev-id = <0x9050>; | |
| qcom,msm-cpudai-tdm-data-align = <0x00>; | |
| compatible = "qcom,msm-dai-q6-tdm"; | |
| phandle = <0x313>; | |
| }; | |
| }; | |
| apps-smmu@15000000 { | |
| #global-interrupts = <0x02>; | |
| #address-cells = <0x01>; | |
| reg-names = "base\0tcu-base"; | |
| qcom,msm-bus,name = "apps_smmu"; | |
| qcom,msm-bus,active-only; | |
| interrupts = <0x00 0x40 0x04 0x00 0x41 0x04 0x00 0x61 0x04 0x00 0x62 0x04 0x00 0x63 0x04 0x00 0x64 0x04 0x00 0x65 0x04 0x00 0x66 0x04 0x00 0x67 0x04 0x00 0x68 0x04 0x00 0x69 0x04 0x00 0x6a 0x04 0x00 0x6b 0x04 0x00 0x6c 0x04 0x00 0x6d 0x04 0x00 0x6e 0x04 0x00 0x6f 0x04 0x00 0x70 0x04 0x00 0x71 0x04 0x00 0x72 0x04 0x00 0x73 0x04 0x00 0x74 0x04 0x00 0x75 0x04 0x00 0x76 0x04 0x00 0xb5 0x04 0x00 0xb6 0x04 0x00 0xb7 0x04 0x00 0xb8 0x04 0x00 0xb9 0x04 0x00 0xba 0x04 0x00 0xbb 0x04 0x00 0xbc 0x04 0x00 0xbd 0x04 0x00 0xbe 0x04 0x00 0xbf 0x04 0x00 0xc0 0x04 0x00 0x13b 0x04 0x00 0x13c 0x04 0x00 0x13d 0x04 0x00 0x13e 0x04 0x00 0x13f 0x04 0x00 0x140 0x04 0x00 0x141 0x04 0x00 0x142 0x04 0x00 0x143 0x04 0x00 0x144 0x04 0x00 0x145 0x04 0x00 0x146 0x04 0x00 0x147 0x04 0x00 0x148 0x04 0x00 0x149 0x04 0x00 0x14a 0x04 0x00 0x14b 0x04 0x00 0x14c 0x04 0x00 0x14d 0x04 0x00 0x14e 0x04 0x00 0x14f 0x04 0x00 0x150 0x04 0x00 0x151 0x04 0x00 0x152 0x04 0x00 0x153 0x04 0x00 0x154 0x04 0x00 0x155 0x04 0x00 0x156 0x04 0x00 0x157 0x04 0x00 0x158 0x04 0x00 0x159 0x04 0x00 0x18b 0x04 0x00 0x18c 0x04 0x00 0x18d 0x04 0x00 0x18e 0x04 0x00 0x18f 0x04 0x00 0x190 0x04 0x00 0x191 0x04 0x00 0x192 0x04 0x00 0x193 0x04 0x00 0x194 0x04 0x00 0x195 0x04 0x00 0x196 0x04 0x00 0x197 0x04 0x00 0x198 0x04 0x00 0x199 0x04 0x00 0x19c 0x04 0x00 0x1a2 0x04 0x00 0x1a3 0x04 0x00 0x1a5 0x04 0x00 0x1a7 0x04 0x00 0x1a8 0x04 0x00 0x1a9 0x04 0x00 0x2b2 0x04 0x00 0x2b3 0x04 0x00 0x2b4 0x04 0x00 0x2b5 0x04 0x00 0x2b6 0x04 0x00 0x2b7 0x04 0x00 0x2b8 0x04 0x00 0x2b9 0x04 0x00 0x2c3 0x04>; | |
| qcom,actlr = <0x800 0x3ff 0x103 0xc00 0x3ff 0x103 0x2000 0x3ff 0x103 0x2400 0x3ff 0x103 0x1081 0x400 0x103 0x1082 0x400 0x103 0x1085 0x400 0x103 0x10a1 0x400 0x103 0x10a2 0x400 0x103 0x10a5 0x400 0x103>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| #size-cells = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| qcom,skip-init; | |
| qcom,use-3-lvl-tables; | |
| #iommu-cells = <0x02>; | |
| compatible = "qcom,qsmmu-v500"; | |
| ranges; | |
| reg = <0x15000000 0x100000 0x15182000 0x20>; | |
| phandle = <0x47>; | |
| qcom,msm-bus,vectors-KBps = <0xa1 0x273 0x00 0x00 0xa1 0x273 0x00 0x3e8>; | |
| mnoc_sf_1_tbu@151a9000 { | |
| reg-names = "base\0status-reg"; | |
| qcom,msm-bus,name = "mnoc_sf_1_tbu"; | |
| qcom,msm-bus,active-only; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| qcom,stream-id-range = <0x2400 0x400>; | |
| qcom,regulator-names = "vdd"; | |
| vdd-supply = <0x180>; | |
| compatible = "qcom,qsmmuv500-tbu"; | |
| reg = <0x151a9000 0x1000 0x15182248 0x08>; | |
| phandle = <0x3ef>; | |
| qcom,msm-bus,vectors-KBps = <0x89 0x304 0x00 0x00 0x89 0x304 0x00 0x3e8>; | |
| }; | |
| mnoc_sf_0_tbu@151a5000 { | |
| reg-names = "base\0status-reg"; | |
| qcom,msm-bus,name = "mnoc_sf_0_tbu"; | |
| qcom,msm-bus,active-only; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| qcom,stream-id-range = <0x2000 0x400>; | |
| qcom,regulator-names = "vdd"; | |
| vdd-supply = <0x17f>; | |
| compatible = "qcom,qsmmuv500-tbu"; | |
| reg = <0x151a5000 0x1000 0x15182240 0x08>; | |
| phandle = <0x3ee>; | |
| qcom,msm-bus,vectors-KBps = <0x89 0x304 0x00 0x00 0x89 0x304 0x00 0x3e8>; | |
| }; | |
| compute_dsp_0_tbu@15199000 { | |
| reg-names = "base\0status-reg"; | |
| qcom,msm-bus,name = "apps_smmu"; | |
| qcom,msm-bus,active-only; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| qcom,stream-id-range = <0x1400 0x400>; | |
| compatible = "qcom,qsmmuv500-tbu"; | |
| reg = <0x15199000 0x1000 0x15182228 0x08>; | |
| phandle = <0x3eb>; | |
| qcom,msm-bus,vectors-KBps = <0x9a 0x2756 0x00 0x00 0x9a 0x2756 0x00 0x3e8>; | |
| }; | |
| mnoc_hf_1_tbu@15191000 { | |
| reg-names = "base\0status-reg"; | |
| qcom,msm-bus,name = "mnoc_hf_1_tbu"; | |
| qcom,msm-bus,active-only; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| qcom,stream-id-range = <0xc00 0x400>; | |
| qcom,regulator-names = "vdd"; | |
| vdd-supply = <0x17e>; | |
| compatible = "qcom,qsmmuv500-tbu"; | |
| reg = <0x15191000 0x1000 0x15182218 0x08>; | |
| phandle = <0x3e9>; | |
| qcom,msm-bus,vectors-KBps = <0x16 0x305 0x00 0x00 0x16 0x305 0x00 0x3e8>; | |
| }; | |
| mnoc_hf_0_tbu@1518d000 { | |
| reg-names = "base\0status-reg"; | |
| qcom,msm-bus,name = "mnoc_hf_0_tbu"; | |
| qcom,msm-bus,active-only; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| qcom,stream-id-range = <0x800 0x400>; | |
| qcom,regulator-names = "vdd"; | |
| vdd-supply = <0x17d>; | |
| compatible = "qcom,qsmmuv500-tbu"; | |
| reg = <0x1518d000 0x1000 0x15182210 0x08>; | |
| phandle = <0x3e8>; | |
| qcom,msm-bus,vectors-KBps = <0x16 0x305 0x00 0x00 0x16 0x305 0x00 0x3e8>; | |
| }; | |
| anoc_2_tbu@15189000 { | |
| reg-names = "base\0status-reg"; | |
| qcom,msm-bus,name = "apps_smmu"; | |
| qcom,msm-bus,active-only; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| qcom,stream-id-range = <0x400 0x400>; | |
| compatible = "qcom,qsmmuv500-tbu"; | |
| reg = <0x15189000 0x1000 0x15182208 0x08>; | |
| phandle = <0x3e7>; | |
| qcom,msm-bus,vectors-KBps = <0xa1 0x273 0x00 0x00 0xa1 0x273 0x00 0x3e8>; | |
| }; | |
| anoc_1_tbu@15185000 { | |
| reg-names = "base\0status-reg"; | |
| qcom,msm-bus,name = "apps_smmu"; | |
| qcom,msm-bus,active-only; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| qcom,stream-id-range = <0x00 0x400>; | |
| compatible = "qcom,qsmmuv500-tbu"; | |
| reg = <0x15185000 0x1000 0x15182200 0x08>; | |
| phandle = <0x3e6>; | |
| qcom,msm-bus,vectors-KBps = <0xa1 0x273 0x00 0x00 0xa1 0x273 0x00 0x3e8>; | |
| }; | |
| anoc_1_pcie_tbu@151a1000 { | |
| clock-names = "gcc_aggre_noc_pcie_tbu_clk"; | |
| reg-names = "base\0status-reg"; | |
| qcom,msm-bus,name = "apps_smmu"; | |
| qcom,msm-bus,active-only; | |
| clocks = <0x16 0x03>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| qcom,stream-id-range = <0x1c00 0x400>; | |
| compatible = "qcom,qsmmuv500-tbu"; | |
| reg = <0x151a1000 0x1000 0x15182238 0x08>; | |
| phandle = <0x3ed>; | |
| qcom,msm-bus,vectors-KBps = <0xa1 0x273 0x00 0x00 0xa1 0x273 0x00 0x3e8>; | |
| }; | |
| adsp_tbu@1519d000 { | |
| reg-names = "base\0status-reg"; | |
| qcom,msm-bus,name = "apps_smmu"; | |
| qcom,msm-bus,active-only; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| qcom,stream-id-range = <0x1800 0x400>; | |
| compatible = "qcom,qsmmuv500-tbu"; | |
| reg = <0x1519d000 0x1000 0x15182230 0x08>; | |
| phandle = <0x3ec>; | |
| qcom,msm-bus,vectors-KBps = <0xa1 0x273 0x00 0x00 0xa1 0x273 0x00 0x3e8>; | |
| }; | |
| compute_dsp_1_tbu@15195000 { | |
| reg-names = "base\0status-reg"; | |
| qcom,msm-bus,name = "apps_smmu"; | |
| qcom,msm-bus,active-only; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| qcom,stream-id-range = <0x1000 0x400>; | |
| compatible = "qcom,qsmmuv500-tbu"; | |
| reg = <0x15195000 0x1000 0x15182220 0x08>; | |
| phandle = <0x3ea>; | |
| qcom,msm-bus,vectors-KBps = <0x9a 0x2756 0x00 0x00 0x9a 0x2756 0x00 0x3e8>; | |
| }; | |
| }; | |
| qcom,msm-imem@146bf000 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| compatible = "qcom,msm-imem"; | |
| ranges = <0x00 0x146bf000 0x1000>; | |
| reg = <0x146bf000 0x1000>; | |
| dload_type@1c { | |
| compatible = "qcom,msm-imem-dload-type"; | |
| reg = <0x1c 0x04>; | |
| }; | |
| restart_reason@65c { | |
| compatible = "qcom,msm-imem-restart_reason"; | |
| reg = <0x65c 0x04>; | |
| }; | |
| boot_stats@6b0 { | |
| compatible = "qcom,msm-imem-boot_stats"; | |
| reg = <0x6b0 0x20>; | |
| }; | |
| pil@94c { | |
| compatible = "qcom,msm-imem-pil"; | |
| reg = <0x94c 0xc8>; | |
| }; | |
| mem_dump_table@10 { | |
| compatible = "qcom,msm-imem-mem_dump_table"; | |
| reg = <0x10 0x08>; | |
| }; | |
| diag_dload@c8 { | |
| compatible = "qcom,msm-imem-diag-dload"; | |
| reg = <0xc8 0xc8>; | |
| }; | |
| kaslr_offset@6d0 { | |
| compatible = "qcom,msm-imem-kaslr_offset"; | |
| reg = <0x6d0 0x0c>; | |
| }; | |
| }; | |
| qcom,cpu-cpu-llcc-bwmon@90b6400 { | |
| reg-names = "base\0global_base"; | |
| interrupts = <0x00 0x245 0x04>; | |
| compatible = "qcom,bimc-bwmon4"; | |
| qcom,hw-timer-hz = <0x124f800>; | |
| qcom,mport = <0x00>; | |
| qcom,count-unit = <0x10000>; | |
| reg = <0x90b6400 0x300 0x90b6300 0x200>; | |
| phandle = <0x35d>; | |
| qcom,target-dev = <0x4c>; | |
| }; | |
| qcom,msm-compr-dsp { | |
| compatible = "qcom,msm-compr-dsp"; | |
| phandle = <0x2eb>; | |
| }; | |
| clocks { | |
| xo-board { | |
| clock-output-names = "xo_board"; | |
| #clock-cells = <0x00>; | |
| clock-frequency = <0x249f000>; | |
| compatible = "fixed-clock"; | |
| phandle = <0x371>; | |
| }; | |
| sleep-clk { | |
| clock-output-names = "chip_sleep_clk"; | |
| #clock-cells = <0x01>; | |
| clock-frequency = <0x7d00>; | |
| compatible = "fixed-clock"; | |
| phandle = <0x372>; | |
| }; | |
| }; | |
| stm@6002000 { | |
| arm,primecell-periphid = <0xbb962>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "stm-base\0stm-stimulus-base\0stm-debug-status"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-stm"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6002000 0x1000 0x16280000 0x180000 0x7820f0 0x04>; | |
| phandle = <0x4e7>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x1a7>; | |
| phandle = <0x1aa>; | |
| }; | |
| }; | |
| }; | |
| qcom,msm-dai-cdc-dma { | |
| compatible = "qcom,msm-dai-cdc-dma"; | |
| phandle = <0x5d2>; | |
| qcom,msm-dai-va-cdc-dma-0-tx { | |
| qcom,msm-dai-is-island-supported = <0x01>; | |
| compatible = "qcom,msm-dai-cdc-dma-dev"; | |
| qcom,msm-dai-cdc-dma-dev-id = <0xb021>; | |
| phandle = <0x31a>; | |
| }; | |
| qcom,msm-dai-rx-cdc-dma-6-rx { | |
| compatible = "qcom,msm-dai-cdc-dma-dev"; | |
| qcom,msm-dai-cdc-dma-dev-id = <0xb03c>; | |
| phandle = <0x329>; | |
| }; | |
| qcom,msm-dai-rx-cdc-dma-3-rx { | |
| compatible = "qcom,msm-dai-cdc-dma-dev"; | |
| qcom,msm-dai-cdc-dma-dev-id = <0xb036>; | |
| phandle = <0x323>; | |
| }; | |
| qcom,msm-dai-rx-cdc-dma-0-rx { | |
| compatible = "qcom,msm-dai-cdc-dma-dev"; | |
| qcom,msm-dai-cdc-dma-dev-id = <0xb030>; | |
| phandle = <0x31d>; | |
| }; | |
| qcom,msm-dai-wsa-cdc-dma-0-tx { | |
| compatible = "qcom,msm-dai-cdc-dma-dev"; | |
| qcom,msm-dai-cdc-dma-dev-id = <0xb001>; | |
| phandle = <0x316>; | |
| }; | |
| qcom,msm-dai-wsa-cdc-dma-0-rx { | |
| compatible = "qcom,msm-dai-cdc-dma-dev"; | |
| qcom,msm-dai-cdc-dma-dev-id = <0xb000>; | |
| phandle = <0x315>; | |
| }; | |
| qcom,msm-dai-tx-cdc-dma-5-tx { | |
| compatible = "qcom,msm-dai-cdc-dma-dev"; | |
| qcom,msm-dai-cdc-dma-dev-id = <0xb03b>; | |
| phandle = <0x328>; | |
| }; | |
| qcom,msm-dai-tx-cdc-dma-2-tx { | |
| compatible = "qcom,msm-dai-cdc-dma-dev"; | |
| qcom,msm-dai-cdc-dma-dev-id = <0xb035>; | |
| phandle = <0x322>; | |
| }; | |
| qcom,msm-dai-va-cdc-dma-2-tx { | |
| compatible = "qcom,msm-dai-cdc-dma-dev"; | |
| qcom,msm-dai-cdc-dma-dev-id = <0xb025>; | |
| phandle = <0x31c>; | |
| }; | |
| qcom,msm-dai-rx-cdc-dma-5-rx { | |
| compatible = "qcom,msm-dai-cdc-dma-dev"; | |
| qcom,msm-dai-cdc-dma-dev-id = <0xb03a>; | |
| phandle = <0x327>; | |
| }; | |
| qcom,msm-dai-rx-cdc-dma-2-rx { | |
| compatible = "qcom,msm-dai-cdc-dma-dev"; | |
| qcom,msm-dai-cdc-dma-dev-id = <0xb034>; | |
| phandle = <0x321>; | |
| }; | |
| qcom,msm-dai-wsa-cdc-dma-2-tx { | |
| compatible = "qcom,msm-dai-cdc-dma-dev"; | |
| qcom,msm-dai-cdc-dma-dev-id = <0xb005>; | |
| phandle = <0x319>; | |
| }; | |
| qcom,msm-dai-tx-cdc-dma-4-tx { | |
| compatible = "qcom,msm-dai-cdc-dma-dev"; | |
| qcom,msm-dai-cdc-dma-dev-id = <0xb039>; | |
| phandle = <0x326>; | |
| }; | |
| qcom,msm-dai-tx-cdc-dma-1-tx { | |
| compatible = "qcom,msm-dai-cdc-dma-dev"; | |
| qcom,msm-dai-cdc-dma-dev-id = <0xb033>; | |
| phandle = <0x320>; | |
| }; | |
| qcom,msm-dai-va-cdc-dma-1-tx { | |
| compatible = "qcom,msm-dai-cdc-dma-dev"; | |
| qcom,msm-dai-cdc-dma-dev-id = <0xb023>; | |
| phandle = <0x31b>; | |
| }; | |
| qcom,msm-dai-rx-cdc-dma-7-rx { | |
| compatible = "qcom,msm-dai-cdc-dma-dev"; | |
| qcom,msm-dai-cdc-dma-dev-id = <0xb03e>; | |
| phandle = <0x32a>; | |
| }; | |
| qcom,msm-dai-rx-cdc-dma-4-rx { | |
| compatible = "qcom,msm-dai-cdc-dma-dev"; | |
| qcom,msm-dai-cdc-dma-dev-id = <0xb038>; | |
| phandle = <0x325>; | |
| }; | |
| qcom,msm-dai-rx-cdc-dma-1-rx { | |
| compatible = "qcom,msm-dai-cdc-dma-dev"; | |
| qcom,msm-dai-cdc-dma-dev-id = <0xb032>; | |
| phandle = <0x31f>; | |
| }; | |
| qcom,msm-dai-wsa-cdc-dma-1-tx { | |
| compatible = "qcom,msm-dai-cdc-dma-dev"; | |
| qcom,msm-dai-cdc-dma-dev-id = <0xb003>; | |
| phandle = <0x318>; | |
| }; | |
| qcom,msm-dai-wsa-cdc-dma-1-rx { | |
| compatible = "qcom,msm-dai-cdc-dma-dev"; | |
| qcom,msm-dai-cdc-dma-dev-id = <0xb002>; | |
| phandle = <0x317>; | |
| }; | |
| qcom,msm-dai-tx-cdc-dma-3-tx { | |
| compatible = "qcom,msm-dai-cdc-dma-dev"; | |
| qcom,msm-dai-cdc-dma-dev-id = <0xb037>; | |
| phandle = <0x324>; | |
| }; | |
| qcom,msm-dai-tx-cdc-dma-0-tx { | |
| compatible = "qcom,msm-dai-cdc-dma-dev"; | |
| qcom,msm-dai-cdc-dma-dev-id = <0xb031>; | |
| phandle = <0x31e>; | |
| }; | |
| }; | |
| qcom,msm-pcm-routing { | |
| compatible = "qcom,msm-pcm-routing"; | |
| phandle = <0x2ea>; | |
| }; | |
| tx_core_clk { | |
| qcom,codec-ext-clk-src = <0x07>; | |
| #clock-cells = <0x01>; | |
| compatible = "qcom,audio-ref-clk"; | |
| phandle = <0x653>; | |
| qcom,codec-lpass-clk-id = <0x30c>; | |
| qcom,codec-lpass-ext-clk-freq = <0x124f800>; | |
| }; | |
| cti@78e0000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti-apss_cti0"; | |
| compatible = "arm,primecell"; | |
| reg = <0x78e0000 0x1000>; | |
| phandle = <0x509>; | |
| }; | |
| qcom,sps { | |
| qcom,pipe-attr-ee; | |
| compatible = "qcom,msm-sps-4k"; | |
| }; | |
| cti@601a000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti10"; | |
| compatible = "arm,primecell"; | |
| reg = <0x601a000 0x1000>; | |
| phandle = <0x522>; | |
| }; | |
| qcom,cpu4-cpugrp { | |
| qcom,cpulist = <0x11 0x12 0x13 0x14>; | |
| compatible = "qcom,arm-memlat-cpugrp"; | |
| phandle = <0x367>; | |
| qcom,cpu7-cpu-l3-latmon { | |
| qcom,cachemiss-ev = <0x17>; | |
| qcom,core-dev-table = <0x493e0 0x11e1a300 0xc9900 0x249f0000 0x11df00 0x3135a800 0x168f00 0x3ca75800 0x197d00 0x493e0000 0x1f5900 0x4ef6d800 0x24ea00 0x5a688800 0x2b5c00 0x60216000>; | |
| qcom,cpulist = <0x14>; | |
| compatible = "qcom,arm-memlat-mon"; | |
| phandle = <0x369>; | |
| qcom,target-dev = <0x5b>; | |
| }; | |
| qcom,cpu4-qoslatmon { | |
| qcom,cachemiss-ev = <0x1000>; | |
| qcom,core-dev-table = <0x493e0 0x01 0x2dc6c0 0x02>; | |
| compatible = "qcom,arm-memlat-mon"; | |
| phandle = <0x36d>; | |
| qcom,target-dev = <0x5f>; | |
| }; | |
| qcom,cpu4-cpu-llcc-latmon { | |
| qcom,cachemiss-ev = <0x2a>; | |
| qcom,core-dev-table = <0x493e0 0x8f0 0xad700 0x11e1 0x101d00 0x1bc6 0x13a100 0x23c3 0x1c6b00 0x300a 0x24ea00 0x379c 0x2b5c00 0x3b9a>; | |
| compatible = "qcom,arm-memlat-mon"; | |
| phandle = <0x36a>; | |
| qcom,target-dev = <0x5c>; | |
| }; | |
| qcom,cpu4-computemon { | |
| compatible = "qcom,arm-compute-mon"; | |
| phandle = <0x36c>; | |
| qcom,target-dev = <0x5e>; | |
| ddr4-map { | |
| qcom,core-dev-table = <0x1c6b00 0x2fa 0x29e500 0xf27 0x2b5c00 0x1f2c>; | |
| qcom,ddr-type = <0x07>; | |
| }; | |
| ddr5-map { | |
| qcom,core-dev-table = <0x1c6b00 0x2fa 0x29e500 0xf27 0x2b5c00 0x28c5>; | |
| qcom,ddr-type = <0x08>; | |
| }; | |
| }; | |
| qcom,cpu4-llcc-ddr-latmon { | |
| qcom,cachemiss-ev = <0x1000>; | |
| qcom,cpulist = <0x11 0x12 0x13 0x14>; | |
| compatible = "qcom,arm-memlat-mon"; | |
| phandle = <0x36b>; | |
| qcom,target-dev = <0x5d>; | |
| ddr4-map { | |
| qcom,core-dev-table = <0x493e0 0x2fa 0xad700 0x6b8 0xc9900 0x826 0x101d00 0xb71 0x13a100 0xf27 0x180600 0x1429 0x1c6b00 0x172b 0x24ea00 0x1ae1 0x29e500 0x1f2c 0x2b5c00 0x28c5>; | |
| qcom,ddr-type = <0x07>; | |
| }; | |
| ddr5-map { | |
| qcom,core-dev-table = <0x493e0 0x2fa 0xad700 0x6b8 0xc9900 0x826 0x101d00 0xb71 0x13a100 0xf27 0x1c6b00 0x172b 0x24ea00 0x1ae1 0x29e500 0x1f2c 0x2b5c00 0x28c5>; | |
| qcom,ddr-type = <0x08>; | |
| }; | |
| }; | |
| qcom,cpu4-cpu-l3-latmon { | |
| qcom,cachemiss-ev = <0x17>; | |
| qcom,core-dev-table = <0x493e0 0x11e1a300 0xc9900 0x249f0000 0x11df00 0x3135a800 0x168f00 0x3ca75800 0x197d00 0x493e0000 0x1f5900 0x4ef6d800 0x24ea00 0x5a688800 0x2b5c00 0x60216000>; | |
| qcom,cpulist = <0x11 0x12 0x13>; | |
| compatible = "qcom,arm-memlat-mon"; | |
| phandle = <0x368>; | |
| qcom,target-dev = <0x5a>; | |
| }; | |
| }; | |
| tmc@6b05000 { | |
| arm,primecell-periphid = <0xbb961>; | |
| coresight-ctis = <0x191 0x192>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tmc-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-tmc-etf"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6b05000 0x1000>; | |
| phandle = <0x4e0>; | |
| coresight-csr = <0x193>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x194>; | |
| phandle = <0x18f>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x00>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x195>; | |
| phandle = <0x196>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,csid0@acb5200 { | |
| camss-supply = <0x253>; | |
| clock-control-debugfs = "true"; | |
| clock-names = "ife_csid_clk_src\0ife_csid_clk\0cphy_rx_clk_src\0ife_cphy_rx_clk\0ife_clk_src\0ife_clk\0ife_0_areg\0ife_0_ahb\0ife_axi_clk"; | |
| reg-names = "csid"; | |
| reg-cam-base = "\0\vR"; | |
| ife0-supply = <0x26d>; | |
| cell-index = <0x00>; | |
| interrupts = <0x00 0x1d0 0x01>; | |
| clocks = <0x6d 0x30 0x6d 0x2f 0x6d 0x0e 0x6d 0x2e 0x6d 0x2d 0x6d 0x2c 0x6d 0x2a 0x6d 0x29 0x6d 0x2b>; | |
| clock-cntl-level = "lowsvs\0svs\0svs_l1\0turbo"; | |
| compatible = "qcom,csid480"; | |
| src-clock-name = "ife_csid_clk_src"; | |
| status = "ok"; | |
| interrupt-names = "csid"; | |
| reg = <0xacb5200 0x1000>; | |
| regulator-names = "camss\0ife0"; | |
| phandle = <0x58e>; | |
| clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x14dc9380 0x00 0x5f5e100 0x00 0x00 0x17d78400 0x00 0x17d78400 0x00 0x1c4fecc0 0x00 0xbebc200 0x00 0x00 0x17d78400 0x00 0x17d78400 0x00 0x22551000 0x00 0x11e1a300 0x00 0x00 0x17d78400 0x00 0x17d78400 0x00 0x2aea5400 0x00 0x17d78400 0x00 0x00>; | |
| }; | |
| qcom,spss_utils { | |
| qcom,spss-dev-firmware-name = "spss2d"; | |
| qcom,spss-fuse4-bit = <0x01>; | |
| qcom,spss-debug-reg-addr = <0x1886020>; | |
| qcom,spss-fuse2-addr = <0x780234>; | |
| qcom,spss-fuse1-addr = <0x780234>; | |
| qcom,spss-fuse1-bit = <0x1b>; | |
| qcom,pil-size = <0xf0000>; | |
| qcom,spss-prod-firmware-name = "spss2p"; | |
| qcom,spss-emul-type-reg-addr = <0x1fc8004>; | |
| qcom,spss-fuse2-bit = <0x1a>; | |
| qcom,spss-test-firmware-name = "spss2t"; | |
| compatible = "qcom,spss-utils"; | |
| qcom,pil-addr = <0x8be00000>; | |
| status = "ok"; | |
| pil-mem = <0x86>; | |
| qcom,spss-fuse4-addr = <0x780218>; | |
| phandle = <0x396>; | |
| qcom,spss-fuse3-bit = <0x0a>; | |
| qcom,spss-fuse3-addr = <0x7801e8>; | |
| }; | |
| cti@6c13000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti-sierra_a6_cti"; | |
| compatible = "arm,primecell"; | |
| status = "disabled"; | |
| reg = <0x6c13000 0x1000>; | |
| phandle = <0x53a>; | |
| }; | |
| tpda@6ac1000 { | |
| arm,primecell-periphid = <0xbb969>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpda-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-tpda-dl-north"; | |
| qcom,dsb-elem-size = <0x00 0x20>; | |
| compatible = "arm,primecell"; | |
| qcom,tpda-atid = <0x61>; | |
| reg = <0x6ac1000 0x1000>; | |
| phandle = <0x4f4>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x1d1>; | |
| phandle = <0x1d9>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x00>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x1d2>; | |
| phandle = <0x1cf>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| boot_log_drv { | |
| second_log_offset = <0x40000>; | |
| compatible = "debug,bootlog"; | |
| status = "okay"; | |
| linux,contiguous-region = <0x48>; | |
| }; | |
| i2c@994000 { | |
| pinctrl-names = "default\0sleep"; | |
| #address-cells = <0x01>; | |
| pinctrl-0 = <0x28b>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| interrupts = <0x00 0x25e 0x04>; | |
| clocks = <0x16 0x62 0x16 0x84 0x16 0x85>; | |
| #size-cells = <0x00>; | |
| qcom,wrapper-core = <0x274>; | |
| dma-names = "tx\0rx"; | |
| compatible = "qcom,i2c-geni"; | |
| pinctrl-1 = <0x28c>; | |
| status = "disabled"; | |
| reg = <0x994000 0x4000>; | |
| phandle = <0x5a5>; | |
| dmas = <0x280 0x00 0x05 0x03 0x40 0x00 0x280 0x01 0x05 0x03 0x40 0x00>; | |
| }; | |
| qcom,msm-dai-tdm-quat-rx { | |
| qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
| qcom,msm-cpudai-tdm-data-out = <0x00>; | |
| qcom,msm-cpudai-tdm-data-delay = <0x01>; | |
| qcom,msm-cpudai-tdm-group-port-id = <0x9030>; | |
| qcom,msm-cpudai-tdm-group-num-ports = <0x01>; | |
| qcom,msm-cpudai-tdm-invert-sync = <0x01>; | |
| compatible = "qcom,msm-dai-tdm"; | |
| qcom,msm-cpudai-tdm-group-id = <0x9130>; | |
| phandle = <0x5ec>; | |
| qcom,msm-cpudai-tdm-sync-src = <0x01>; | |
| qcom,msm-cpudai-tdm-clk-internal = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-mode = <0x01>; | |
| qcom,msm-dai-q6-tdm-quat-rx-0 { | |
| qcom,msm-cpudai-tdm-dev-id = <0x9030>; | |
| qcom,msm-cpudai-tdm-data-align = <0x00>; | |
| compatible = "qcom,msm-dai-q6-tdm"; | |
| phandle = <0x30f>; | |
| }; | |
| }; | |
| cti@7020000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| cpu = <0x0d>; | |
| coresight-name = "coresight-cti-cpu0"; | |
| compatible = "arm,primecell"; | |
| reg = <0x7020000 0x1000>; | |
| phandle = <0x528>; | |
| }; | |
| ipcc-self-ping-cdsp { | |
| interrupts-extended = <0x8a 0x06 0x03 0x04>; | |
| compatible = "qcom,ipcc-self-ping"; | |
| phandle = <0x60f>; | |
| mboxes = <0x8a 0x06 0x03>; | |
| }; | |
| i2c@a84000 { | |
| pinctrl-names = "default\0sleep"; | |
| #address-cells = <0x01>; | |
| pinctrl-0 = <0x2a7>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| interrupts = <0x00 0x162 0x04>; | |
| clocks = <0x16 0x6c 0x16 0x86 0x16 0x87>; | |
| #size-cells = <0x00>; | |
| qcom,wrapper-core = <0x2a3>; | |
| dma-names = "tx\0rx"; | |
| compatible = "qcom,i2c-geni"; | |
| pinctrl-1 = <0x2a8>; | |
| status = "disabled"; | |
| reg = <0xa84000 0x4000>; | |
| phandle = <0x5b2>; | |
| dmas = <0x2a4 0x00 0x01 0x03 0x40 0x00 0x2a4 0x01 0x01 0x03 0x40 0x00>; | |
| }; | |
| qcom,mdss_dsi_pll@ae94900 { | |
| clock-names = "iface_clk"; | |
| reg-names = "pll_base\0phy_base\0gdsc_base\0dynamic_pll_base"; | |
| cell-index = <0x00>; | |
| memory-region = <0x24e>; | |
| clocks = <0x6c 0x00>; | |
| #clock-cells = <0x01>; | |
| label = "MDSS DSI 0 PLL"; | |
| compatible = "qcom,mdss_dsi_pll_7nm_v4_1"; | |
| clock-rate = <0x00>; | |
| qcom,dsi-pll-ssc-mode = "down-spread"; | |
| reg = <0xae94900 0x260 0xae94400 0x800 0xaf03000 0x08 0xae94200 0x100>; | |
| phandle = <0x55b>; | |
| qcom,dsi-pll-ssc-en; | |
| }; | |
| cti@6961000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| qcom,proxy-regs = "vddcx\0vdd"; | |
| vddcx-supply = <0x17c>; | |
| clock-names = "apb_pclk\0rbbmtimer_clk\0mem_clk\0mem_iface_clk\0gmu_clk\0gpu_cc_ahb\0l3_vote"; | |
| reg-names = "cti-base"; | |
| qcom,proxy-clks = "rbbmtimer_clk\0mem_clk\0mem_iface_clk\0gmu_clk\0gpu_cc_ahb\0l3_vote"; | |
| clocks = <0x49 0x00 0x6e 0x09 0x16 0x16 0x16 0x26 0x6e 0x03 0x6e 0x00 0x1ae 0x03>; | |
| coresight-name = "coresight-cti-gpu_isdb_cti"; | |
| vdd-supply = <0x1af>; | |
| compatible = "arm,primecell"; | |
| status = "disabled"; | |
| reg = <0x6961000 0x1000>; | |
| regulator-names = "vddcx\0vdd"; | |
| phandle = <0x531>; | |
| }; | |
| qcom,mpm2-sleep-counter@c221000 { | |
| clock-frequency = <0x8000>; | |
| compatible = "qcom,mpm2-sleep-counter"; | |
| reg = <0xc221000 0x1000>; | |
| }; | |
| qcom,cam-isp { | |
| compatible = "qcom,cam-isp"; | |
| status = "ok"; | |
| arch-compat = "ife"; | |
| }; | |
| qcom,mdss_dsi_phy0@ae94400 { | |
| qcom,platform-strength-ctrl = [55 03 55 03 55 03 55 03 55 00]; | |
| reg-names = "dsi_phy\0dyn_refresh_base"; | |
| cell-index = <0x00>; | |
| label = "dsi-phy-0"; | |
| qcom,platform-lane-config = <0xa0a 0xa0a 0xa0a 0xa0a 0x8a8a>; | |
| compatible = "qcom,dsi-phy-v4.1"; | |
| vdda-0p9-supply = <0x7c>; | |
| qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; | |
| reg = <0xae94400 0x7c0 0xae94200 0x100>; | |
| phandle = <0x559>; | |
| qcom,phy-supply-entries { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,phy-supply-entry@0 { | |
| qcom,supply-disable-load = <0x00>; | |
| qcom,supply-enable-load = <0xb3b0>; | |
| qcom,supply-name = "vdda-0p9"; | |
| qcom,supply-max-voltage = <0xd6d80>; | |
| reg = <0x00>; | |
| qcom,supply-min-voltage = <0xd6d80>; | |
| }; | |
| }; | |
| }; | |
| qcom,cam-icp { | |
| icp_pc_en; | |
| ipe_bps_pc_en; | |
| num-bps = <0x01>; | |
| num-ipe = <0x01>; | |
| num-a5 = <0x01>; | |
| compat-hw-name = "qcom,a5\0qcom,ipe0\0qcom,bps"; | |
| compatible = "qcom,cam-icp"; | |
| status = "ok"; | |
| }; | |
| llcc-pmu@9095000 { | |
| reg-names = "lagg-base"; | |
| compatible = "qcom,llcc-pmu-ver2"; | |
| reg = <0x9095000 0x300>; | |
| phandle = <0x35c>; | |
| }; | |
| funnel@6c2d000 { | |
| arm,primecell-periphid = <0xbb908>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "funnel-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-funnel-dl-center"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6c2d000 0x1000>; | |
| phandle = <0x4fa>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| source = <0x1e3>; | |
| remote-endpoint = <0x1e2>; | |
| phandle = <0x1b5>; | |
| }; | |
| }; | |
| port@14 { | |
| reg = <0x0e>; | |
| endpoint { | |
| remote-endpoint = <0x1fe>; | |
| phandle = <0x232>; | |
| }; | |
| }; | |
| port@9 { | |
| reg = <0x09>; | |
| endpoint { | |
| source = <0x1f5>; | |
| remote-endpoint = <0x1f4>; | |
| phandle = <0x1be>; | |
| }; | |
| }; | |
| port@12 { | |
| reg = <0x0c>; | |
| endpoint { | |
| source = <0x1fb>; | |
| remote-endpoint = <0x1fa>; | |
| phandle = <0x1c1>; | |
| }; | |
| }; | |
| port@7 { | |
| reg = <0x07>; | |
| endpoint { | |
| source = <0x1f1>; | |
| remote-endpoint = <0x1f0>; | |
| phandle = <0x1bc>; | |
| }; | |
| }; | |
| port@20 { | |
| reg = <0x07>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x204>; | |
| phandle = <0x206>; | |
| }; | |
| }; | |
| port@10 { | |
| reg = <0x0a>; | |
| endpoint { | |
| source = <0x1f7>; | |
| remote-endpoint = <0x1f6>; | |
| phandle = <0x1bf>; | |
| }; | |
| }; | |
| port@5 { | |
| reg = <0x05>; | |
| endpoint { | |
| source = <0x1ed>; | |
| remote-endpoint = <0x1ec>; | |
| phandle = <0x1ba>; | |
| }; | |
| }; | |
| port@19 { | |
| reg = <0x06>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x203>; | |
| phandle = <0x205>; | |
| }; | |
| }; | |
| port@3 { | |
| reg = <0x03>; | |
| endpoint { | |
| source = <0x1e9>; | |
| remote-endpoint = <0x1e8>; | |
| phandle = <0x1b8>; | |
| }; | |
| }; | |
| port@17 { | |
| reg = <0x04>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x201>; | |
| phandle = <0x225>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| source = <0x1e5>; | |
| remote-endpoint = <0x1e4>; | |
| phandle = <0x1b6>; | |
| }; | |
| }; | |
| port@15 { | |
| reg = <0x02>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x1ff>; | |
| phandle = <0x211>; | |
| }; | |
| }; | |
| port@13 { | |
| reg = <0x0d>; | |
| endpoint { | |
| source = <0x1fd>; | |
| remote-endpoint = <0x1fc>; | |
| phandle = <0x1c2>; | |
| }; | |
| }; | |
| port@8 { | |
| reg = <0x08>; | |
| endpoint { | |
| source = <0x1f3>; | |
| remote-endpoint = <0x1f2>; | |
| phandle = <0x1bd>; | |
| }; | |
| }; | |
| port@11 { | |
| reg = <0x0b>; | |
| endpoint { | |
| source = <0x1f9>; | |
| remote-endpoint = <0x1f8>; | |
| phandle = <0x1c0>; | |
| }; | |
| }; | |
| port@6 { | |
| reg = <0x06>; | |
| endpoint { | |
| source = <0x1ef>; | |
| remote-endpoint = <0x1ee>; | |
| phandle = <0x1bb>; | |
| }; | |
| }; | |
| port@4 { | |
| reg = <0x04>; | |
| endpoint { | |
| source = <0x1eb>; | |
| remote-endpoint = <0x1ea>; | |
| phandle = <0x1b9>; | |
| }; | |
| }; | |
| port@18 { | |
| reg = <0x05>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x202>; | |
| phandle = <0x1da>; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x02>; | |
| endpoint { | |
| source = <0x1e7>; | |
| remote-endpoint = <0x1e6>; | |
| phandle = <0x1b7>; | |
| }; | |
| }; | |
| port@16 { | |
| reg = <0x03>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x200>; | |
| phandle = <0x1cc>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| tpdm@78b0000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-tpdm-llm-gold"; | |
| compatible = "arm,primecell"; | |
| reg = <0x78b0000 0x1000>; | |
| phandle = <0x4fe>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x20e>; | |
| phandle = <0x20a>; | |
| }; | |
| }; | |
| }; | |
| qcom,csiphy@ac6a000 { | |
| clock-names = "cphy_rx_clk_src\0csiphy0_clk\0csi0phytimer_clk_src\0csi0phytimer_clk"; | |
| reg-names = "csiphy"; | |
| reg-cam-base = <0x6a000>; | |
| csi-vdd-voltage = <0x124f80>; | |
| cell-index = <0x00>; | |
| interrupts = <0x00 0x1dd 0x01>; | |
| clocks = <0x6d 0x0e 0x6d 0x1b 0x6d 0x10 0x6d 0x0f>; | |
| gdscr-supply = <0x253>; | |
| clock-cntl-level = "turbo"; | |
| compatible = "qcom,csiphy-v1.2.1\0qcom,csiphy"; | |
| src-clock-name = "csi0phytimer_clk_src"; | |
| mipi-csi-vdd-supply = <0x7d>; | |
| status = "ok"; | |
| interrupt-names = "csiphy"; | |
| reg = <0xac6a000 0x2000>; | |
| regulator-names = "gdscr\0refgen"; | |
| phandle = <0x55d>; | |
| refgen-supply = <0xb4>; | |
| clock-rates = <0x17d78400 0x00 0x11e1a300 0x00>; | |
| }; | |
| tpdm@6c29000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-tpdm-ipcc"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6c29000 0x1000>; | |
| phandle = <0x1fd>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x206>; | |
| phandle = <0x204>; | |
| }; | |
| }; | |
| }; | |
| tz-log@146bf720 { | |
| hyplog-address-offset = <0x410>; | |
| compatible = "qcom,tz-log"; | |
| qcom,hyplog-enabled; | |
| reg = <0x146bf720 0x3000>; | |
| phandle = <0x3a3>; | |
| hyplog-size-offset = <0x414>; | |
| }; | |
| qcom,vidc@aa00000 { | |
| qcom,allowed-clock-rates = <0xe4e1bff 0x14257880 0x15d0b780 0x1a76e700>; | |
| iris-ctl-supply = <0x99>; | |
| #address-cells = <0x01>; | |
| sku-index = <0x00>; | |
| clock-names = "gcc_video_axi0\0core_clk\0vcodec_clk"; | |
| resets = <0x16 0x2b 0x6b 0x02>; | |
| vcodec-supply = <0x32e>; | |
| interrupts = <0x00 0xae 0x04>; | |
| clocks = <0x16 0xce 0x6b 0x05 0x6b 0x02>; | |
| #size-cells = <0x01>; | |
| qcom,reg-presets = <0xb0088 0x00>; | |
| compatible = "qcom,msm-vidc\0qcom,kona-vidc"; | |
| status = "ok"; | |
| reg = <0xaa00000 0x100000>; | |
| phandle = <0x603>; | |
| qcom,proxy-clock-names = "gcc_video_axi0\0core_clk\0vcodec_clk"; | |
| reset-names = "video_axi_reset\0video_core_reset"; | |
| qcom,clock-configs = <0x00 0x01 0x01>; | |
| cache-slice-names = "vidsc0"; | |
| venus_bus_ddr { | |
| label = "venus-ddr"; | |
| compatible = "qcom,msm-vidc,bus"; | |
| qcom,bus-slave = <0x200>; | |
| qcom,bus-master = <0x81>; | |
| qcom,mode = "venus-ddr"; | |
| qcom,bus-range-kbps = <0x2fa 0xe4e1c0>; | |
| }; | |
| venus_bus_llcc { | |
| label = "venus-llcc"; | |
| compatible = "qcom,msm-vidc,bus"; | |
| qcom,bus-slave = <0x302>; | |
| qcom,bus-master = <0x3f>; | |
| qcom,mode = "venuc-llcc"; | |
| qcom,bus-range-kbps = <0x8f0 0xe4e1c0>; | |
| }; | |
| non_secure_cb { | |
| iommus = <0x47 0x2100 0x400>; | |
| virtual-addr-pool = <0x25800000 0xba800000>; | |
| label = "venus_ns"; | |
| compatible = "qcom,msm-vidc,context-bank"; | |
| qcom,iommu-dma-addr-pool = <0x25800000 0xba800000>; | |
| qcom,iommu-pagetable = "LLC"; | |
| buffer-types = <0xfff>; | |
| qcom,iommu-faults = "non-fatal"; | |
| }; | |
| secure_non_pixel_cb { | |
| iommus = <0x47 0x2104 0x400>; | |
| qcom,secure-context-bank; | |
| virtual-addr-pool = <0x1000000 0x24800000>; | |
| label = "venus_sec_non_pixel"; | |
| compatible = "qcom,msm-vidc,context-bank"; | |
| qcom,iommu-dma-addr-pool = <0x1000000 0x24800000>; | |
| qcom,iommu-pagetable = "LLC"; | |
| buffer-types = <0x480>; | |
| qcom,iommu-faults = "non-fatal"; | |
| qcom,iommu-vmid = <0x0b>; | |
| }; | |
| bus_cnoc { | |
| label = "cnoc"; | |
| compatible = "qcom,msm-vidc,bus"; | |
| qcom,bus-slave = <0x254>; | |
| qcom,bus-master = <0x01>; | |
| qcom,mode = "performance"; | |
| qcom,bus-range-kbps = <0x2fa 0x2fa>; | |
| }; | |
| secure_bitstream_cb { | |
| iommus = <0x47 0x2101 0x404>; | |
| qcom,secure-context-bank; | |
| virtual-addr-pool = <0x500000 0xdfb00000>; | |
| label = "venus_sec_bitstream"; | |
| compatible = "qcom,msm-vidc,context-bank"; | |
| qcom,iommu-dma-addr-pool = <0x500000 0xdfb00000>; | |
| qcom,iommu-pagetable = "LLC"; | |
| buffer-types = <0x241>; | |
| qcom,iommu-faults = "non-fatal"; | |
| qcom,iommu-vmid = <0x09>; | |
| }; | |
| secure_pixel_cb { | |
| iommus = <0x47 0x2103 0x400>; | |
| qcom,secure-context-bank; | |
| virtual-addr-pool = <0x500000 0xdfb00000>; | |
| label = "venus_sec_pixel"; | |
| compatible = "qcom,msm-vidc,context-bank"; | |
| qcom,iommu-dma-addr-pool = <0x500000 0xdfb00000>; | |
| qcom,iommu-pagetable = "LLC"; | |
| buffer-types = <0x106>; | |
| qcom,iommu-faults = "non-fatal"; | |
| qcom,iommu-vmid = <0x0a>; | |
| }; | |
| }; | |
| qcom,gdsc@abf0bf8 { | |
| clock-names = "ahb_clk"; | |
| qcom,msm-bus,name = "mvs0c_gdsc_ahb"; | |
| parent-supply = <0x69>; | |
| qcom,retain-regs; | |
| clocks = <0x16 0xcd>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| regulator-name = "mvs0c_gdsc"; | |
| vdd_parent-supply = <0x69>; | |
| compatible = "qcom,gdsc"; | |
| reg = <0xabf0bf8 0x04>; | |
| phandle = <0x99>; | |
| qcom,msm-bus,vectors-KBps = <0x01 0x254 0x00 0x00 0x01 0x254 0x00 0x01>; | |
| }; | |
| ssphy@88eb000 { | |
| qcom,vbus-valid-override; | |
| qcom,vdd-voltage-level = <0x00 0xdea80 0xdea80>; | |
| clock-names = "aux_clk\0pipe_clk\0pipe_clk_mux\0pipe_clk_ext_src\0ref_clk_src\0ref_clk\0com_aux_clk"; | |
| reg-names = "qmp_phy_base\0pcs_clamp_enable_reg"; | |
| resets = <0x16 0x27 0x16 0x29>; | |
| clocks = <0x16 0xc8 0x16 0xcb 0x16 0xcc 0x16 0x02 0x15 0x00 0x16 0xc7 0x16 0xca>; | |
| vdd-supply = <0x187>; | |
| qcom,qmp-phy-reg-offset = <0x814 0xe08 0xe14 0x840 0x800 0x844>; | |
| compatible = "qcom,usb-ssphy-qmp-v2"; | |
| qcom,vdd-max-load-uA = <0xb798>; | |
| reg = <0x88eb000 0x1000 0x88eb88c 0x04>; | |
| phandle = <0x18a>; | |
| reset-names = "phy_reset\0phy_phy_reset"; | |
| qcom,qmp-phy-init-seq = <0x94 0x1a 0x00 0x1bc 0x11 0x00 0x158 0x01 0x00 0xbc 0x82 0x00 0xcc 0xab 0x00 0xd0 0xea 0x00 0xd4 0x02 0x00 0x1ac 0xca 0x00 0x1b0 0x1e 0x00 0x74 0x06 0x00 0x7c 0x16 0x00 0x84 0x36 0x00 0x110 0x24 0x00 0xb0 0x34 0x00 0xac 0x14 0x00 0xa4 0x04 0x00 0x50 0x0a 0x00 0x11c 0x02 0x00 0x118 0x24 0x00 0x16c 0x08 0x00 0xc4 0x82 0x00 0xd8 0xab 0x00 0xdc 0xea 0x00 0xe0 0x02 0x00 0xb8 0x82 0x00 0xb4 0x34 0x00 0x78 0x06 0x00 0x80 0x16 0x00 0x88 0x36 0x00 0x1b4 0xca 0x00 0x1b8 0x1e 0x00 0x60 0x20 0x00 0x10 0x01 0x00 0x1c 0x31 0x00 0x20 0x01 0x00 0x30 0xde 0x00 0x34 0x07 0x00 0x24 0xde 0x00 0x28 0x07 0x00 0x10c 0x02 0x00 0x580 0xb8 0x00 0x57c 0xff 0x00 0x578 0xbf 0x00 0x574 0x7f 0x00 0x570 0x7f 0x00 0x594 0xb4 0x00 0x590 0x7b 0x00 0x58c 0x5c 0x00 0x588 0xdc 0x00 0x584 0xdc 0x00 0x444 0x99 0x00 0x44c 0x04 0x00 0x450 0x08 0x00 0x454 0x05 0x00 0x458 0x05 0x00 0x430 0x2f 0x00 0x43c 0xff 0x00 0x440 0x0f 0x00 0x434 0x7f 0x00 0x408 0x0a 0x00 0x4d4 0x54 0x00 0x4d8 0x0c 0x00 0x4ec 0x0f 0x00 0x4f0 0x4a 0x00 0x4f4 0x0a 0x00 0x5b4 0x04 0x00 0x510 0x47 0x00 0x514 0x80 0x00 0x51c 0x04 0x00 0x524 0x0e 0x00 0x4fc 0x00 0x00 0x4f8 0xc0 0x00 0x5b8 0x38 0x00 0x414 0x06 0x00 0x5bc 0x0c 0x00 0x4dc 0x1f 0x00 0x29c 0x12 0x00 0x284 0xd5 0x00 0x288 0x82 0x00 0x304 0x40 0x00 0x23c 0x11 0x00 0x240 0x02 0x00 0x8c4 0xd0 0x00 0x8c8 0x07 0x00 0x8cc 0x20 0x00 0x8d8 0x13 0x00 0x990 0xe7 0x00 0x994 0x03 0x00 0x988 0xa9 0x00 0x9d0 0x0c 0x00 0xe38 0x07 0x00 0xe18 0xf8 0x00 0x9b0 0x0a 0x00 0x9c0 0x88 0x00 0x9c4 0x13 0x00 0x9dc 0x4b 0x00 0x9ec 0x10 0x00 0x8dc 0x21 0x00 0xffffffff 0xffffffff 0x00>; | |
| core-supply = <0x7d>; | |
| }; | |
| cti@698b000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti-turing_q6_cti"; | |
| compatible = "arm,primecell"; | |
| reg = <0x698b000 0x1000>; | |
| phandle = <0x542>; | |
| }; | |
| llcc-bw-opp-table { | |
| compatible = "operating-points-v2"; | |
| phandle = <0x4b>; | |
| opp-1000 { | |
| opp-hz = <0x00 0x3b9a>; | |
| }; | |
| opp-300 { | |
| opp-hz = <0x00 0x11e1>; | |
| }; | |
| opp-600 { | |
| opp-hz = <0x00 0x23c3>; | |
| }; | |
| opp-806 { | |
| opp-hz = <0x00 0x300a>; | |
| }; | |
| opp-466 { | |
| opp-hz = <0x00 0x1bc6>; | |
| }; | |
| opp-933 { | |
| opp-hz = <0x00 0x379c>; | |
| }; | |
| opp-150 { | |
| opp-hz = <0x00 0x8f0>; | |
| }; | |
| }; | |
| qcom,msm-pcm-dtmf { | |
| compatible = "qcom,msm-pcm-dtmf"; | |
| phandle = <0x5d0>; | |
| }; | |
| qcom,cpu4-cpu-llcc-lat { | |
| qcom,src-dst-ports = <0x01 0x302>; | |
| governor = "performance"; | |
| compatible = "qcom,devbw"; | |
| phandle = <0x5c>; | |
| qcom,active-only; | |
| operating-points-v2 = <0x4b>; | |
| }; | |
| mem_dump { | |
| memory-region = <0xa1>; | |
| compatible = "qcom,mem-dump"; | |
| c700_scandump { | |
| qcom,dump-size = <0x1a4c0>; | |
| qcom,dump-id = <0x137>; | |
| }; | |
| l1_icache600 { | |
| qcom,dump-size = <0x26000>; | |
| qcom,dump-id = <0x66>; | |
| }; | |
| l2_cache600 { | |
| qcom,dump-size = <0x68000>; | |
| qcom,dump-id = <0xc6>; | |
| }; | |
| l1_itlb400 { | |
| qcom,dump-size = <0x300>; | |
| qcom,dump-id = <0x24>; | |
| }; | |
| l1_dtlb600 { | |
| qcom,dump-size = <0x480>; | |
| qcom,dump-id = <0x46>; | |
| }; | |
| c400_context { | |
| qcom,dump-size = <0x800>; | |
| qcom,dump-id = <0x04>; | |
| }; | |
| l2_tlb400 { | |
| qcom,dump-size = <0x7800>; | |
| qcom,dump-id = <0x124>; | |
| }; | |
| osm_reg { | |
| qcom,dump-size = <0x400>; | |
| qcom,dump-id = <0x163>; | |
| }; | |
| l1_dcache300 { | |
| qcom,dump-size = <0x9000>; | |
| qcom,dump-id = <0x83>; | |
| }; | |
| etflpass_reg { | |
| qcom,dump-size = <0x1000>; | |
| qcom,dump-id = <0x104>; | |
| }; | |
| l1_itlb700 { | |
| qcom,dump-size = <0x300>; | |
| qcom,dump-id = <0x27>; | |
| }; | |
| l2_tlb700 { | |
| qcom,dump-size = <0x7800>; | |
| qcom,dump-id = <0x127>; | |
| }; | |
| c0_context { | |
| qcom,dump-size = <0x800>; | |
| qcom,dump-id = <0x00>; | |
| }; | |
| l1_dcache600 { | |
| qcom,dump-size = <0x1a000>; | |
| qcom,dump-id = <0x86>; | |
| }; | |
| c500_scandump { | |
| qcom,dump-size = <0x1a4c0>; | |
| qcom,dump-id = <0x135>; | |
| }; | |
| fsm_data { | |
| qcom,dump-size = <0x400>; | |
| qcom,dump-id = <0x165>; | |
| }; | |
| l1_icache200 { | |
| qcom,dump-size = <0x10800>; | |
| qcom,dump-id = <0x62>; | |
| }; | |
| c200_context { | |
| qcom,dump-size = <0x800>; | |
| qcom,dump-id = <0x02>; | |
| }; | |
| c700_context { | |
| qcom,dump-size = <0x800>; | |
| qcom,dump-id = <0x07>; | |
| }; | |
| c0_scandump { | |
| qcom,dump-size = <0x10100>; | |
| qcom,dump-id = <0x130>; | |
| }; | |
| l1_icache500 { | |
| qcom,dump-size = <0x26000>; | |
| qcom,dump-id = <0x65>; | |
| }; | |
| fcm { | |
| qcom,dump-size = <0x8400>; | |
| qcom,dump-id = <0xee>; | |
| }; | |
| l2_cache500 { | |
| qcom,dump-size = <0x68000>; | |
| qcom,dump-id = <0xc5>; | |
| }; | |
| rpm_sw { | |
| qcom,dump-size = <0x28000>; | |
| qcom,dump-id = <0xea>; | |
| }; | |
| l1_dtlb500 { | |
| qcom,dump-size = <0x480>; | |
| qcom,dump-id = <0x45>; | |
| }; | |
| l2_tlb300 { | |
| qcom,dump-size = <0x6000>; | |
| qcom,dump-id = <0x123>; | |
| }; | |
| etfswao_reg { | |
| qcom,dump-size = <0x1000>; | |
| qcom,dump-id = <0x102>; | |
| }; | |
| c300_scandump { | |
| qcom,dump-size = <0x10100>; | |
| qcom,dump-id = <0x133>; | |
| }; | |
| l1_dcache0 { | |
| qcom,dump-size = <0x9000>; | |
| qcom,dump-id = <0x80>; | |
| }; | |
| l1_dcache200 { | |
| qcom,dump-size = <0x9000>; | |
| qcom,dump-id = <0x82>; | |
| }; | |
| l2_tlb0 { | |
| qcom,dump-size = <0x6000>; | |
| qcom,dump-id = <0x120>; | |
| }; | |
| l1_itlb600 { | |
| qcom,dump-size = <0x300>; | |
| qcom,dump-id = <0x26>; | |
| }; | |
| l2_tlb600 { | |
| qcom,dump-size = <0x7800>; | |
| qcom,dump-id = <0x126>; | |
| }; | |
| etr_reg { | |
| qcom,dump-size = <0x1000>; | |
| qcom,dump-id = <0x100>; | |
| }; | |
| c500_context { | |
| qcom,dump-size = <0x800>; | |
| qcom,dump-id = <0x05>; | |
| }; | |
| gemnoc { | |
| qcom,dump-size = <0x100000>; | |
| qcom,dump-id = <0x162>; | |
| }; | |
| l1_dcache500 { | |
| qcom,dump-size = <0x1a000>; | |
| qcom,dump-id = <0x85>; | |
| }; | |
| pmic { | |
| qcom,dump-size = <0x80000>; | |
| qcom,dump-id = <0xe4>; | |
| }; | |
| l1_icache100 { | |
| qcom,dump-size = <0x10800>; | |
| qcom,dump-id = <0x61>; | |
| }; | |
| c100_scandump { | |
| qcom,dump-size = <0x10100>; | |
| qcom,dump-id = <0x131>; | |
| }; | |
| etf_slpi { | |
| qcom,dump-size = <0x4000>; | |
| qcom,dump-id = <0xf3>; | |
| }; | |
| mhm_scan { | |
| qcom,dump-size = <0x20000>; | |
| qcom,dump-id = <0x161>; | |
| }; | |
| c600_scandump { | |
| qcom,dump-size = <0x1a4c0>; | |
| qcom,dump-id = <0x136>; | |
| }; | |
| l1_icache400 { | |
| qcom,dump-size = <0x26000>; | |
| qcom,dump-id = <0x64>; | |
| }; | |
| etfslpi_reg { | |
| qcom,dump-size = <0x1000>; | |
| qcom,dump-id = <0x103>; | |
| }; | |
| l2_cache400 { | |
| qcom,dump-size = <0x68000>; | |
| qcom,dump-id = <0xc4>; | |
| }; | |
| c300_context { | |
| qcom,dump-size = <0x800>; | |
| qcom,dump-id = <0x03>; | |
| }; | |
| l1_dtlb400 { | |
| qcom,dump-size = <0x480>; | |
| qcom,dump-id = <0x44>; | |
| }; | |
| l2_tlb200 { | |
| qcom,dump-size = <0x6000>; | |
| qcom,dump-id = <0x122>; | |
| }; | |
| l1_dcache100 { | |
| qcom,dump-size = <0x9000>; | |
| qcom,dump-id = <0x81>; | |
| }; | |
| etf_swao { | |
| qcom,dump-size = <0x10000>; | |
| qcom,dump-id = <0xf1>; | |
| }; | |
| cpuss_reg { | |
| qcom,dump-size = <0x30000>; | |
| qcom,dump-id = <0xef>; | |
| }; | |
| l1_icache700 { | |
| qcom,dump-size = <0x26000>; | |
| qcom,dump-id = <0x67>; | |
| }; | |
| pcu_reg { | |
| qcom,dump-size = <0x400>; | |
| qcom,dump-id = <0x164>; | |
| }; | |
| l2_cache700 { | |
| qcom,dump-size = <0xd0000>; | |
| qcom,dump-id = <0xc7>; | |
| }; | |
| l1_itlb500 { | |
| qcom,dump-size = <0x300>; | |
| qcom,dump-id = <0x25>; | |
| }; | |
| l1_dtlb700 { | |
| qcom,dump-size = <0x480>; | |
| qcom,dump-id = <0x47>; | |
| }; | |
| l2_tlb500 { | |
| qcom,dump-size = <0x7800>; | |
| qcom,dump-id = <0x125>; | |
| }; | |
| l1_icache0 { | |
| qcom,dump-size = <0x10800>; | |
| qcom,dump-id = <0x60>; | |
| }; | |
| misc_data { | |
| qcom,dump-size = <0x1000>; | |
| qcom,dump-id = <0xe8>; | |
| }; | |
| c400_scandump { | |
| qcom,dump-size = <0x1a4c0>; | |
| qcom,dump-id = <0x134>; | |
| }; | |
| l1_dcache400 { | |
| qcom,dump-size = <0x1a000>; | |
| qcom,dump-id = <0x84>; | |
| }; | |
| etf_lpass { | |
| qcom,dump-size = <0x4000>; | |
| qcom,dump-id = <0xf4>; | |
| }; | |
| c100_context { | |
| qcom,dump-size = <0x800>; | |
| qcom,dump-id = <0x01>; | |
| }; | |
| c600_context { | |
| qcom,dump-size = <0x800>; | |
| qcom,dump-id = <0x06>; | |
| }; | |
| rpmh { | |
| qcom,dump-size = <0x2000000>; | |
| qcom,dump-id = <0xec>; | |
| }; | |
| l1_dcache700 { | |
| qcom,dump-size = <0x1a000>; | |
| qcom,dump-id = <0x87>; | |
| }; | |
| l1_icache300 { | |
| qcom,dump-size = <0x10800>; | |
| qcom,dump-id = <0x63>; | |
| }; | |
| l2_tlb100 { | |
| qcom,dump-size = <0x6000>; | |
| qcom,dump-id = <0x121>; | |
| }; | |
| c200_scandump { | |
| qcom,dump-size = <0x10100>; | |
| qcom,dump-id = <0x132>; | |
| }; | |
| }; | |
| qcom,msm-pcm { | |
| qcom,msm-pcm-dsp-id = <0x00>; | |
| compatible = "qcom,msm-pcm-dsp"; | |
| phandle = <0x2e0>; | |
| }; | |
| qoslat-opp-table { | |
| compatible = "operating-points-v2"; | |
| phandle = <0x56>; | |
| opp-1 { | |
| opp-hz = <0x00 0x02>; | |
| }; | |
| opp-0 { | |
| opp-hz = <0x00 0x01>; | |
| }; | |
| }; | |
| dsi_panel_pwr_supply_avdd { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| phandle = <0x6e7>; | |
| qcom,panel-supply-entry@1 { | |
| qcom,supply-disable-load = <0x64>; | |
| qcom,supply-enable-load = <0x186a0>; | |
| qcom,supply-name = "avdd"; | |
| qcom,supply-max-voltage = <0x5b8d80>; | |
| reg = <0x01>; | |
| qcom,supply-min-voltage = <0x4630c0>; | |
| }; | |
| qcom,panel-supply-entry@0 { | |
| qcom,supply-disable-load = <0x50>; | |
| qcom,supply-enable-load = <0xf230>; | |
| qcom,supply-post-on-sleep = <0x14>; | |
| qcom,supply-name = "vddio"; | |
| qcom,supply-max-voltage = <0x1b7740>; | |
| reg = <0x00>; | |
| qcom,supply-min-voltage = <0x1b7740>; | |
| }; | |
| }; | |
| qcom,msm-sec-auxpcm { | |
| qcom,msm-cpudai-auxpcm-quant = <0x02 0x02>; | |
| qcom,msm-cpudai-auxpcm-frame = <0x05 0x04>; | |
| qcom,msm-cpudai-auxpcm-sync = <0x01 0x01>; | |
| qcom,msm-auxpcm-interface = "secondary"; | |
| qcom,msm-cpudai-auxpcm-slot-mapping = <0x01 0x01>; | |
| qcom,msm-cpudai-auxpcm-data = <0x00 0x00>; | |
| qcom,msm-cpudai-afe-clk-ver = <0x02>; | |
| qcom,msm-cpudai-auxpcm-num-slots = <0x01 0x01>; | |
| compatible = "qcom,msm-auxpcm-dev"; | |
| qcom,msm-cpudai-auxpcm-mode = <0x00 0x00>; | |
| phandle = <0x2f6>; | |
| qcom,msm-cpudai-auxpcm-pcm-clk-rate = <0x1f4000 0x1f4000>; | |
| }; | |
| cti@7620000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| cpu = <0x13>; | |
| coresight-name = "coresight-cti-cpu6"; | |
| compatible = "arm,primecell"; | |
| reg = <0x7620000 0x1000>; | |
| phandle = <0x52e>; | |
| }; | |
| tpdm@6850000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-tpdm-pimem"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6850000 0x1000>; | |
| phandle = <0x4f0>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x1cb>; | |
| phandle = <0x1c7>; | |
| }; | |
| }; | |
| }; | |
| qcom,gdsc@ad0b004 { | |
| clock-names = "ahb_clk"; | |
| qcom,msm-bus,name = "ife_1_gdsc_ahb"; | |
| parent-supply = <0x69>; | |
| qcom,retain-regs; | |
| clocks = <0x16 0x0b>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| regulator-name = "ife_1_gdsc"; | |
| vdd_parent-supply = <0x69>; | |
| compatible = "qcom,gdsc"; | |
| reg = <0xad0b004 0x04>; | |
| phandle = <0x26e>; | |
| qcom,msm-bus,vectors-KBps = <0x01 0x24d 0x00 0x00 0x01 0x24d 0x00 0x01>; | |
| }; | |
| cti@7900000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti-apss_cti2"; | |
| compatible = "arm,primecell"; | |
| reg = <0x7900000 0x1000>; | |
| phandle = <0x50b>; | |
| }; | |
| qcom,cam-res-mgr { | |
| compatible = "qcom,cam-res-mgr"; | |
| status = "ok"; | |
| }; | |
| spi@890000 { | |
| pinctrl-names = "default\0sleep"; | |
| #address-cells = <0x01>; | |
| pinctrl-0 = <0x2da>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| reg-names = "se_phys"; | |
| interrupts = <0x00 0x24a 0x04>; | |
| clocks = <0x16 0x80 0x16 0x88 0x16 0x89>; | |
| #size-cells = <0x00>; | |
| qcom,wrapper-core = <0x2bf>; | |
| spi-max-frequency = <0x2faf080>; | |
| dma-names = "tx\0rx"; | |
| compatible = "qcom,spi-geni"; | |
| pinctrl-1 = <0x2db>; | |
| status = "disabled"; | |
| reg = <0x890000 0x4000>; | |
| phandle = <0x5ca>; | |
| dmas = <0x2c2 0x00 0x04 0x01 0x40 0x00 0x2c2 0x01 0x04 0x01 0x40 0x00>; | |
| }; | |
| qcom,csiphy@ac72000 { | |
| clock-names = "cphy_rx_clk_src\0csiphy4_clk\0csi4phytimer_clk_src\0csi4phytimer_clk"; | |
| reg-names = "csiphy"; | |
| reg-cam-base = "\0\a "; | |
| csi-vdd-voltage = <0x124f80>; | |
| cell-index = <0x04>; | |
| interrupts = <0x00 0x56 0x01>; | |
| clocks = <0x6d 0x0e 0x6d 0x1f 0x6d 0x18 0x6d 0x17>; | |
| gdscr-supply = <0x253>; | |
| clock-cntl-level = "turbo"; | |
| compatible = "qcom,csiphy-v1.2.1\0qcom,csiphy"; | |
| src-clock-name = "csi4phytimer_clk_src"; | |
| mipi-csi-vdd-supply = <0x7d>; | |
| status = "ok"; | |
| interrupt-names = "csiphy"; | |
| reg = <0xac72000 0x2000>; | |
| regulator-names = "gdscr\0refgen"; | |
| phandle = <0x561>; | |
| refgen-supply = <0xb4>; | |
| clock-rates = <0x17d78400 0x00 0x11e1a300 0x00>; | |
| }; | |
| cti@6017000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti7"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6017000 0x1000>; | |
| phandle = <0x51f>; | |
| }; | |
| cti@6b21000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti-lpass_lpi_cti"; | |
| compatible = "arm,primecell"; | |
| status = "disabled"; | |
| reg = <0x6b21000 0x1000>; | |
| phandle = <0x534>; | |
| }; | |
| qcom,msm-dai-mi2s { | |
| compatible = "qcom,msm-dai-mi2s"; | |
| phandle = <0x5d1>; | |
| qcom,msm-dai-q6-mi2s-prim { | |
| pinctrl-0 = <0x44a 0x44c 0x44e 0x450>; | |
| qcom,msm-dai-q6-mi2s-dev-id = <0x00>; | |
| qcom,msm-mi2s-rx-lines = <0x02>; | |
| qcom,msm-mi2s-tx-lines = <0x01>; | |
| compatible = "qcom,msm-dai-q6-mi2s"; | |
| pinctrl-1 = <0x449 0x44b 0x44d 0x44f>; | |
| status = "okay"; | |
| phandle = <0x2ef>; | |
| }; | |
| qcom,msm-dai-q6-mi2s-quin { | |
| qcom,msm-dai-q6-mi2s-dev-id = <0x04>; | |
| qcom,msm-mi2s-rx-lines = <0x01>; | |
| qcom,msm-mi2s-tx-lines = <0x02>; | |
| compatible = "qcom,msm-dai-q6-mi2s"; | |
| phandle = <0x2f3>; | |
| }; | |
| qcom,msm-dai-q6-mi2s-senary { | |
| qcom,msm-dai-q6-mi2s-dev-id = <0x05>; | |
| qcom,msm-mi2s-rx-lines = <0x00>; | |
| qcom,msm-mi2s-tx-lines = <0x03>; | |
| compatible = "qcom,msm-dai-q6-mi2s"; | |
| phandle = <0x2f4>; | |
| }; | |
| qcom,msm-dai-q6-mi2s-quat { | |
| qcom,msm-dai-q6-mi2s-dev-id = <0x03>; | |
| qcom,msm-mi2s-rx-lines = <0x01>; | |
| qcom,msm-mi2s-tx-lines = <0x02>; | |
| compatible = "qcom,msm-dai-q6-mi2s"; | |
| phandle = <0x2f2>; | |
| }; | |
| qcom,msm-dai-q6-mi2s-tert { | |
| pinctrl-0 = <0x45c 0x45e 0x460 0x462>; | |
| qcom,msm-dai-q6-mi2s-dev-id = <0x02>; | |
| qcom,msm-mi2s-rx-lines = <0x02>; | |
| qcom,msm-mi2s-tx-lines = <0x01>; | |
| compatible = "qcom,msm-dai-q6-mi2s"; | |
| pinctrl-1 = <0x45b 0x45d 0x45f 0x461>; | |
| status = "okay"; | |
| phandle = <0x2f1>; | |
| }; | |
| qcom,msm-dai-q6-mi2s-sec { | |
| qcom,msm-dai-q6-mi2s-dev-id = <0x01>; | |
| qcom,msm-mi2s-rx-lines = <0x01>; | |
| qcom,msm-mi2s-tx-lines = <0x00>; | |
| compatible = "qcom,msm-dai-q6-mi2s"; | |
| phandle = <0x2f0>; | |
| }; | |
| }; | |
| i2c@88c000 { | |
| pinctrl-names = "default\0sleep"; | |
| #address-cells = <0x01>; | |
| pinctrl-0 = <0x2cc>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| interrupts = <0x00 0x249 0x04>; | |
| clocks = <0x16 0x7e 0x16 0x88 0x16 0x89>; | |
| #size-cells = <0x00>; | |
| qcom,wrapper-core = <0x2bf>; | |
| dma-names = "tx\0rx"; | |
| compatible = "qcom,i2c-geni"; | |
| pinctrl-1 = <0x2cd>; | |
| status = "disabled"; | |
| reg = <0x88c000 0x4000>; | |
| phandle = <0x5c3>; | |
| dmas = <0x2c2 0x00 0x03 0x03 0x40 0x00 0x2c2 0x01 0x03 0x03 0x40 0x00>; | |
| }; | |
| gpio_keys { | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x694>; | |
| label = "gpio-keys"; | |
| compatible = "gpio-keys"; | |
| vol_up { | |
| linux,can-disable; | |
| label = "volume_up"; | |
| linux,input-type = <0x01>; | |
| gpio-key,wakeup; | |
| linux,code = <0x73>; | |
| debounce-interval = <0x0f>; | |
| gpios = <0x695 0x06 0x01>; | |
| }; | |
| }; | |
| qcom,ife0@acb4000 { | |
| camss-supply = <0x253>; | |
| clock-control-debugfs = "true"; | |
| clock-names = "ife_0_ahb\0ife_0_areg\0ife_clk_src\0ife_clk\0ife_axi_clk"; | |
| clocks-option = <0x6d 0x31>; | |
| reg-names = "ife\0cam_camnoc"; | |
| clock-rates-option = <0x2aea5400>; | |
| reg-cam-base = <0xb4000 0x42000>; | |
| ife0-supply = <0x26d>; | |
| cell-index = <0x00>; | |
| interrupts = <0x00 0x1d1 0x01>; | |
| clocks = <0x6d 0x29 0x6d 0x2a 0x6d 0x2d 0x6d 0x2c 0x6d 0x2b>; | |
| ubwc-static-cfg = <0x1026 0x1036>; | |
| clock-cntl-level = "lowsvs\0svs\0svs_l1\0turbo"; | |
| compatible = "qcom,vfe480"; | |
| src-clock-name = "ife_clk_src"; | |
| status = "ok"; | |
| clock-names-option = "ife_dsp_clk"; | |
| interrupt-names = "ife"; | |
| scl-clk-names = "ife_0_areg"; | |
| reg = <0xacb4000 0xd000 0xac42000 0x8000>; | |
| regulator-names = "camss\0ife0"; | |
| phandle = <0x58f>; | |
| clock-rates = <0x00 0x5f5e100 0x14dc9380 0x00 0x00 0x00 0xbebc200 0x1c4fecc0 0x00 0x00 0x00 0x11e1a300 0x22551000 0x00 0x00 0x00 0x17d78400 0x2aea5400 0x00 0x00>; | |
| }; | |
| msm_tspp@8880000 { | |
| iommus = <0x47 0xa0 0x00>; | |
| pinctrl-4 = <0xb2 0xb3>; | |
| pinctrl-names = "disabled\0tsif0-mode1\0tsif0-mode2\0tsif1-mode1\0tsif1-mode2\0dual-tsif-mode1\0dual-tsif-mode2"; | |
| pinctrl-2 = <0xb0 0xb1>; | |
| pinctrl-0; | |
| clock-names = "iface_clk\0ref_clk"; | |
| reg-names = "MSM_TSIF0_PHYS\0MSM_TSIF1_PHYS\0MSM_TSPP_PHYS\0MSM_TSPP_BAM_PHYS"; | |
| qcom,msm-bus,name = "tsif"; | |
| memory-region = <0x60>; | |
| interrupts = <0x00 0x79 0x04 0x00 0x77 0x04 0x00 0x78 0x04 0x00 0x7a 0x04>; | |
| clocks = <0x16 0x91 0x16 0x93>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| pinctrl-5 = <0xb0 0xb2>; | |
| pinctrl-3 = <0xb2>; | |
| compatible = "qcom,msm_tspp"; | |
| pinctrl-1 = <0xb0>; | |
| interrupt-names = "TSIF_TSPP_IRQ\0TSIF0_IRQ\0TSIF1_IRQ\0TSIF_BAM_IRQ"; | |
| qcom,iommu-dma-addr-pool = <0x10000000 0x40000000>; | |
| reg = <0x88a7000 0x200 0x88a8000 0x200 0x88a9000 0x1000 0x8884000 0x23000>; | |
| phandle = <0x3a8>; | |
| qcom,msm-bus,vectors-KBps = <0x52 0x200 0x00 0x00 0x52 0x200 0x3000 0x6000>; | |
| qcom,smmu-s1-enable; | |
| pinctrl-6 = <0xb0 0xb1 0xb2 0xb3>; | |
| }; | |
| qcom,lpm-levels { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,lpm-levels"; | |
| qcom,pm-cluster@0 { | |
| qcom,psci-mode-mask = <0xfff>; | |
| #address-cells = <0x01>; | |
| qcom,clstr-tmr-add = <0x3e8>; | |
| #size-cells = <0x00>; | |
| label = "L3"; | |
| qcom,psci-mode-shift = <0x04>; | |
| reg = <0x00>; | |
| qcom,pm-cpu@1 { | |
| qcom,psci-mode-mask = <0x0f>; | |
| #address-cells = <0x01>; | |
| qcom,cpu = <0x11 0x12 0x13 0x14>; | |
| #size-cells = <0x00>; | |
| qcom,psci-mode-shift = <0x00>; | |
| reg = <0x01>; | |
| qcom,disable-ipi-prediction; | |
| qcom,pm-cpu-level@2 { | |
| qcom,exit-latency-us = <0x2b>; | |
| qcom,psci-cpu-mode = <0x01>; | |
| label = "wfi"; | |
| qcom,min-residency-us = <0x53>; | |
| reg = <0x02>; | |
| qcom,entry-latency-us = <0x39>; | |
| }; | |
| qcom,pm-cpu-level@3 { | |
| qcom,exit-latency-us = <0x425>; | |
| qcom,is-reset; | |
| qcom,psci-cpu-mode = <0x04>; | |
| label = "rail-pc"; | |
| qcom,use-broadcast-timer; | |
| qcom,min-residency-us = <0x1188>; | |
| reg = <0x03>; | |
| qcom,entry-latency-us = <0x2be>; | |
| }; | |
| }; | |
| qcom,pm-cluster-level@1 { | |
| qcom,exit-latency-us = <0x19a2>; | |
| qcom,psci-mode = <0xc24>; | |
| qcom,is-reset; | |
| label = "llcc-off"; | |
| qcom,notify-rpm; | |
| qcom,min-child-idx = <0x01>; | |
| qcom,min-residency-us = <0x2703>; | |
| reg = <0x01>; | |
| qcom,entry-latency-us = <0xcbf>; | |
| }; | |
| qcom,pm-cpu@0 { | |
| qcom,psci-mode-mask = <0x0f>; | |
| qcom,tmr-add = <0x3e8>; | |
| #address-cells = <0x01>; | |
| qcom,cpu = <0x0d 0x0e 0x0f 0x10>; | |
| #size-cells = <0x00>; | |
| qcom,psci-mode-shift = <0x00>; | |
| reg = <0x00>; | |
| qcom,ref-premature-cnt = <0x01>; | |
| qcom,ref-stddev = <0x1f4>; | |
| qcom,disable-ipi-prediction; | |
| qcom,pm-cpu-level@0 { | |
| qcom,exit-latency-us = <0x2b>; | |
| qcom,psci-cpu-mode = <0x01>; | |
| label = "wfi"; | |
| qcom,min-residency-us = <0x64>; | |
| reg = <0x00>; | |
| qcom,entry-latency-us = <0x39>; | |
| }; | |
| qcom,pm-cpu-level@1 { | |
| qcom,exit-latency-us = <0x213>; | |
| qcom,is-reset; | |
| qcom,psci-cpu-mode = <0x04>; | |
| label = "rail-pc"; | |
| qcom,use-broadcast-timer; | |
| qcom,min-residency-us = <0xf5e>; | |
| reg = <0x01>; | |
| qcom,entry-latency-us = <0x168>; | |
| }; | |
| }; | |
| qcom,pm-cluster-level@0 { | |
| qcom,exit-latency-us = <0x33>; | |
| qcom,psci-mode = <0x01>; | |
| label = "l3-wfi"; | |
| qcom,min-residency-us = <0x63>; | |
| reg = <0x00>; | |
| qcom,entry-latency-us = <0x30>; | |
| }; | |
| }; | |
| }; | |
| i2c@980000 { | |
| pinctrl-names = "default\0sleep"; | |
| #address-cells = <0x01>; | |
| pinctrl-0 = <0x281>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| interrupts = <0x00 0x259 0x04>; | |
| clocks = <0x16 0x58 0x16 0x84 0x16 0x85>; | |
| #size-cells = <0x00>; | |
| qcom,wrapper-core = <0x274>; | |
| dma-names = "tx\0rx"; | |
| compatible = "qcom,i2c-geni"; | |
| pinctrl-1 = <0x282>; | |
| status = "disabled"; | |
| reg = <0x980000 0x4000>; | |
| phandle = <0x5a0>; | |
| dmas = <0x280 0x00 0x00 0x03 0x40 0x00 0x280 0x01 0x00 0x03 0x40 0x00>; | |
| }; | |
| funnel@6983000 { | |
| arm,primecell-periphid = <0xbb908>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "funnel-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-funnel-turing"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6983000 0x1000>; | |
| phandle = <0x504>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x21f>; | |
| phandle = <0x1db>; | |
| }; | |
| }; | |
| port@3 { | |
| reg = <0x02>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x222>; | |
| phandle = <0x234>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x00>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x220>; | |
| phandle = <0x223>; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x01>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x221>; | |
| phandle = <0x224>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,msm_fastrpc { | |
| qcom,fastrpc-adsp-audio-pdr; | |
| qcom,qos-cores = <0x00 0x01 0x02 0x03>; | |
| qcom,rpc-latency-us = <0xeb>; | |
| compatible = "qcom,msm-fastrpc-compute"; | |
| qcom,fastrpc-adsp-sensors-pdr; | |
| phandle = <0x39f>; | |
| qcom,adsp-remoteheap-vmid = <0x16 0x25>; | |
| qcom,msm_fastrpc_compute_cb3 { | |
| iommus = <0x47 0x1003 0x460>; | |
| dma-coherent; | |
| label = "cdsprpc-smd"; | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; | |
| qcom,iommu-faults = "stall-disable\0HUPCF"; | |
| }; | |
| qcom,msm_fastrpc_compute_cb1 { | |
| iommus = <0x47 0x1001 0x460>; | |
| dma-coherent; | |
| label = "cdsprpc-smd"; | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; | |
| qcom,iommu-faults = "stall-disable\0HUPCF"; | |
| }; | |
| qcom,msm_fastrpc_compute_cb15 { | |
| iommus = <0x47 0x543 0x00>; | |
| dma-coherent; | |
| shared-cb = <0x04>; | |
| label = "sdsprpc-smd"; | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; | |
| qcom,iommu-faults = "stall-disable\0HUPCF"; | |
| }; | |
| qcom,msm_fastrpc_compute_cb8 { | |
| iommus = <0x47 0x1008 0x460>; | |
| dma-coherent; | |
| label = "cdsprpc-smd"; | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; | |
| qcom,iommu-faults = "stall-disable\0HUPCF"; | |
| }; | |
| qcom,msm_fastrpc_compute_cb13 { | |
| iommus = <0x47 0x541 0x00>; | |
| dma-coherent; | |
| label = "sdsprpc-smd"; | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; | |
| qcom,iommu-faults = "stall-disable\0HUPCF"; | |
| }; | |
| qcom,msm_fastrpc_compute_cb6 { | |
| iommus = <0x47 0x1006 0x460>; | |
| dma-coherent; | |
| label = "cdsprpc-smd"; | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; | |
| qcom,iommu-faults = "stall-disable\0HUPCF"; | |
| }; | |
| qcom,msm_fastrpc_compute_cb11 { | |
| iommus = <0x47 0x1804 0x00>; | |
| dma-coherent; | |
| label = "adsprpc-smd"; | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; | |
| qcom,iommu-faults = "stall-disable\0HUPCF"; | |
| }; | |
| qcom,msm_fastrpc_compute_cb4 { | |
| iommus = <0x47 0x1004 0x460>; | |
| dma-coherent; | |
| label = "cdsprpc-smd"; | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; | |
| qcom,iommu-faults = "stall-disable\0HUPCF"; | |
| }; | |
| qcom,msm_fastrpc_compute_cb2 { | |
| iommus = <0x47 0x1002 0x460>; | |
| dma-coherent; | |
| label = "cdsprpc-smd"; | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; | |
| qcom,iommu-faults = "stall-disable\0HUPCF"; | |
| }; | |
| qcom,msm_fastrpc_compute_cb9 { | |
| iommus = <0x47 0x1009 0x460>; | |
| dma-coherent; | |
| qcom,secure-context-bank; | |
| label = "cdsprpc-smd"; | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| qcom,iommu-dma-addr-pool = <0x60000000 0x78000000>; | |
| qcom,iommu-faults = "stall-disable\0HUPCF"; | |
| qcom,iommu-vmid = <0x0a>; | |
| }; | |
| qcom,msm_fastrpc_compute_cb14 { | |
| iommus = <0x47 0x542 0x00>; | |
| dma-coherent; | |
| label = "sdsprpc-smd"; | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; | |
| qcom,iommu-faults = "stall-disable\0HUPCF"; | |
| }; | |
| qcom,msm_fastrpc_compute_cb7 { | |
| iommus = <0x47 0x1007 0x460>; | |
| dma-coherent; | |
| label = "cdsprpc-smd"; | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; | |
| qcom,iommu-faults = "stall-disable\0HUPCF"; | |
| }; | |
| qcom,msm_fastrpc_compute_cb12 { | |
| iommus = <0x47 0x1805 0x00>; | |
| dma-coherent; | |
| label = "adsprpc-smd"; | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; | |
| qcom,iommu-faults = "stall-disable\0HUPCF"; | |
| }; | |
| qcom,msm_fastrpc_compute_cb5 { | |
| iommus = <0x47 0x1005 0x460>; | |
| dma-coherent; | |
| label = "cdsprpc-smd"; | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; | |
| qcom,iommu-faults = "stall-disable\0HUPCF"; | |
| }; | |
| qcom,msm_fastrpc_compute_cb10 { | |
| iommus = <0x47 0x1803 0x00>; | |
| dma-coherent; | |
| label = "adsprpc-smd"; | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; | |
| qcom,iommu-faults = "stall-disable\0HUPCF"; | |
| }; | |
| }; | |
| qcom,jpegdma@ac57000 { | |
| clock-names = "jpegdma_clk_src\0jpegdma_clk"; | |
| reg-names = "jpegdma_hw"; | |
| reg-cam-base = <0x57000>; | |
| cell-index = <0x00>; | |
| camss-vdd-supply = <0x253>; | |
| interrupts = <0x00 0x1db 0x01>; | |
| clocks = <0x6d 0x48 0x6d 0x47>; | |
| clock-cntl-level = "nominal"; | |
| compatible = "qcom,cam_jpeg_dma"; | |
| src-clock-name = "jpegdma_clk_src"; | |
| status = "ok"; | |
| interrupt-names = "jpegdma"; | |
| reg = <0xac57000 0x4000>; | |
| regulator-names = "camss-vdd"; | |
| phandle = <0x59a>; | |
| clock-rates = <0x23c34600 0x00>; | |
| }; | |
| spi@888000 { | |
| pinctrl-names = "default\0sleep"; | |
| #address-cells = <0x01>; | |
| pinctrl-0 = <0x2d6>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| reg-names = "se_phys"; | |
| interrupts = <0x00 0x248 0x04>; | |
| clocks = <0x16 0x7c 0x16 0x88 0x16 0x89>; | |
| #size-cells = <0x00>; | |
| qcom,wrapper-core = <0x2bf>; | |
| spi-max-frequency = <0x2faf080>; | |
| dma-names = "tx\0rx"; | |
| compatible = "qcom,spi-geni"; | |
| pinctrl-1 = <0x2d7>; | |
| status = "disabled"; | |
| reg = <0x888000 0x4000>; | |
| phandle = <0x5c8>; | |
| dmas = <0x2c2 0x00 0x02 0x01 0x40 0x00 0x2c2 0x01 0x02 0x01 0x40 0x00>; | |
| }; | |
| cti@6e01000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti-ddr_dl_0_cti_0"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6e01000 0x1000>; | |
| phandle = <0x50c>; | |
| }; | |
| ddr-bw-opp-table { | |
| compatible = "operating-points-v2"; | |
| phandle = <0x4d>; | |
| opp-1017 { | |
| opp-hz = <0x00 0xf27>; | |
| opp-supported-hw = <0x180>; | |
| }; | |
| opp-2736 { | |
| opp-hz = <0x00 0x28c5>; | |
| opp-supported-hw = <0x100>; | |
| }; | |
| opp-300 { | |
| opp-hz = <0x00 0x478>; | |
| opp-supported-hw = <0x180>; | |
| }; | |
| opp-451 { | |
| opp-hz = <0x00 0x6b8>; | |
| opp-supported-hw = <0x180>; | |
| }; | |
| opp-1353 { | |
| opp-hz = <0x00 0x1429>; | |
| opp-supported-hw = <0x80>; | |
| }; | |
| opp-2092 { | |
| opp-hz = <0x00 0x1f2c>; | |
| opp-supported-hw = <0x180>; | |
| }; | |
| opp-1804 { | |
| opp-hz = <0x00 0x1ae1>; | |
| opp-supported-hw = <0x180>; | |
| }; | |
| opp-768 { | |
| opp-hz = <0x00 0xb71>; | |
| opp-supported-hw = <0x180>; | |
| }; | |
| opp-200 { | |
| opp-hz = <0x00 0x2fa>; | |
| opp-supported-hw = <0x180>; | |
| }; | |
| opp-681 { | |
| opp-hz = <0x00 0xa25>; | |
| opp-supported-hw = <0x180>; | |
| }; | |
| opp-1555 { | |
| opp-hz = <0x00 0x172b>; | |
| opp-supported-hw = <0x180>; | |
| }; | |
| opp-547 { | |
| opp-hz = <0x00 0x826>; | |
| opp-supported-hw = <0x180>; | |
| }; | |
| }; | |
| qcom,gpubw { | |
| qcom,src-dst-ports = <0x1a 0x200>; | |
| governor = "bw_vbif"; | |
| compatible = "qcom,devbw-ddr"; | |
| phandle = <0x333>; | |
| operating-points-v2 = <0x51>; | |
| }; | |
| cti@6b4e000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti-ssc_cti_noc"; | |
| compatible = "arm,primecell"; | |
| status = "disabled"; | |
| reg = <0x6b4e000 0x1000>; | |
| phandle = <0x53e>; | |
| }; | |
| ssusb@a800000 { | |
| iommus = <0x47 0x20 0x00>; | |
| #address-cells = <0x01>; | |
| clock-names = "core_clk\0iface_clk\0bus_aggr_clk\0utmi_clk\0sleep_clk\0xo"; | |
| reg-names = "core_base"; | |
| qcom,charging-disabled; | |
| qcom,msm-bus,name = "usb1"; | |
| resets = <0x16 0x23>; | |
| clocks = <0x16 0xbc 0x16 0x10 0x16 0x09 0x16 0xbe 0x16 0xc1 0x16 0xc7>; | |
| qcom,use-pdc-interrupts; | |
| qcom,msm-bus,num-paths = <0x03>; | |
| extcon = <0x6a3>; | |
| #size-cells = <0x01>; | |
| qcom,msm-bus,num-cases = <0x03>; | |
| interrupts-extended = <0x76 0x0c 0x03 0x01 0x00 0x87 0x04 0x76 0x10 0x04 0x76 0x0d 0x03>; | |
| qcom,core-clk-rate-hs = <0x3f940ab>; | |
| qcom,num-gsi-evt-buffs = <0x03>; | |
| compatible = "qcom,dwc-usb3-msm"; | |
| ranges; | |
| interrupt-names = "dp_hs_phy_irq\0pwr_event_irq\0ss_phy_irq\0dm_hs_phy_irq"; | |
| qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; | |
| qcom,core-clk-rate = <0xbebc200>; | |
| reg = <0xa800000 0x100000>; | |
| phandle = <0x4dc>; | |
| qcom,msm-bus,vectors-KBps = <0x65 0x200 0x00 0x00 0x65 0x2a4 0x00 0x00 0x01 0x2ef 0x00 0x00 0x65 0x200 0xf4240 0x2625a0 0x65 0x2a4 0x00 0x960 0x01 0x2ef 0x00 0x9c40 0x65 0x200 0x3a980 0xaae60 0x65 0x2a4 0x00 0x960 0x01 0x2ef 0x00 0x9c40>; | |
| qcom,dwc-usb3-msm-tx-fifo-size = <0x6c30>; | |
| reset-names = "core_reset"; | |
| USB3_GDSC-supply = <0x188>; | |
| qcom,gsi-reg-offset = <0xfc 0x110 0x120 0x130 0x144 0x1a4>; | |
| qcom,iommu-dma = "atomic"; | |
| dwc3@a800000 { | |
| linux,sysdev_is_parent; | |
| snps,hird-threshold = [10]; | |
| tx-fifo-resize; | |
| snps,usb3_lpm_capable; | |
| usb-core-id = <0x01>; | |
| interrupts = <0x00 0x8a 0x04>; | |
| compatible = "snps,dwc3"; | |
| snps,disable-clk-gating; | |
| snps,has-lpm-erratum; | |
| reg = <0xa800000 0xd93c>; | |
| usb-phy = <0x189 0x18a>; | |
| dr_mode = "drd"; | |
| maximum-speed = "super-speed"; | |
| }; | |
| }; | |
| cti@6014000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti4"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6014000 0x1000>; | |
| phandle = <0x51c>; | |
| }; | |
| rx_npl_clk { | |
| qcom,codec-ext-clk-src = <0x06>; | |
| #clock-cells = <0x01>; | |
| compatible = "qcom,audio-ref-clk"; | |
| phandle = <0x656>; | |
| qcom,codec-lpass-clk-id = <0x30f>; | |
| qcom,codec-lpass-ext-clk-freq = <0x1588800>; | |
| }; | |
| tpdm@69d0000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-tpdm-qm"; | |
| compatible = "arm,primecell"; | |
| reg = <0x69d0000 0x1000>; | |
| phandle = <0x4fb>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x207>; | |
| phandle = <0x1c6>; | |
| }; | |
| }; | |
| }; | |
| qcom,qupv3_2_geni_se@8c0000 { | |
| iommus = <0x47 0x63 0x00>; | |
| qcom,bus-mas-id = <0x99>; | |
| qcom,bus-slv-id = <0x200>; | |
| compatible = "qcom,qupv3-geni-se"; | |
| qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>; | |
| reg = <0x8c0000 0x2000>; | |
| phandle = <0x2bf>; | |
| qcom,iommu-dma = "fastmap"; | |
| }; | |
| cti@6c42000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti-npu_dl_cti_0"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6c42000 0x1000>; | |
| phandle = <0x537>; | |
| }; | |
| cti@6c2c000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti-dlct_cti2"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6c2c000 0x1000>; | |
| phandle = <0x518>; | |
| }; | |
| etm@7340000 { | |
| arm,primecell-periphid = <0xbb95d>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x49 0x00>; | |
| cpu = <0x10>; | |
| qcom,tupwr-disable; | |
| coresight-name = "coresight-etm3"; | |
| compatible = "arm,primecell"; | |
| reg = <0x7340000 0x1000>; | |
| phandle = <0x54a>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x23e>; | |
| phandle = <0x247>; | |
| }; | |
| }; | |
| }; | |
| tpdm@6ac0000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-tpdm-dl-north"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6ac0000 0x1000>; | |
| phandle = <0x4f2>; | |
| qcom,msr-fix-req; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x1cf>; | |
| phandle = <0x1d2>; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dp_pll@c011000 { | |
| clock-names = "iface_clk\0ref_clk_src\0gcc_iface\0pipe_clk"; | |
| reg-names = "pll_base\0phy_base\0ln_tx0_base\0ln_tx0_tran_base\0ln_tx0_vmode_base\0ln_tx1_base\0ln_tx1_tran_base\0ln_tx1_vmode_base\0gdsc_base"; | |
| cell-index = <0x00>; | |
| clocks = <0x6c 0x00 0x15 0x00 0x16 0x18 0x16 0xc5>; | |
| #clock-cells = <0x01>; | |
| label = "MDSS DP PLL"; | |
| compatible = "qcom,mdss_dp_pll_7nm"; | |
| clock-rate = <0x00>; | |
| reg = <0x88ea000 0x200 0x88eaa00 0x200 0x88ea200 0x200 0x88ea2b8 0x08 0x88ea2e8 0x04 0x88ea600 0x200 0x88ea6b8 0x08 0x88ea6e8 0x04 0xaf03000 0x08>; | |
| phandle = <0x24d>; | |
| }; | |
| i3c-master@984000 { | |
| pinctrl-names = "default\0sleep\0disable"; | |
| #address-cells = <0x03>; | |
| pinctrl-2 = <0x277>; | |
| pinctrl-0 = <0x275>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| qcom,ibi-ctrl-id = <0x01>; | |
| clocks = <0x16 0x5a 0x16 0x84 0x16 0x85>; | |
| #size-cells = <0x00>; | |
| qcom,wrapper-core = <0x274>; | |
| interrupts-extended = <0x01 0x00 0x25a 0x04 0x76 0x21 0x04 0x76 0x20 0x04>; | |
| compatible = "qcom,geni-i3c"; | |
| pinctrl-1 = <0x276>; | |
| status = "disabled"; | |
| reg = <0x984000 0x4000 0xec40000 0x10000>; | |
| phandle = <0x59d>; | |
| }; | |
| jtagmm@7440000 { | |
| clock-names = "core_clk"; | |
| reg-names = "etm-base"; | |
| clocks = <0x49 0x00>; | |
| compatible = "qcom,jtagv8-mm"; | |
| qcom,coresight-jtagmm-cpu = <0x11>; | |
| reg = <0x7440000 0x1000>; | |
| phandle = <0x356>; | |
| }; | |
| interrupt-controller@b220000 { | |
| qcom,pdc-ranges = <0x00 0x1e0 0x5e 0x5e 0x261 0x1f 0x7d 0x3f 0x01 0x7e 0x2cc 0x0c>; | |
| interrupt-parent = <0x01>; | |
| compatible = "qcom,kona-pdc"; | |
| #interrupt-cells = <0x02>; | |
| reg = <0xb220000 0x30000 0x17c000f0 0x60>; | |
| phandle = <0x76>; | |
| interrupt-controller; | |
| }; | |
| kryo-erp { | |
| interrupts = <0x01 0x00 0x04 0x00 0x23 0x04>; | |
| compatible = "arm,arm64-kryo-cpu-erp"; | |
| interrupt-names = "l1-l2-faultirq\0l3-scu-faultirq"; | |
| }; | |
| qcom,wdt@17c10000 { | |
| qcom,bark-time = <0x2af8>; | |
| reg-names = "wdt-base"; | |
| interrupts = <0x00 0x00 0x04 0x00 0x01 0x04>; | |
| qcom,wakeup-enable; | |
| compatible = "qcom,msm-watchdog"; | |
| qcom,ipi-ping; | |
| qcom,pet-time = <0x2490>; | |
| reg = <0x17c10000 0x1000>; | |
| phandle = <0x34d>; | |
| }; | |
| tpdm@6c60000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-tpdm-mdss"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6c60000 0x1000>; | |
| phandle = <0x1e5>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x218>; | |
| phandle = <0x213>; | |
| }; | |
| }; | |
| }; | |
| cti@6b4b000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti-ssc_cti0_q6"; | |
| compatible = "arm,primecell"; | |
| status = "disabled"; | |
| reg = <0x6b4b000 0x1000>; | |
| phandle = <0x53c>; | |
| }; | |
| cti@6011000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti1"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6011000 0x1000>; | |
| phandle = <0x519>; | |
| }; | |
| qcom,cpu-llcc-ddr-bw { | |
| qcom,src-dst-ports = <0x81 0x200>; | |
| governor = "performance"; | |
| compatible = "qcom,devbw-ddr"; | |
| phandle = <0x4e>; | |
| qcom,active-only; | |
| operating-points-v2 = <0x4d>; | |
| }; | |
| qcom,ipa_uc { | |
| qcom,pil-force-shutdown; | |
| memory-region = <0x88>; | |
| qcom,pas-id = <0x1b>; | |
| compatible = "qcom,pil-tz-generic"; | |
| qcom,firmware-name = "ipa_uc"; | |
| }; | |
| demux { | |
| compatible = "qcom,demux"; | |
| }; | |
| qcom,camcc@ad00000 { | |
| #reset-cells = <0x01>; | |
| clock-names = "cfg_ahb_clk"; | |
| reg-names = "cc_base"; | |
| clocks = <0x16 0x0b>; | |
| vdd_mm-supply = <0x69>; | |
| #clock-cells = <0x01>; | |
| vdd_mx-supply = <0x6a>; | |
| compatible = "qcom,camcc-kona-v2\0syscon"; | |
| reg = <0xad00000 0x10000>; | |
| phandle = <0x6d>; | |
| }; | |
| qcom,msm-lsm-client { | |
| compatible = "qcom,msm-lsm-client"; | |
| phandle = <0x2e9>; | |
| }; | |
| qcom,gdsc@17d054 { | |
| qcom,no-status-check-on-disable; | |
| qcom,gds-timeout = <0x1f4>; | |
| regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc"; | |
| compatible = "qcom,gdsc"; | |
| reg = <0x17d054 0x04>; | |
| phandle = <0x17f>; | |
| }; | |
| qcom,qup_uart@988000 { | |
| pinctrl-names = "default\0sleep"; | |
| pinctrl-0 = <0x278>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| reg-names = "se_phys"; | |
| interrupts = <0x00 0x25b 0x04>; | |
| clocks = <0x16 0x5c 0x16 0x84 0x16 0x85>; | |
| qcom,change-sampling-rate; | |
| qcom,wrapper-core = <0x274>; | |
| compatible = "qcom,msm-geni-console"; | |
| pinctrl-1 = <0x279>; | |
| status = "disabled"; | |
| reg = <0x988000 0x4000>; | |
| phandle = <0x59e>; | |
| }; | |
| ssphy@88e8000 { | |
| qcom,vbus-valid-override; | |
| qcom,vdd-voltage-level = <0x00 0xdea80 0xdea80>; | |
| clock-names = "aux_clk\0pipe_clk\0pipe_clk_mux\0pipe_clk_ext_src\0ref_clk_src\0com_aux_clk"; | |
| reg-names = "qmp_phy_base"; | |
| resets = <0x16 0x24 0x16 0x26>; | |
| clocks = <0x16 0xc2 0x16 0xc5 0x16 0xc6 0x16 0x01 0x15 0x00 0x16 0xc4>; | |
| extcon = <0x637>; | |
| vdd-supply = <0x187>; | |
| qcom,qmp-phy-reg-offset = <0x1c14 0x1f08 0x1f14 0x1c40 0x1c00 0x1c44 0xffff 0x2a18 0x08 0x04 0x1c 0x00 0x10 0x0c 0x1c8c>; | |
| compatible = "qcom,usb-ssphy-qmp-dp-combo"; | |
| qcom,vdd-max-load-uA = <0xb798>; | |
| reg = <0x88e8000 0x3000>; | |
| phandle = <0x184>; | |
| reset-names = "global_phy_reset\0phy_reset"; | |
| qcom,qmp-phy-init-seq = <0x1010 0x01 0x00 0x101c 0x31 0x00 0x1020 0x01 0x00 0x1024 0xde 0x00 0x1028 0x07 0x00 0x1030 0xde 0x00 0x1034 0x07 0x00 0x1050 0x0a 0x00 0x1060 0x20 0x00 0x1074 0x06 0x00 0x1078 0x06 0x00 0x107c 0x16 0x00 0x1080 0x16 0x00 0x1084 0x36 0x00 0x1088 0x36 0x00 0x1094 0x1a 0x00 0x10a4 0x04 0x00 0x10ac 0x14 0x00 0x10b0 0x34 0x00 0x10b4 0x34 0x00 0x10b8 0x82 0x00 0x10bc 0x82 0x00 0x10c4 0x82 0x00 0x10cc 0xab 0x00 0x10d0 0xea 0x00 0x10d4 0x02 0x00 0x10d8 0xab 0x00 0x10dc 0xea 0x00 0x10e0 0x02 0x00 0x110c 0x02 0x00 0x1110 0x24 0x00 0x1118 0x24 0x00 0x111c 0x02 0x00 0x1158 0x01 0x00 0x116c 0x08 0x00 0x11ac 0xca 0x00 0x11b0 0x1e 0x00 0x11b4 0xca 0x00 0x11b8 0x1e 0x00 0x11bc 0x11 0x00 0x1234 0x60 0x00 0x1238 0x60 0x00 0x123c 0x11 0x00 0x1240 0x02 0x00 0x1284 0xd5 0x00 0x1288 0x00 0x00 0x129c 0x12 0x00 0x1304 0x40 0x00 0x1408 0x09 0x00 0x1414 0x05 0x00 0x1430 0x2f 0x00 0x1434 0x7f 0x00 0x143c 0xff 0x00 0x1440 0x0f 0x00 0x1444 0x99 0x00 0x144c 0x08 0x00 0x1450 0x08 0x00 0x1454 0x00 0x00 0x1458 0x04 0x00 0x14d4 0x54 0x00 0x14d8 0x0c 0x00 0x14ec 0x0f 0x00 0x14f0 0x4a 0x00 0x14f4 0x0a 0x00 0x14f8 0xc0 0x00 0x14fc 0x00 0x00 0x1510 0x77 0x00 0x151c 0x04 0x00 0x1524 0x0e 0x00 0x1570 0xff 0x00 0x1574 0x7f 0x00 0x1578 0x7f 0x00 0x157c 0x7f 0x00 0x1580 0x97 0x00 0x1584 0xdc 0x00 0x1588 0xdc 0x00 0x158c 0x5c 0x00 0x1590 0x7b 0x00 0x1594 0xb4 0x00 0x15b4 0x04 0x00 0x15b8 0x38 0x00 0x1460 0xa0 0x00 0x15bc 0x0c 0x00 0x14dc 0x1f 0x00 0x15c4 0x10 0x00 0x1634 0x60 0x00 0x1638 0x60 0x00 0x163c 0x11 0x00 0x1640 0x02 0x00 0x1684 0xd5 0x00 0x1688 0x00 0x00 0x169c 0x12 0x00 0x1704 0x54 0x00 0x1808 0x09 0x00 0x1814 0x05 0x00 0x1830 0x2f 0x00 0x1834 0x7f 0x00 0x183c 0xff 0x00 0x1840 0x0f 0x00 0x1844 0x99 0x00 0x184c 0x08 0x00 0x1850 0x08 0x00 0x1854 0x00 0x00 0x1858 0x04 0x00 0x18d4 0x54 0x00 0x18d8 0x0c 0x00 0x18ec 0x0f 0x00 0x18f0 0x4a 0x00 0x18f4 0x0a 0x00 0x18f8 0xc0 0x00 0x18fc 0x00 0x00 0x1910 0x77 0x00 0x191c 0x04 0x00 0x1924 0x0e 0x00 0x1970 0x7f 0x00 0x1974 0xff 0x00 0x1978 0x3f 0x00 0x197c 0x7f 0x00 0x1980 0xa6 0x00 0x1984 0xdc 0x00 0x1988 0xdc 0x00 0x198c 0x5c 0x00 0x1990 0x7b 0x00 0x1994 0xb4 0x00 0x19b4 0x04 0x00 0x19b8 0x38 0x00 0x1860 0xa0 0x00 0x19bc 0x0c 0x00 0x18dc 0x1f 0x00 0x19c4 0x10 0x00 0x1cc4 0xd0 0x00 0x1cc8 0x07 0x00 0x1ccc 0x20 0x00 0x1cd8 0x13 0x00 0x1cdc 0x21 0x00 0x1d88 0xa9 0x00 0x1db0 0x0a 0x00 0x1dc0 0x88 0x00 0x1dc4 0x13 0x00 0x1dd0 0x0c 0x00 0x1ddc 0x4b 0x00 0x1dec 0x10 0x00 0x1f18 0xf8 0x00 0x1f38 0x07 0x00 0xffffffff 0xffffffff 0x00>; | |
| core-supply = <0x7d>; | |
| }; | |
| qcom,msm_npu@9800000 { | |
| iommus = <0x47 0x1081 0x400 0x47 0x1082 0x400 0x47 0x10a1 0x400 0x47 0x10a2 0x400 0x47 0x10c1 0x400 0x47 0x10c2 0x400>; | |
| qcom,npu-dsp-sid-mapped; | |
| clock-names = "xo_clk\0npu_core_clk\0cal_hm0_clk\0cal_hm1_clk\0cal_hm0_cdc_clk\0cal_hm1_cdc_clk\0axi_clk\0ahb_clk\0dma_clk\0llm_clk\0llm_xo_clk\0llm_temp_clk\0llm_curr_clk\0dl_llm_clk\0isense_clk\0dpm_clk\0dpm_xo_clk\0dl_dpm_clk\0rsc_xo_clk\0dpm_temp_clk\0cal_hm0_dpm_ip_clk\0cal_hm1_dpm_ip_clk\0s2p_clk\0bwmon_clk\0cal_hm0_perf_cnt_clk\0cal_hm1_perf_cnt_clk\0bto_core_clk\0dsp_core_clk_src"; | |
| reg-names = "tcm\0core\0cc\0apss_shared\0tcsr"; | |
| qcom,src-dst-ports = <0x9a 0x200 0x9a 0x26c>; | |
| resets = <0x55 0x03 0x55 0x05 0x55 0x06>; | |
| interrupts = <0x00 0x16c 0x04 0x00 0x16e 0x01 0x00 0x170 0x01 0x00 0x16d 0x04>; | |
| clocks = <0x55 0x28 0x55 0x0d 0x55 0x04 0x55 0x09 0x55 0x03 0x55 0x08 0x55 0x20 0x55 0x1f 0x55 0x21 0x55 0x1a 0x55 0x1d 0x55 0x1c 0x55 0x1b 0x55 0x10 0x55 0x19 0x55 0x11 0x55 0x13 0x55 0x0f 0x55 0x26 0x55 0x12 0x55 0x06 0x55 0x0b 0x55 0x27 0x55 0x02 0x55 0x07 0x55 0x0c 0x55 0x01 0x55 0x2a>; | |
| #mbox-cells = <0x02>; | |
| vdd-supply = <0x1de>; | |
| compatible = "qcom,msm-npu"; | |
| status = "ok"; | |
| qcom,vdd_cx-uV-uA = <0x180 0x186a0>; | |
| interrupt-names = "error_irq\0wdg_bite_irq\0ipc_irq\0general_irq"; | |
| reg = <0x9900000 0x20000 0x99f0000 0x10000 0x9980000 0x10000 0x17c00000 0x10000 0x1f40000 0x40000>; | |
| phandle = <0x3f>; | |
| mboxes = <0x8a 0x07 0x00 0x8a 0x07 0x02 0x8a 0x07 0x03>; | |
| vdd_cx-supply = <0x67>; | |
| reset-names = "dpm_temp_clk\0llm_curr_clk\0llm_temp_clk"; | |
| qcom,npubw-devs = <0x50 0x52 0x53>; | |
| qcom,proxy-reg-names = "vdd\0vdd_cx"; | |
| mbox-names = "ipcc-glink\0ipcc-smp2p\0ipcc-ping"; | |
| #cooling-cells = <0x02>; | |
| qcom,npubw-dev-names = "llcc_bw\0llcc_ddr_bw\0dsp_ddr_bw"; | |
| qcom,npu-pwrlevels { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| initial-pwrlevel = <0x05>; | |
| compatible = "qcom,npu-pwrlevels"; | |
| qcom,npu-pwrlevel@5 { | |
| clk-freq = <0x124f800 0x1dcd6500 0x3b9aca00 0x3b9aca00 0x3b9aca00 0x3b9aca00 0x29b92700 0x47868c0 0x300a9580 0x11e1a300 0x124f800 0x5f5e100 0xbebc200 0x11e1a300 0x11e1a300 0x11e1a300 0x124f800 0x11e1a300 0x124f800 0x5f5e100 0x3b9aca00 0x3b9aca00 0x5f5e100 0x124f800 0x3b9aca00 0x3b9aca00 0x124f800 0x2faf0800>; | |
| vreg = <0x07>; | |
| reg = <0x05>; | |
| }; | |
| qcom,npu-pwrlevel@3 { | |
| clk-freq = <0x124f800 0x1982c300 0x2b82ea80 0x2b82ea80 0x2b82ea80 0x2b82ea80 0x1fc4ef40 0x47868c0 0x29b92700 0x11e1a300 0x124f800 0x5f5e100 0xbebc200 0x11e1a300 0x11e1a300 0x11e1a300 0x124f800 0x11e1a300 0x124f800 0x5f5e100 0x2b82ea80 0x2b82ea80 0x5f5e100 0x124f800 0x2b82ea80 0x2b82ea80 0x124f800 0x2756cd00>; | |
| vreg = <0x04>; | |
| reg = <0x03>; | |
| }; | |
| qcom,npu-pwrlevel@1 { | |
| clk-freq = <0x124f800 0xbebc200 0x18331180 0x18331180 0x18331180 0x18331180 0xfea18c0 0x2625a00 0x18054ac0 0xbebc200 0x124f800 0x2faf080 0x2faf080 0xbebc200 0xbebc200 0xbebc200 0x124f800 0xbebc200 0x124f800 0x2faf080 0x18331180 0x18331180 0x2faf080 0x124f800 0x18331180 0x18331180 0x124f800 0x17d78400>; | |
| vreg = <0x02>; | |
| reg = <0x01>; | |
| }; | |
| qcom,npu-pwrlevel@4 { | |
| clk-freq = <0x124f800 0x1dcd6500 0x36d61600 0x36d61600 0x36d61600 0x36d61600 0x29b92700 0x47868c0 0x300a9580 0x11e1a300 0x124f800 0x5f5e100 0xbebc200 0x11e1a300 0x11e1a300 0x11e1a300 0x124f800 0x11e1a300 0x124f800 0x5f5e100 0x36d61600 0x36d61600 0x5f5e100 0x124f800 0x36d61600 0x36d61600 0x124f800 0x2faf0800>; | |
| vreg = <0x06>; | |
| reg = <0x04>; | |
| }; | |
| qcom,npu-pwrlevel@2 { | |
| clk-freq = <0x124f800 0x13d92d40 0x1fc4ef40 0x1fc4ef40 0x1fc4ef40 0x1fc4ef40 0x18054ac0 0x47868c0 0x1fc4ef40 0xcc16180 0x124f800 0x2faf080 0x5f5e100 0xcc16180 0xcc16180 0xcc16180 0x124f800 0xcc16180 0x124f800 0x2faf080 0x1fc4ef40 0x1fc4ef40 0x2faf080 0x124f800 0x1fc4ef40 0x1fc4ef40 0x124f800 0x1dcd6500>; | |
| vreg = <0x03>; | |
| reg = <0x02>; | |
| }; | |
| qcom,npu-pwrlevel@0 { | |
| clk-freq = <0x124f800 0x5f5e100 0x11e1a300 0x11e1a300 0x11e1a300 0x11e1a300 0xbebc200 0x2625a00 0x11e1a300 0x5f5e100 0x124f800 0x2faf080 0x2faf080 0x5f5e100 0x5f5e100 0x5f5e100 0x124f800 0x5f5e100 0x124f800 0x2faf080 0xbebc200 0xbebc200 0x2faf080 0x124f800 0x11e1a300 0x11e1a300 0x124f800 0x11e1a300>; | |
| vreg = <0x01>; | |
| reg = <0x00>; | |
| }; | |
| }; | |
| }; | |
| syscon@3d91508 { | |
| compatible = "syscon"; | |
| reg = <0x3d91508 0x04>; | |
| phandle = <0x73>; | |
| }; | |
| qcom,msm-tert-auxpcm { | |
| qcom,msm-cpudai-auxpcm-quant = <0x02 0x02>; | |
| qcom,msm-cpudai-auxpcm-frame = <0x05 0x04>; | |
| qcom,msm-cpudai-auxpcm-sync = <0x01 0x01>; | |
| qcom,msm-auxpcm-interface = "tertiary"; | |
| qcom,msm-cpudai-auxpcm-slot-mapping = <0x01 0x01>; | |
| qcom,msm-cpudai-auxpcm-data = <0x00 0x00>; | |
| qcom,msm-cpudai-afe-clk-ver = <0x02>; | |
| qcom,msm-cpudai-auxpcm-num-slots = <0x01 0x01>; | |
| compatible = "qcom,msm-auxpcm-dev"; | |
| qcom,msm-cpudai-auxpcm-mode = <0x00 0x00>; | |
| phandle = <0x2f7>; | |
| qcom,msm-cpudai-auxpcm-pcm-clk-rate = <0x1f4000 0x1f4000>; | |
| }; | |
| qcom,msm-transcode-loopback { | |
| compatible = "qcom,msm-transcode-loopback"; | |
| phandle = <0x5cc>; | |
| }; | |
| qcom,ife-lite0@acd9000 { | |
| camss-supply = <0x253>; | |
| clock-control-debugfs = "true"; | |
| clock-names = "ife_lite_ahb\0ife_lite_axi\0ife_clk_src\0ife_clk"; | |
| reg-names = "ife-lite"; | |
| reg-cam-base = <0xd9000>; | |
| cell-index = <0x02>; | |
| interrupts = <0x00 0x1d5 0x01>; | |
| clocks = <0x6d 0x3b 0x6d 0x3c 0x6d 0x3e 0x6d 0x3d>; | |
| clock-cntl-level = "lowsvs\0svs\0svs_l1\0turbo"; | |
| compatible = "qcom,vfe-lite480"; | |
| src-clock-name = "ife_clk_src"; | |
| status = "ok"; | |
| interrupt-names = "ife-lite"; | |
| reg = <0xacd9000 0x2200>; | |
| regulator-names = "camss"; | |
| phandle = <0x593>; | |
| clock-rates = <0x00 0x00 0x17d78400 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x1c9c3800 0x00>; | |
| }; | |
| i2c@894000 { | |
| pinctrl-names = "default\0sleep"; | |
| #address-cells = <0x01>; | |
| pinctrl-0 = <0x2d0>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| interrupts = <0x00 0x24b 0x04>; | |
| clocks = <0x16 0x82 0x16 0x88 0x16 0x89>; | |
| #size-cells = <0x00>; | |
| qcom,wrapper-core = <0x2bf>; | |
| dma-names = "tx\0rx"; | |
| compatible = "qcom,i2c-geni"; | |
| pinctrl-1 = <0x2d1>; | |
| status = "disabled"; | |
| reg = <0x894000 0x4000>; | |
| phandle = <0x5c5>; | |
| dmas = <0x2c2 0x00 0x05 0x03 0x40 0x00 0x2c2 0x01 0x05 0x03 0x40 0x00>; | |
| }; | |
| qcom,ion { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,msm-ion"; | |
| qcom,ion-heap@13 { | |
| memory-region = <0x162>; | |
| qcom,ion-heap-type = "HYP_CMA"; | |
| reg = <0x0d>; | |
| }; | |
| qcom,ion-heap@26 { | |
| memory-region = <0x160>; | |
| qcom,ion-heap-type = "DMA"; | |
| reg = <0x1a>; | |
| }; | |
| qcom,ion-heap@14 { | |
| qcom,ion-heap-type = "SECURE_CARVEOUT"; | |
| reg = <0x0e>; | |
| cdsp { | |
| memory-region = <0x164>; | |
| token = <0x20000000>; | |
| }; | |
| }; | |
| qcom,ion-heap@22 { | |
| memory-region = <0x15f>; | |
| qcom,ion-heap-type = "DMA"; | |
| reg = <0x16>; | |
| phandle = <0x3d7>; | |
| }; | |
| qcom,ion-heap@10 { | |
| memory-region = <0x163>; | |
| qcom,ion-heap-type = "HYP_CMA"; | |
| reg = <0x0a>; | |
| }; | |
| qcom,ion-heap@9 { | |
| qcom,ion-heap-type = "SYSTEM_SECURE"; | |
| reg = <0x09>; | |
| phandle = <0x3d8>; | |
| }; | |
| qcom,ion-heap@19 { | |
| memory-region = <0x161>; | |
| qcom,ion-heap-type = "DMA"; | |
| reg = <0x13>; | |
| }; | |
| qcom,ion-heap@27 { | |
| memory-region = <0x60>; | |
| qcom,ion-heap-type = "DMA"; | |
| reg = <0x1b>; | |
| }; | |
| qcom,ion-heap@25 { | |
| qcom,ion-heap-type = "SYSTEM"; | |
| reg = <0x19>; | |
| phandle = <0x3d6>; | |
| }; | |
| }; | |
| funnel@6041000 { | |
| arm,primecell-periphid = <0xbb908>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "funnel-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-funnel-in0"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6041000 0x1000>; | |
| phandle = <0x4e8>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x1a8>; | |
| phandle = <0x1a5>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x06>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x1a9>; | |
| phandle = <0x230>; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x07>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x1aa>; | |
| phandle = <0x1a7>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,csid1@acc4200 { | |
| camss-supply = <0x253>; | |
| clock-control-debugfs = "true"; | |
| clock-names = "ife_csid_clk_src\0ife_csid_clk\0cphy_rx_clk_src\0ife_cphy_rx_clk\0ife_clk_src\0ife_clk\0ife_1_areg\0ife_1_ahb\0ife_axi_clk"; | |
| reg-names = "csid"; | |
| reg-cam-base = "\0\fB"; | |
| cell-index = <0x01>; | |
| ife1-supply = <0x26e>; | |
| interrupts = <0x00 0x1d2 0x01>; | |
| clocks = <0x6d 0x39 0x6d 0x38 0x6d 0x0e 0x6d 0x37 0x6d 0x36 0x6d 0x35 0x6d 0x33 0x6d 0x32 0x6d 0x34>; | |
| clock-cntl-level = "lowsvs\0svs\0svs_l1\0turbo"; | |
| compatible = "qcom,csid480"; | |
| src-clock-name = "ife_csid_clk_src"; | |
| status = "ok"; | |
| interrupt-names = "csid"; | |
| reg = <0xacc4200 0x1000>; | |
| regulator-names = "camss\0ife1"; | |
| phandle = <0x590>; | |
| clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x14dc9380 0x00 0x5f5e100 0x00 0x00 0x17d78400 0x00 0x17d78400 0x00 0x1c4fecc0 0x00 0xbebc200 0x00 0x00 0x17d78400 0x00 0x17d78400 0x00 0x22551000 0x00 0x11e1a300 0x00 0x00 0x17d78400 0x00 0x17d78400 0x00 0x2aea5400 0x00 0x17d78400 0x00 0x00>; | |
| }; | |
| csr@6b0c000 { | |
| qcom,blk-size = <0x01>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "csr-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-swao-csr"; | |
| qcom,timestamp-support; | |
| compatible = "qcom,coresight-csr"; | |
| reg = <0x6b0c000 0x1000>; | |
| phandle = <0x193>; | |
| }; | |
| qcom,cpas-cdm0@ac4d000 { | |
| camss-supply = <0x253>; | |
| clock-names = "cam_cc_cpas_slow_ahb_clk\0cam_cc_cpas_ahb_clk"; | |
| reg-names = "cpas-cdm"; | |
| reg-cam-base = <0x4d000>; | |
| cdm-client-names = "ife"; | |
| cell-index = <0x00>; | |
| interrupts = <0x00 0x1cd 0x01>; | |
| clocks = <0x6d 0x6d 0x6d 0x0d>; | |
| label = "cpas-cdm"; | |
| clock-cntl-level = "svs"; | |
| compatible = "qcom,cam170-cpas-cdm0"; | |
| status = "ok"; | |
| interrupt-names = "cpas-cdm"; | |
| reg = <0xac4d000 0x1000>; | |
| regulator-names = "camss"; | |
| clock-rates = <0x00 0x00>; | |
| }; | |
| qcom,msm-adsp-loader { | |
| qcom,adsp-state = <0x00>; | |
| compatible = "qcom,adsp-loader"; | |
| status = "ok"; | |
| phandle = <0x5e5>; | |
| }; | |
| qcom,gdsc@ad08004 { | |
| clock-names = "ahb_clk"; | |
| qcom,msm-bus,name = "ipe_0_gdsc_ahb"; | |
| parent-supply = <0x69>; | |
| qcom,support-hw-trigger; | |
| qcom,retain-regs; | |
| clocks = <0x16 0x0b>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| regulator-name = "ipe_0_gdsc"; | |
| vdd_parent-supply = <0x69>; | |
| compatible = "qcom,gdsc"; | |
| reg = <0xad08004 0x04>; | |
| phandle = <0x26f>; | |
| qcom,msm-bus,vectors-KBps = <0x01 0x24d 0x00 0x00 0x01 0x24d 0x00 0x01>; | |
| }; | |
| qcom,pcie@1c10000 { | |
| pinctrl-names = "default"; | |
| qcom,vreg-0p9-voltage-level = <0xd6d80 0xd6d80 0x181f0>; | |
| #address-cells = <0x03>; | |
| dma-coherent; | |
| pinctrl-0 = <0x175 0x176 0x177>; | |
| clock-names = "pcie_2_pipe_clk\0pcie_2_ref_clk_src\0pcie_2_aux_clk\0pcie_2_cfg_ahb_clk\0pcie_2_mstr_axi_clk\0pcie_2_slv_axi_clk\0pcie_2_ldo\0pcie_2_slv_q2a_axi_clk\0pcie_tbu_clk\0pcie_phy_refgen_clk\0pcie_ddrss_sf_tbu_clk"; | |
| reg-names = "parf\0phy\0dm_core\0elbi\0iatu\0conf"; | |
| qcom,phy-power-down-offset = <0xa40>; | |
| qcom,msm-bus,name = "pcie2"; | |
| qcom,pcie-phy-ver = <0x44e>; | |
| cell-index = <0x02>; | |
| resets = <0x16 0x0e 0x16 0x11>; | |
| qcom,bw-scale = <0x40 0x124f800 0x40 0x124f800 0x100 0x5f5e100>; | |
| interrupts = <0x00 0x01 0x02 0x03 0x04>; | |
| clocks = <0x16 0x44 0x15 0x00 0x16 0x40 0x16 0x42 0x16 0x43 0x16 0x45 0x16 0x47 0x16 0x46 0x16 0x03 0x16 0x31 0x16 0x17>; | |
| qcom,smmu-sid-base = <0x1d00>; | |
| interrupt-map = <0x00 0x00 0x00 0x00 0x01 0x00 0xec 0x04 0x00 0x00 0x00 0x01 0x01 0x00 0x122 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0x19f 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x1a0 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0x1a1 0x04>; | |
| max-clock-frequency-hz = <0x00 0x00 0x124f800 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x5f5e100 0x00>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| #size-cells = <0x02>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| qcom,boot-option = <0x01>; | |
| interrupt-parent = <0x173>; | |
| qcom,vreg-1p8-voltage-level = <0x124f80 0x124f80 0x639c>; | |
| qcom,phy-status-offset = <0xa14>; | |
| interrupt-map-mask = <0x00 0x00 0x00 0xffffffff>; | |
| wake-gpio = <0x66 0x57 0x00>; | |
| vreg-0p9-supply = <0x7c>; | |
| qcom,drv-supported; | |
| compatible = "qcom,pci-msm"; | |
| ranges = <0x1000000 0x00 0x64200000 0x64200000 0x00 0x100000 0x2000000 0x00 0x64300000 0x64300000 0x00 0x3d00000>; | |
| #interrupt-cells = <0x01>; | |
| interrupt-names = "int_global_int\0int_a\0int_b\0int_c\0int_d"; | |
| vreg-1p8-supply = <0x7d>; | |
| reg = <0x1c10000 0x3000 0x1c16000 0x2000 0x64000000 0xf1d 0x64000f20 0xa8 0x64001000 0x1000 0x64100000 0x100000>; | |
| linux,pci-domain = <0x02>; | |
| phandle = <0x173>; | |
| qcom,msm-bus,vectors-KBps = <0x6c 0x200 0x00 0x00 0x6c 0x200 0x1f4 0x320>; | |
| gdsc-vdd-supply = <0x178>; | |
| iommu-map = <0x00 0x47 0x1d00 0x01 0x100 0x47 0x1d01 0x01>; | |
| msi-parent = <0x174>; | |
| qcom,no-l0s-supported; | |
| reset-names = "pcie_2_core_reset\0pcie_2_phy_reset"; | |
| qcom,ep-latency = <0x0a>; | |
| vreg-cx-supply = <0x67>; | |
| qcom,use-19p2mhz-aux-clk; | |
| perst-gpio = <0x66 0x55 0x00>; | |
| qcom,vreg-cx-voltage-level = <0xffff 0x100 0x00>; | |
| qcom,phy-status-bit = <0x06>; | |
| qcom,slv-addr-space-size = <0x4000000>; | |
| qcom,phy-sequence = <0xa40 0x03 0x00 0x10 0x01 0x00 0x1c 0x31 0x00 0x20 0x01 0x00 0x24 0xde 0x00 0x28 0x07 0x00 0x30 0x4c 0x00 0x34 0x06 0x00 0x48 0x90 0x00 0x58 0x0f 0x00 0x74 0x06 0x00 0x78 0x06 0x00 0x7c 0x16 0x00 0x80 0x16 0x00 0x84 0x36 0x00 0x88 0x36 0x00 0x94 0x08 0x00 0xa4 0x42 0x00 0xac 0x0a 0x00 0xb0 0x1a 0x00 0xb4 0x14 0x00 0xb8 0x34 0x00 0xbc 0x82 0x00 0xc4 0x68 0x00 0xcc 0x55 0x00 0xd0 0x55 0x00 0xd4 0x03 0x00 0xd8 0xab 0x00 0xdc 0xaa 0x00 0xe0 0x02 0x00 0x10c 0x02 0x00 0x110 0x24 0x00 0x118 0xb4 0x00 0x11c 0x03 0x00 0x154 0x34 0x00 0x158 0x01 0x00 0x16c 0x08 0x00 0x1ac 0xca 0x00 0x1b0 0x1e 0x00 0x1b4 0xa2 0x00 0x1b8 0x18 0x00 0x1bc 0x11 0x00 0x23c 0x11 0x00 0x284 0x75 0x00 0x29c 0x12 0x00 0x304 0x02 0x00 0x408 0x0c 0x00 0x414 0x03 0x00 0x434 0x7f 0x00 0x444 0x70 0x00 0x460 0x30 0x00 0x4d4 0x04 0x00 0x4d8 0x07 0x00 0x4dc 0x1b 0x00 0x4e8 0x04 0x00 0x4ec 0x0e 0x00 0x4f0 0x4a 0x00 0x4f4 0x0f 0x00 0x4f8 0xc0 0x00 0x4fc 0x00 0x00 0x510 0x17 0x00 0x518 0x1c 0x00 0x51c 0x03 0x00 0x524 0x1e 0x00 0x570 0xbf 0x00 0x574 0x3f 0x00 0x578 0xff 0x00 0x57c 0x7f 0x00 0x580 0x15 0x00 0x584 0x24 0x00 0x588 0xe4 0x00 0x58c 0xec 0x00 0x590 0x3b 0x00 0x594 0x36 0x00 0x598 0xd4 0x00 0x59c 0x54 0x00 0x5a0 0xdb 0x00 0x5a4 0x3b 0x00 0x5a8 0x31 0x00 0x5bc 0x0c 0x00 0x5b8 0x38 0x00 0x63c 0x11 0x00 0x684 0x75 0x00 0x69c 0x12 0x00 0x704 0x20 0x00 0x808 0x0c 0x00 0x814 0x03 0x00 0x834 0x7f 0x00 0x844 0x70 0x00 0x860 0x30 0x00 0x8d4 0x04 0x00 0x8d8 0x07 0x00 0x8dc 0x1b 0x00 0x8e8 0x04 0x00 0x8ec 0x0e 0x00 0x8f0 0x4a 0x00 0x8f4 0x0f 0x00 0x8f8 0xc0 0x00 0x8fc 0x00 0x00 0x910 0x17 0x00 0x918 0x1c 0x00 0x91c 0x03 0x00 0x924 0x1e 0x00 0x970 0xbf 0x00 0x974 0x3f 0x00 0x978 0xff 0x00 0x97c 0x7f 0x00 0x980 0x15 0x00 0x984 0x24 0x00 0x988 0xe4 0x00 0x98c 0xec 0x00 0x990 0x3b 0x00 0x994 0x36 0x00 0x998 0xd4 0x00 0x99c 0x54 0x00 0x9a0 0xdb 0x00 0x9a4 0x3b 0x00 0x9a8 0x31 0x00 0x9bc 0x0c 0x00 0x9b8 0x38 0x00 0xadc 0x05 0x00 0xb88 0x77 0x00 0xb98 0x0b 0x00 0xba4 0x01 0x00 0xbe0 0x0f 0x00 0xe0c 0x0d 0x00 0xe14 0x07 0x00 0xe1c 0xc1 0x00 0xe40 0x01 0x00 0xe48 0x01 0x00 0xe90 0x00 0x00 0xeb4 0x33 0x00 0xebc 0x00 0x00 0xee0 0x58 0x00 0xa00 0x00 0x00 0xa44 0x03 0x00>; | |
| pcie2_rp { | |
| #address-cells = <0x05>; | |
| #size-cells = <0x00>; | |
| reg = <0x00 0x00 0x00 0x00 0x00>; | |
| phandle = <0x3dd>; | |
| qcom,mhi@0 { | |
| #address-cells = <0x01>; | |
| mhi,timeout = <0x7d0>; | |
| mhi,name = "esoc0"; | |
| qcom,msm-bus,name = "mhi0"; | |
| mhi,buffer-len = <0x8000>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| #size-cells = <0x01>; | |
| qcom,msm-bus,num-cases = <0x04>; | |
| esoc-names = "mdm"; | |
| qcom,iommu-group = <0x179>; | |
| reg = <0x00 0x00 0x00 0x00 0x00>; | |
| phandle = <0x3de>; | |
| qcom,msm-bus,vectors-KBps = <0x6c 0x200 0x00 0x00 0x6c 0x200 0x00 0x00 0x6c 0x200 0x7a120 0x00 0x6c 0x200 0xf4240 0x00>; | |
| mhi,sfr-support; | |
| mhi,max-channels = <0x6f>; | |
| esoc-0 = <0x61>; | |
| mhi_channels { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| phandle = <0x3df>; | |
| mhi_chan@10 { | |
| mhi,event-ring = <0x01>; | |
| label = "EFS"; | |
| mhi,data-type = <0x00>; | |
| mhi,num-elements = <0x40>; | |
| reg = <0x0a>; | |
| mhi,ee = <0x04>; | |
| mhi,chan-dir = <0x01>; | |
| mhi,doorbell-mode = <0x02>; | |
| }; | |
| mhi_chan@102 { | |
| mhi,lpm-notify; | |
| mhi,event-ring = <0x09>; | |
| label = "IP_HW_ADPL"; | |
| mhi,offload-chan; | |
| mhi,data-type = <0x03>; | |
| reg = <0x66>; | |
| mhi,ee = <0x04>; | |
| mhi,chan-dir = <0x02>; | |
| }; | |
| mhi_chan@19 { | |
| mhi,event-ring = <0x01>; | |
| label = "IP_CTRL"; | |
| mhi,data-type = <0x00>; | |
| mhi,num-elements = <0x40>; | |
| reg = <0x13>; | |
| mhi,ee = <0x04>; | |
| mhi,chan-dir = <0x02>; | |
| mhi,doorbell-mode = <0x02>; | |
| mhi,auto-queue; | |
| }; | |
| mhi_chan@5 { | |
| mhi,event-ring = <0x03>; | |
| label = "DIAG"; | |
| mhi,data-type = <0x00>; | |
| mhi,num-elements = <0x40>; | |
| reg = <0x05>; | |
| mhi,ee = <0x04>; | |
| mhi,chan-dir = <0x02>; | |
| mhi,doorbell-mode = <0x02>; | |
| }; | |
| mhi_chan@110 { | |
| mhi,event-ring = <0x10>; | |
| label = "RMNET_CTL"; | |
| mhi,data-type = <0x00>; | |
| mhi,num-elements = <0x80>; | |
| reg = <0x6e>; | |
| mhi,ee = <0x04>; | |
| mhi,chan-dir = <0x02>; | |
| mhi,doorbell-mode = <0x02>; | |
| }; | |
| mhi_chan@100 { | |
| mhi,event-ring = <0x07>; | |
| label = "IP_HW0"; | |
| mhi,db-mode-switch; | |
| mhi,data-type = <0x01>; | |
| mhi,num-elements = <0x200>; | |
| reg = <0x64>; | |
| mhi,ee = <0x04>; | |
| mhi,chan-dir = <0x01>; | |
| mhi,doorbell-mode = <0x03>; | |
| }; | |
| mhi_chan@27 { | |
| mhi,event-ring = <0x03>; | |
| label = "DCI"; | |
| mhi,data-type = <0x00>; | |
| mhi,num-elements = <0x40>; | |
| reg = <0x1b>; | |
| mhi,ee = <0x04>; | |
| mhi,chan-dir = <0x02>; | |
| mhi,doorbell-mode = <0x02>; | |
| }; | |
| mhi_chan@17 { | |
| mhi,event-ring = <0x03>; | |
| label = "QMI1"; | |
| mhi,data-type = <0x00>; | |
| mhi,num-elements = <0x40>; | |
| reg = <0x11>; | |
| mhi,ee = <0x04>; | |
| mhi,chan-dir = <0x02>; | |
| mhi,doorbell-mode = <0x02>; | |
| }; | |
| mhi_chan@3 { | |
| mhi,event-ring = <0x01>; | |
| label = "SAHARA"; | |
| mhi,data-type = <0x00>; | |
| mhi,num-elements = <0x80>; | |
| reg = <0x03>; | |
| mhi,ee = <0x02>; | |
| mhi,chan-dir = <0x02>; | |
| mhi,doorbell-mode = <0x02>; | |
| }; | |
| mhi_chan@73 { | |
| mhi,event-ring = <0x05>; | |
| label = "SLPI_3"; | |
| mhi,offload-chan; | |
| mhi,data-type = <0x03>; | |
| reg = <0x49>; | |
| mhi,ee = <0x04>; | |
| mhi,chan-dir = <0x00>; | |
| }; | |
| mhi_chan@109 { | |
| mhi,event-ring = <0x0f>; | |
| label = "RMNET_CTL"; | |
| mhi,data-type = <0x01>; | |
| mhi,num-elements = <0x80>; | |
| reg = <0x6d>; | |
| mhi,ee = <0x04>; | |
| mhi,chan-dir = <0x01>; | |
| mhi,doorbell-mode = <0x02>; | |
| }; | |
| mhi_chan@25 { | |
| mhi,auto-start; | |
| mhi,event-ring = <0x01>; | |
| label = "BL"; | |
| mhi,data-type = <0x00>; | |
| mhi,num-elements = <0x20>; | |
| reg = <0x19>; | |
| mhi,ee = <0x02>; | |
| mhi,chan-dir = <0x02>; | |
| mhi,doorbell-mode = <0x02>; | |
| mhi,auto-queue; | |
| }; | |
| mhi_chan@53 { | |
| mhi,event-ring = <0x05>; | |
| label = "SLPI_1"; | |
| mhi,offload-chan; | |
| mhi,data-type = <0x03>; | |
| reg = <0x35>; | |
| mhi,ee = <0x04>; | |
| mhi,chan-dir = <0x00>; | |
| }; | |
| mhi_chan@15 { | |
| mhi,event-ring = <0x02>; | |
| label = "QMI0"; | |
| mhi,data-type = <0x00>; | |
| mhi,num-elements = <0x40>; | |
| reg = <0x0f>; | |
| mhi,ee = <0x04>; | |
| mhi,chan-dir = <0x02>; | |
| mhi,doorbell-mode = <0x02>; | |
| }; | |
| mhi_chan@1 { | |
| mhi,event-ring = <0x02>; | |
| label = "LOOPBACK"; | |
| mhi,data-type = <0x00>; | |
| mhi,num-elements = <0x40>; | |
| reg = <0x01>; | |
| mhi,ee = <0x04>; | |
| mhi,chan-dir = <0x02>; | |
| mhi,doorbell-mode = <0x02>; | |
| }; | |
| mhi_chan@71 { | |
| mhi,event-ring = <0x04>; | |
| label = "ADSP_3"; | |
| mhi,offload-chan; | |
| mhi,data-type = <0x03>; | |
| reg = <0x47>; | |
| mhi,ee = <0x04>; | |
| mhi,chan-dir = <0x00>; | |
| }; | |
| mhi_chan@107 { | |
| mhi,event-ring = <0x0d>; | |
| label = "IP_HW_MHIP_1"; | |
| mhi,offload-chan; | |
| mhi,data-type = <0x03>; | |
| reg = <0x6b>; | |
| mhi,ee = <0x04>; | |
| mhi,chan-dir = <0x01>; | |
| }; | |
| mhi_chan@33 { | |
| mhi,event-ring = <0x03>; | |
| label = "DUN"; | |
| mhi,data-type = <0x00>; | |
| mhi,num-elements = <0x40>; | |
| reg = <0x21>; | |
| mhi,ee = <0x04>; | |
| mhi,chan-dir = <0x02>; | |
| mhi,doorbell-mode = <0x02>; | |
| }; | |
| mhi_chan@23 { | |
| mhi,event-ring = <0x02>; | |
| label = "TF"; | |
| mhi,data-type = <0x00>; | |
| mhi,num-elements = <0x40>; | |
| reg = <0x17>; | |
| mhi,ee = <0x04>; | |
| mhi,chan-dir = <0x02>; | |
| mhi,doorbell-mode = <0x02>; | |
| }; | |
| mhi_chan@51 { | |
| mhi,event-ring = <0x04>; | |
| label = "ADSP_1"; | |
| mhi,offload-chan; | |
| mhi,data-type = <0x03>; | |
| reg = <0x33>; | |
| mhi,ee = <0x04>; | |
| mhi,chan-dir = <0x00>; | |
| }; | |
| mhi_chan@105 { | |
| mhi,event-ring = <0x0b>; | |
| label = "IP_HW_MHIP_0"; | |
| mhi,offload-chan; | |
| mhi,data-type = <0x03>; | |
| reg = <0x69>; | |
| mhi,ee = <0x04>; | |
| mhi,chan-dir = <0x01>; | |
| }; | |
| mhi_chan@21 { | |
| mhi,auto-start; | |
| mhi,event-ring = <0x02>; | |
| label = "IPCR"; | |
| mhi,data-type = <0x00>; | |
| mhi,num-elements = <0x40>; | |
| reg = <0x15>; | |
| mhi,ee = <0x04>; | |
| mhi,chan-dir = <0x02>; | |
| mhi,doorbell-mode = <0x02>; | |
| mhi,auto-queue; | |
| }; | |
| mhi_chan@8 { | |
| mhi,event-ring = <0x01>; | |
| label = "QDSS"; | |
| mhi,data-type = <0x00>; | |
| mhi,num-elements = <0x40>; | |
| reg = <0x08>; | |
| mhi,ee = <0x04>; | |
| mhi,chan-dir = <0x01>; | |
| mhi,doorbell-mode = <0x02>; | |
| }; | |
| mhi_chan@11 { | |
| mhi,event-ring = <0x01>; | |
| label = "EFS"; | |
| mhi,wake-capable; | |
| mhi,data-type = <0x00>; | |
| mhi,num-elements = <0x40>; | |
| reg = <0x0b>; | |
| mhi,ee = <0x04>; | |
| mhi,chan-dir = <0x02>; | |
| mhi,doorbell-mode = <0x02>; | |
| }; | |
| mhi_chan@103 { | |
| mhi,event-ring = <0x0a>; | |
| label = "IP_HW_QDSS"; | |
| mhi,data-type = <0x00>; | |
| mhi,num-elements = <0x80>; | |
| reg = <0x67>; | |
| mhi,ee = <0x04>; | |
| mhi,chan-dir = <0x02>; | |
| mhi,doorbell-mode = <0x02>; | |
| }; | |
| mhi_chan@101 { | |
| mhi,event-ring = <0x08>; | |
| label = "IP_HW0"; | |
| mhi,data-type = <0x04>; | |
| mhi,num-elements = <0x200>; | |
| reg = <0x65>; | |
| mhi,ee = <0x04>; | |
| mhi,chan-dir = <0x02>; | |
| mhi,doorbell-mode = <0x03>; | |
| }; | |
| mhi_chan@18 { | |
| mhi,event-ring = <0x01>; | |
| label = "IP_CTRL"; | |
| mhi,data-type = <0x00>; | |
| mhi,num-elements = <0x40>; | |
| reg = <0x12>; | |
| mhi,ee = <0x04>; | |
| mhi,chan-dir = <0x01>; | |
| mhi,doorbell-mode = <0x02>; | |
| }; | |
| mhi_chan@4 { | |
| mhi,event-ring = <0x01>; | |
| label = "DIAG"; | |
| mhi,data-type = <0x00>; | |
| mhi,num-elements = <0x40>; | |
| reg = <0x04>; | |
| mhi,ee = <0x04>; | |
| mhi,chan-dir = <0x01>; | |
| mhi,doorbell-mode = <0x02>; | |
| }; | |
| mhi_chan@26 { | |
| mhi,event-ring = <0x03>; | |
| label = "DCI"; | |
| mhi,data-type = <0x00>; | |
| mhi,num-elements = <0x40>; | |
| reg = <0x1a>; | |
| mhi,ee = <0x04>; | |
| mhi,chan-dir = <0x01>; | |
| mhi,doorbell-mode = <0x02>; | |
| }; | |
| mhi_chan@16 { | |
| mhi,event-ring = <0x03>; | |
| label = "QMI1"; | |
| mhi,data-type = <0x00>; | |
| mhi,num-elements = <0x40>; | |
| reg = <0x10>; | |
| mhi,ee = <0x04>; | |
| mhi,chan-dir = <0x01>; | |
| mhi,doorbell-mode = <0x02>; | |
| }; | |
| mhi_chan@2 { | |
| mhi,event-ring = <0x01>; | |
| label = "SAHARA"; | |
| mhi,data-type = <0x00>; | |
| mhi,num-elements = <0x80>; | |
| reg = <0x02>; | |
| mhi,ee = <0x02>; | |
| mhi,chan-dir = <0x01>; | |
| mhi,doorbell-mode = <0x02>; | |
| }; | |
| mhi_chan@72 { | |
| mhi,event-ring = <0x05>; | |
| label = "SLPI_2"; | |
| mhi,offload-chan; | |
| mhi,data-type = <0x03>; | |
| reg = <0x48>; | |
| mhi,ee = <0x04>; | |
| mhi,chan-dir = <0x00>; | |
| }; | |
| mhi_chan@108 { | |
| mhi,lpm-notify; | |
| mhi,event-ring = <0x0e>; | |
| label = "IP_HW_MHIP_1"; | |
| mhi,offload-chan; | |
| mhi,data-type = <0x03>; | |
| reg = <0x6c>; | |
| mhi,ee = <0x04>; | |
| mhi,chan-dir = <0x02>; | |
| }; | |
| mhi_chan@52 { | |
| mhi,event-ring = <0x05>; | |
| label = "SLPI_0"; | |
| mhi,offload-chan; | |
| mhi,data-type = <0x03>; | |
| reg = <0x34>; | |
| mhi,ee = <0x04>; | |
| mhi,chan-dir = <0x00>; | |
| }; | |
| mhi_chan@80 { | |
| mhi,event-ring = <0x00>; | |
| label = "AUDIO_VOICE_0"; | |
| mhi,offload-chan; | |
| mhi,data-type = <0x03>; | |
| status = "ok"; | |
| reg = <0x50>; | |
| mhi,ee = <0x04>; | |
| mhi,chan-dir = <0x00>; | |
| }; | |
| mhi_chan@14 { | |
| mhi,event-ring = <0x01>; | |
| label = "QMI0"; | |
| mhi,data-type = <0x00>; | |
| mhi,num-elements = <0x40>; | |
| reg = <0x0e>; | |
| mhi,ee = <0x04>; | |
| mhi,chan-dir = <0x01>; | |
| mhi,doorbell-mode = <0x02>; | |
| }; | |
| mhi_chan@0 { | |
| mhi,event-ring = <0x02>; | |
| label = "LOOPBACK"; | |
| mhi,data-type = <0x00>; | |
| mhi,num-elements = <0x40>; | |
| reg = <0x00>; | |
| mhi,ee = <0x04>; | |
| mhi,chan-dir = <0x01>; | |
| mhi,doorbell-mode = <0x02>; | |
| }; | |
| mhi_chan@70 { | |
| mhi,event-ring = <0x04>; | |
| label = "ADSP_2"; | |
| mhi,offload-chan; | |
| mhi,data-type = <0x03>; | |
| reg = <0x46>; | |
| mhi,ee = <0x04>; | |
| mhi,chan-dir = <0x00>; | |
| }; | |
| mhi_chan@106 { | |
| mhi,lpm-notify; | |
| mhi,event-ring = <0x0c>; | |
| label = "IP_HW_MHIP_0"; | |
| mhi,offload-chan; | |
| mhi,data-type = <0x03>; | |
| reg = <0x6a>; | |
| mhi,ee = <0x04>; | |
| mhi,chan-dir = <0x02>; | |
| }; | |
| mhi_chan@32 { | |
| mhi,event-ring = <0x03>; | |
| label = "DUN"; | |
| mhi,data-type = <0x00>; | |
| mhi,num-elements = <0x40>; | |
| reg = <0x20>; | |
| mhi,ee = <0x04>; | |
| mhi,chan-dir = <0x01>; | |
| mhi,doorbell-mode = <0x02>; | |
| }; | |
| mhi_chan@22 { | |
| mhi,event-ring = <0x02>; | |
| label = "TF"; | |
| mhi,data-type = <0x00>; | |
| mhi,num-elements = <0x40>; | |
| reg = <0x16>; | |
| mhi,ee = <0x04>; | |
| mhi,chan-dir = <0x01>; | |
| mhi,doorbell-mode = <0x02>; | |
| }; | |
| mhi_chan@9 { | |
| mhi,event-ring = <0x01>; | |
| label = "QDSS"; | |
| mhi,data-type = <0x00>; | |
| mhi,num-elements = <0x80>; | |
| reg = <0x09>; | |
| mhi,ee = <0x04>; | |
| mhi,chan-dir = <0x02>; | |
| mhi,doorbell-mode = <0x02>; | |
| }; | |
| mhi_chan@50 { | |
| mhi,event-ring = <0x04>; | |
| label = "ADSP_0"; | |
| mhi,offload-chan; | |
| mhi,data-type = <0x03>; | |
| reg = <0x32>; | |
| mhi,ee = <0x04>; | |
| mhi,chan-dir = <0x00>; | |
| }; | |
| mhi_chan@104 { | |
| mhi,local-elements = <0xc06>; | |
| mhi,chan-type = <0x03>; | |
| mhi,event-ring = <0x08>; | |
| label = "IP_HW0_RSC"; | |
| mhi,data-type = <0x05>; | |
| mhi,num-elements = <0x200>; | |
| reg = <0x68>; | |
| mhi,ee = <0x04>; | |
| mhi,chan-dir = <0x02>; | |
| mhi,doorbell-mode = <0x03>; | |
| }; | |
| mhi_chan@20 { | |
| mhi,auto-start; | |
| mhi,event-ring = <0x02>; | |
| label = "IPCR"; | |
| mhi,data-type = <0x01>; | |
| mhi,num-elements = <0x40>; | |
| reg = <0x14>; | |
| mhi,ee = <0x04>; | |
| mhi,chan-dir = <0x01>; | |
| mhi,doorbell-mode = <0x02>; | |
| }; | |
| }; | |
| mhi_0_iommu_group { | |
| qcom,iommu-dma-addr-pool = <0x20000000 0x1fffffff>; | |
| phandle = <0x179>; | |
| qcom,iommu-pagetable = "coherent"; | |
| qcom,iommu-dma = "fastmap"; | |
| }; | |
| mhi_events { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| phandle = <0x3e0>; | |
| mhi_event@4 { | |
| mhi,brstmode = <0x03>; | |
| mhi,intmod = <0x05>; | |
| mhi,offload; | |
| mhi,priority = <0x01>; | |
| mhi,num-elements = <0x200>; | |
| mhi,msi = <0x00>; | |
| mhi,client-manage; | |
| }; | |
| mhi_event@12 { | |
| mhi,hw-ev; | |
| mhi,brstmode = <0x03>; | |
| mhi,chan = <0x6a>; | |
| mhi,intmod = <0x00>; | |
| mhi,offload; | |
| mhi,priority = <0x01>; | |
| mhi,num-elements = <0x00>; | |
| mhi,msi = <0x00>; | |
| mhi,client-manage; | |
| }; | |
| mhi_event@2 { | |
| mhi,brstmode = <0x02>; | |
| mhi,intmod = <0x00>; | |
| mhi,priority = <0x01>; | |
| mhi,num-elements = <0x100>; | |
| mhi,msi = <0x03>; | |
| }; | |
| mhi_event@10 { | |
| mhi,hw-ev; | |
| mhi,brstmode = <0x02>; | |
| mhi,chan = <0x67>; | |
| mhi,intmod = <0x05>; | |
| mhi,priority = <0x01>; | |
| mhi,num-elements = <0x400>; | |
| mhi,msi = <0x07>; | |
| }; | |
| mhi_event@0 { | |
| mhi,brstmode = <0x02>; | |
| mhi,intmod = <0x00>; | |
| mhi,data-type = <0x01>; | |
| mhi,priority = <0x00>; | |
| mhi,num-elements = <0x20>; | |
| reg = <0x00>; | |
| mhi,msi = <0x01>; | |
| }; | |
| mhi_event@9 { | |
| mhi,hw-ev; | |
| mhi,brstmode = <0x03>; | |
| mhi,chan = <0x66>; | |
| mhi,intmod = <0x00>; | |
| mhi,offload; | |
| mhi,priority = <0x01>; | |
| mhi,num-elements = <0x00>; | |
| mhi,msi = <0x00>; | |
| mhi,client-manage; | |
| }; | |
| mhi_event@7 { | |
| mhi,hw-ev; | |
| mhi,brstmode = <0x03>; | |
| mhi,chan = <0x64>; | |
| mhi,intmod = <0x05>; | |
| mhi,priority = <0x01>; | |
| mhi,num-elements = <0x400>; | |
| mhi,msi = <0x05>; | |
| }; | |
| mhi_event@15 { | |
| mhi,hw-ev; | |
| mhi,brstmode = <0x02>; | |
| mhi,chan = <0x6d>; | |
| mhi,intmod = <0x01>; | |
| mhi,priority = <0x00>; | |
| mhi,num-elements = <0x400>; | |
| mhi,msi = <0x08>; | |
| }; | |
| mhi_event@5 { | |
| mhi,brstmode = <0x03>; | |
| mhi,intmod = <0x05>; | |
| mhi,offload; | |
| mhi,priority = <0x01>; | |
| mhi,num-elements = <0x200>; | |
| mhi,msi = <0x00>; | |
| mhi,client-manage; | |
| }; | |
| mhi_event@13 { | |
| mhi,hw-ev; | |
| mhi,brstmode = <0x03>; | |
| mhi,chan = <0x6b>; | |
| mhi,intmod = <0x00>; | |
| mhi,offload; | |
| mhi,priority = <0x01>; | |
| mhi,num-elements = <0x00>; | |
| mhi,msi = <0x00>; | |
| mhi,client-manage; | |
| }; | |
| mhi_event@3 { | |
| mhi,brstmode = <0x02>; | |
| mhi,intmod = <0x00>; | |
| mhi,priority = <0x01>; | |
| mhi,num-elements = <0x100>; | |
| mhi,msi = <0x04>; | |
| }; | |
| mhi_event@11 { | |
| mhi,hw-ev; | |
| mhi,brstmode = <0x03>; | |
| mhi,chan = <0x69>; | |
| mhi,intmod = <0x00>; | |
| mhi,offload; | |
| mhi,priority = <0x01>; | |
| mhi,num-elements = <0x00>; | |
| mhi,msi = <0x00>; | |
| mhi,client-manage; | |
| }; | |
| mhi_event@1 { | |
| mhi,brstmode = <0x02>; | |
| mhi,intmod = <0x00>; | |
| mhi,priority = <0x01>; | |
| mhi,num-elements = <0x100>; | |
| mhi,msi = <0x02>; | |
| }; | |
| mhi_event@8 { | |
| mhi,hw-ev; | |
| mhi,brstmode = <0x03>; | |
| mhi,chan = <0x65>; | |
| mhi,intmod = <0x05>; | |
| mhi,force-uncached; | |
| mhi,priority = <0x01>; | |
| mhi,num-elements = <0x800>; | |
| mhi,msi = <0x06>; | |
| mhi,client-manage; | |
| }; | |
| mhi_event@16 { | |
| mhi,hw-ev; | |
| mhi,brstmode = <0x02>; | |
| mhi,chan = <0x6e>; | |
| mhi,intmod = <0x00>; | |
| mhi,priority = <0x00>; | |
| mhi,num-elements = <0x400>; | |
| mhi,msi = <0x09>; | |
| }; | |
| mhi_event@6 { | |
| mhi,brstmode = <0x02>; | |
| mhi,intmod = <0x00>; | |
| mhi,data-type = <0x03>; | |
| mhi,priority = <0x02>; | |
| mhi,num-elements = <0x40>; | |
| mhi,msi = <0x00>; | |
| }; | |
| mhi_event@14 { | |
| mhi,hw-ev; | |
| mhi,brstmode = <0x03>; | |
| mhi,chan = <0x6c>; | |
| mhi,intmod = <0x00>; | |
| mhi,offload; | |
| mhi,priority = <0x01>; | |
| mhi,num-elements = <0x00>; | |
| mhi,msi = <0x00>; | |
| mhi,client-manage; | |
| }; | |
| }; | |
| mhi_devices { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| phandle = <0x3e1>; | |
| mhi_qdss_dev_0 { | |
| mhi,chan = "QDSS"; | |
| mhi,default-channel; | |
| }; | |
| mhi_qrtr { | |
| mhi,early-notify; | |
| mhi,chan = "IPCR"; | |
| qcom,net-id = <0x03>; | |
| }; | |
| mhi_rmnet@0 { | |
| mhi,chan = "IP_HW0"; | |
| mhi,chain-skb; | |
| reg = <0x00>; | |
| mhi,mru = <0x8000>; | |
| phandle = <0x17b>; | |
| mhi,interface-name = "rmnet_mhi"; | |
| mhi,rsc-child = <0x17a>; | |
| }; | |
| mhi_dev@2 { | |
| mhi,early-notify; | |
| mhi,chan = "ADSP_0"; | |
| mhi,max-devices = <0x04>; | |
| reg = <0x02>; | |
| phandle = <0x3e2>; | |
| }; | |
| mhi_qdss_dev_1 { | |
| mhi,chan = "IP_HW_QDSS"; | |
| }; | |
| mhi_rmnet@1 { | |
| mhi,rsc-parent = <0x17b>; | |
| mhi,chan = "IP_HW0_RSC"; | |
| reg = <0x01>; | |
| mhi,mru = <0x8000>; | |
| phandle = <0x17a>; | |
| }; | |
| mhi_dev@3 { | |
| mhi,early-notify; | |
| mhi,chan = "SLPI_0"; | |
| mhi,max-devices = <0x04>; | |
| reg = <0x03>; | |
| phandle = <0x3e3>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| }; | |
| display_gpio_regulator@1 { | |
| regulator-max-microvolt = <0x53ec60>; | |
| pinctrl-names = "default"; | |
| regulator-boot-on; | |
| gpio = <0x66 0x3d 0x00>; | |
| pinctrl-0 = <0x63b>; | |
| regulator-enable-ramp-delay = <0xe9>; | |
| enable-active-high; | |
| regulator-min-microvolt = <0x53ec60>; | |
| regulator-name = "display_panel_avdd"; | |
| compatible = "regulator-fixed"; | |
| phandle = <0x63c>; | |
| }; | |
| qcom,msm-quat-auxpcm { | |
| qcom,msm-cpudai-auxpcm-quant = <0x02 0x02>; | |
| qcom,msm-cpudai-auxpcm-frame = <0x05 0x04>; | |
| qcom,msm-cpudai-auxpcm-sync = <0x01 0x01>; | |
| qcom,msm-auxpcm-interface = "quaternary"; | |
| qcom,msm-cpudai-auxpcm-slot-mapping = <0x01 0x01>; | |
| qcom,msm-cpudai-auxpcm-data = <0x00 0x00>; | |
| qcom,msm-cpudai-afe-clk-ver = <0x02>; | |
| qcom,msm-cpudai-auxpcm-num-slots = <0x01 0x01>; | |
| compatible = "qcom,msm-auxpcm-dev"; | |
| qcom,msm-cpudai-auxpcm-mode = <0x00 0x00>; | |
| phandle = <0x2f8>; | |
| qcom,msm-cpudai-auxpcm-pcm-clk-rate = <0x1f4000 0x1f4000>; | |
| }; | |
| rx_core_clk { | |
| qcom,codec-ext-clk-src = <0x05>; | |
| #clock-cells = <0x01>; | |
| compatible = "qcom,audio-ref-clk"; | |
| phandle = <0x655>; | |
| qcom,codec-lpass-clk-id = <0x30e>; | |
| qcom,codec-lpass-ext-clk-freq = <0x1588800>; | |
| }; | |
| qcom,msm-audio-apr { | |
| qcom,subsys-name = "apr_adsp"; | |
| compatible = "qcom,msm-audio-apr"; | |
| phandle = <0x5d8>; | |
| qcom,voice-mhi-audio { | |
| voice_mhi_voting; | |
| memory-region = <0x32d>; | |
| compatible = "qcom,voice-mhi-audio"; | |
| phandle = <0x5e3>; | |
| }; | |
| qcom,msm-audio-ion { | |
| iommus = <0x47 0x1801 0x00>; | |
| qcom,smmu-enabled; | |
| qcom,smmu-sid-mask = <0x00 0x0f>; | |
| compatible = "qcom,msm-audio-ion"; | |
| qcom,iommu-dma-addr-pool = <0x10000000 0x10000000>; | |
| phandle = <0x5d9>; | |
| qcom,smmu-version = <0x02>; | |
| }; | |
| qcom,q6core-audio { | |
| compatible = "qcom,q6core-audio"; | |
| phandle = <0x5da>; | |
| bolero-cdc { | |
| qcom,num-macros = <0x03>; | |
| clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; | |
| clocks = <0x2de 0x00 0x2df 0x00>; | |
| compatible = "qcom,bolero-codec"; | |
| phandle = <0x5db>; | |
| wcd938x-codec { | |
| qcom,rx-slave = <0x65e>; | |
| qcom,cdc-vdd-mic-bias-voltage = "\02K\0\02K"; | |
| qcom,cdc-vdd-mic-bias-current = <0x7530>; | |
| qcom,wcd-rst-gpio-node = <0x65d>; | |
| qcom,tx-slave = <0x65f>; | |
| qcom,tx_swr_ch_map = <0x00 0x12 0x01 0x00 0x12 0x00 0x13 0x02 0x00 0x13 0x01 0x14 0x01 0x00 0x14 0x01 0x15 0x02 0x00 0x15 0x02 0x16 0x01 0x00 0x16 0x02 0x17 0x02 0x00 0x17 0x02 0x11 0x04 0x00 0x18 0x02 0x18 0x04 0x00 0x18 0x02 0x19 0x08 0x00 0x19 0x03 0x1a 0x01 0x00 0x1a 0x03 0x1b 0x02 0x00 0x1b 0x03 0x1c 0x04 0x00 0x1c 0x03 0x1d 0x08 0x00 0x1d>; | |
| qcom,cdc-micbias2-mv = <0xa8c>; | |
| qcom,cdc-vdd-rxtx-voltage = <0x1b7740 0x1b7740>; | |
| qcom,rx_swr_ch_map = <0x00 0x09 0x01 0x00 0x09 0x00 0x0a 0x02 0x00 0x0a 0x01 0x0d 0x01 0x00 0x0d 0x02 0x0b 0x01 0x00 0x0b 0x02 0x0c 0x02 0x00 0x0c 0x03 0x0e 0x01 0x00 0x0e 0x04 0x0f 0x01 0x00 0x0f 0x04 0x10 0x02 0x00 0x10>; | |
| qcom,cdc-vdd-rxtx-current = <0x7530>; | |
| cdc-vdd-buck-supply = <0xa9>; | |
| qcom,cdc-static-supplies = "cdc-vdd-rxtx\0cdc-vddio\0cdc-vdd-buck\0cdc-vdd-mic-bias"; | |
| cdc-vdd-rxtx-supply = <0xa9>; | |
| qcom,cdc-vdd-buck-voltage = <0x1b7740 0x1b7740>; | |
| compatible = "qcom,wcd938x-codec"; | |
| qcom,cdc-vdd-buck-current = <0x9eb10>; | |
| qcom,cdc-vddio-voltage = <0x1b7740 0x1b7740>; | |
| qcom,cdc-micbias4-mv = <0x708>; | |
| cdc-vdd-mic-bias-supply = <0x2c9>; | |
| qcom,cdc-micbias1-mv = <0x708>; | |
| qcom,cdc-vddio-current = <0x7530>; | |
| cdc-vddio-supply = <0xa9>; | |
| phandle = <0x668>; | |
| qcom,split-codec = <0x01>; | |
| qcom,cdc-micbias3-mv = <0x708>; | |
| }; | |
| bolero-clk-rsc-mngr { | |
| qcom,wsa_mclk_mode_muxsel = <0x33220d8>; | |
| clock-names = "tx_core_clk\0tx_npl_clk\0rx_core_clk\0rx_npl_clk\0wsa_core_clk\0wsa_npl_clk\0va_core_clk\0va_npl_clk"; | |
| qcom,va_mclk_mode_muxsel = <0x33a0000>; | |
| clocks = <0x653 0x00 0x654 0x00 0x655 0x00 0x656 0x00 0x657 0x00 0x658 0x00 0x659 0x00 0x65a 0x00>; | |
| qcom,rx_mclk_mode_muxsel = <0x33240d8>; | |
| qcom,fs-gen-sequence = <0x3000 0x01 0x3004 0x01 0x3080 0x02>; | |
| compatible = "qcom,bolero-clk-rsc-mngr"; | |
| }; | |
| va-macro@3370000 { | |
| qcom,va-vdd-micb-voltage = <0x1b7740 0x1b7740>; | |
| qcom,default-clk-id = <0x00>; | |
| qcom,va-vdd-micb-current = <0x2bc0>; | |
| clock-names = "lpass_audio_hw_vote"; | |
| qcom,va-clk-mux-select = <0x01>; | |
| clocks = <0x2df 0x00>; | |
| va-vdd-micb-supply = <0xa9>; | |
| qcom,va-dmic-sample-rate = <0x927c0>; | |
| compatible = "qcom,va-macro"; | |
| qcom,va-island-mode-muxsel = <0x33a0000>; | |
| reg = <0x3370000 0x00>; | |
| phandle = <0x73d>; | |
| }; | |
| wsa-macro@3240000 { | |
| phandle = <0x5e0>; | |
| wsa_swr_master { | |
| phandle = <0x5e1>; | |
| }; | |
| }; | |
| rx-macro@3200000 { | |
| qcom,default-clk-id = <0x00>; | |
| clock-names = "rx_core_clk\0rx_npl_clk"; | |
| clocks = <0x655 0x00 0x656 0x00>; | |
| qcom,rx_mclk_mode_muxsel = <0x33240d8>; | |
| compatible = "qcom,rx-macro"; | |
| reg = <0x3200000 0x00>; | |
| qcom,rx-bcl-pmic-params = [00 04 3e]; | |
| phandle = <0x740>; | |
| qcom,rx-swr-gpios = <0x65c>; | |
| rx_swr_master { | |
| qcom,swr-clock-stop-mode0 = <0x01>; | |
| #address-cells = <0x02>; | |
| clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; | |
| qcom,swr-num-dev = <0x01>; | |
| interrupts = <0x00 0x12a 0x04>; | |
| clocks = <0x2de 0x00 0x2df 0x00>; | |
| swrm-io-base = <0x3210000 0x00>; | |
| #size-cells = <0x00>; | |
| qcom,swr_master_id = <0x02>; | |
| compatible = "qcom,swr-mstr"; | |
| qcom,mipi-sdw-block-packing-mode = <0x01>; | |
| interrupt-names = "swr_master_irq"; | |
| qcom,swr-port-mapping = <0x01 0x09 0x01 0x01 0x0a 0x02 0x02 0x0d 0x01 0x03 0x0b 0x01 0x03 0x0c 0x02 0x04 0x0e 0x01 0x05 0x0f 0x01 0x05 0x10 0x02>; | |
| phandle = <0x741>; | |
| qcom,swr-num-ports = <0x05>; | |
| qcom,disable-div2-clk-switch = <0x01>; | |
| wcd938x-rx-slave { | |
| compatible = "qcom,wcd938x-slave"; | |
| reg = <0x0d 0x1170224>; | |
| phandle = <0x65e>; | |
| }; | |
| }; | |
| }; | |
| tx-macro@3220000 { | |
| clock-names = "tx_core_clk\0tx_npl_clk"; | |
| clocks = <0x653 0x00 0x654 0x00>; | |
| qcom,tx-dmic-sample-rate = <0x249f00>; | |
| compatible = "qcom,tx-macro"; | |
| reg = <0x3220000 0x00>; | |
| phandle = <0x73e>; | |
| qcom,tx-swr-gpios = <0x65b>; | |
| tx_swr_master { | |
| qcom,swr-clock-stop-mode0 = <0x01>; | |
| #address-cells = <0x02>; | |
| clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; | |
| qcom,swr-num-dev = <0x01>; | |
| clocks = <0x2de 0x00 0x2df 0x00>; | |
| swrm-io-base = <0x3230000 0x00>; | |
| #size-cells = <0x00>; | |
| qcom,swr_master_id = <0x03>; | |
| interrupts-extended = <0x01 0x00 0x129 0x04 0x76 0x6d 0x04>; | |
| compatible = "qcom,swr-mstr"; | |
| qcom,mipi-sdw-block-packing-mode = <0x01>; | |
| interrupt-names = "swr_master_irq\0swr_wake_irq"; | |
| qcom,swr-port-mapping = <0x01 0x21 0x0f 0x02 0x12 0x01 0x02 0x13 0x02 0x03 0x14 0x01 0x03 0x15 0x02 0x04 0x16 0x01 0x04 0x17 0x02 0x04 0x18 0x04 0x04 0x19 0x08 0x05 0x1a 0x01 0x05 0x1b 0x02 0x05 0x1c 0x04 0x05 0x1d 0x08>; | |
| phandle = <0x73f>; | |
| qcom,swr-wakeup-required = <0x01>; | |
| qcom,swr-mstr-irq-wakeup-capable = <0x01>; | |
| qcom,swr-num-ports = <0x05>; | |
| wcd938x-tx-slave { | |
| compatible = "qcom,wcd938x-slave"; | |
| reg = <0x0d 0x1170223>; | |
| phandle = <0x65f>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| vote_lpass_core_hw { | |
| qcom,codec-ext-clk-src = <0x09>; | |
| #clock-cells = <0x01>; | |
| compatible = "qcom,audio-ref-clk"; | |
| phandle = <0x2de>; | |
| }; | |
| vote_lpass_audio_hw { | |
| qcom,codec-ext-clk-src = <0x0b>; | |
| #clock-cells = <0x01>; | |
| compatible = "qcom,audio-ref-clk"; | |
| phandle = <0x2df>; | |
| }; | |
| wsa_swr_clk_data_pinctrl { | |
| pinctrl-names = "aud_active\0aud_sleep"; | |
| pinctrl-0 = <0x676 0x677>; | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| qcom,lpi-gpios; | |
| pinctrl-1 = <0x678 0x679>; | |
| phandle = <0x742>; | |
| }; | |
| cdc_dmic01_pinctrl { | |
| pinctrl-names = "aud_active\0aud_sleep"; | |
| pinctrl-0 = <0x66a 0x66b>; | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| qcom,lpi-gpios; | |
| pinctrl-1 = <0x66c 0x66d>; | |
| status = "okay"; | |
| phandle = <0x660>; | |
| }; | |
| msm_cdc_pinctrl_tert { | |
| pinctrl-names = "aud_active\0aud_sleep"; | |
| pinctrl-0 = <0x45c 0x45e 0x460 0x462>; | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| pinctrl-1 = <0x45b 0x45d 0x45f 0x461>; | |
| phandle = <0x693>; | |
| }; | |
| cdc_dmic45_pinctrl { | |
| pinctrl-names = "aud_active\0aud_sleep"; | |
| pinctrl-0 = <0x672 0x673>; | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| qcom,lpi-gpios; | |
| pinctrl-1 = <0x674 0x675>; | |
| qcom,tlmm-gpio = <0x9e>; | |
| phandle = <0x662>; | |
| }; | |
| msm_cdc_pinctrl_pri { | |
| pinctrl-names = "aud_active\0aud_sleep"; | |
| pinctrl-0 = <0x44a 0x44c 0x44e 0x450>; | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| pinctrl-1 = <0x449 0x44b 0x44d 0x44f>; | |
| phandle = <0x692>; | |
| }; | |
| tx_swr_clk_data_pinctrl { | |
| pinctrl-names = "aud_active\0aud_sleep"; | |
| pinctrl-0 = <0x680 0x681 0x682>; | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| qcom,lpi-gpios; | |
| pinctrl-1 = <0x683 0x684 0x685>; | |
| qcom,tlmm-gpio = <0x93>; | |
| phandle = <0x65b>; | |
| }; | |
| sound { | |
| qcom,tert-mi2s-gpios = <0x693>; | |
| cirrus,prince-max-devs = <0x04>; | |
| qcom,audio-routing = "AMIC2\0MIC BIAS2\0MIC BIAS2\0Analog Mic2\0TX DMIC0\0Digital Mic0\0TX DMIC1\0Digital Mic1\0TX DMIC2\0Digital Mic2\0TX DMIC3\0Digital Mic3\0IN1_HPHL\0HPHL_OUT\0IN2_HPHR\0HPHR_OUT\0IN3_AUX\0AUX_OUT\0TX SWR_ADC0\0ADC1_OUTPUT\0TX SWR_ADC1\0ADC2_OUTPUT\0TX SWR_ADC2\0ADC3_OUTPUT\0TX SWR_ADC3\0ADC4_OUTPUT\0TX SWR_DMIC0\0DMIC1_OUTPUT\0TX SWR_DMIC1\0DMIC2_OUTPUT\0TX SWR_DMIC2\0DMIC3_OUTPUT\0TX SWR_DMIC3\0DMIC4_OUTPUT\0TX SWR_DMIC4\0DMIC5_OUTPUT\0TX SWR_DMIC5\0DMIC6_OUTPUT\0TX SWR_DMIC6\0DMIC7_OUTPUT\0TX SWR_DMIC7\0DMIC8_OUTPUT\0WSA SRC0_INP\0SRC0\0WSA_TX DEC0_INP\0TX DEC0 MUX\0WSA_TX DEC1_INP\0TX DEC1 MUX\0RX_TX DEC0_INP\0TX DEC0 MUX\0RX_TX DEC1_INP\0TX DEC1 MUX\0RX_TX DEC2_INP\0TX DEC2 MUX\0RX_TX DEC3_INP\0TX DEC3 MUX\0SpkrLeft IN\0WSA_SPK1 OUT\0SpkrRight IN\0WSA_SPK2 OUT\0VA_AIF1 CAP\0VA_SWR_CLK\0VA_AIF2 CAP\0VA_SWR_CLK\0VA_AIF3 CAP\0VA_SWR_CLK\0VA MIC BIAS3\0Digital Mic0\0VA MIC BIAS3\0Digital Mic1\0VA MIC BIAS1\0Digital Mic2\0VA MIC BIAS1\0Digital Mic3\0VA MIC BIAS4\0Digital Mic4\0VA MIC BIAS4\0Digital Mic5\0VA DMIC0\0VA MIC BIAS3\0VA DMIC1\0VA MIC BIAS3\0VA DMIC2\0VA MIC BIAS1\0VA DMIC3\0VA MIC BIAS1\0VA DMIC4\0VA MIC BIAS4\0VA DMIC5\0VA MIC BIAS4\0VA SWR_ADC0\0VA_SWR_CLK\0VA SWR_ADC1\0VA_SWR_CLK\0VA SWR_ADC2\0VA_SWR_CLK\0VA SWR_ADC3\0VA_SWR_CLK\0VA SWR_MIC0\0VA_SWR_CLK\0VA SWR_MIC1\0VA_SWR_CLK\0VA SWR_MIC2\0VA_SWR_CLK\0VA SWR_MIC3\0VA_SWR_CLK\0VA SWR_MIC4\0VA_SWR_CLK\0VA SWR_MIC5\0VA_SWR_CLK\0VA SWR_MIC6\0VA_SWR_CLK\0VA SWR_MIC7\0VA_SWR_CLK\0VA SWR_ADC0\0ADC1_OUTPUT\0VA SWR_ADC1\0ADC2_OUTPUT\0VA SWR_ADC2\0ADC3_OUTPUT\0VA SWR_ADC3\0ADC4_OUTPUT\0VA SWR_MIC0\0DMIC1_OUTPUT\0VA SWR_MIC1\0DMIC2_OUTPUT\0VA SWR_MIC2\0DMIC3_OUTPUT\0VA SWR_MIC3\0DMIC4_OUTPUT\0VA SWR_MIC4\0DMIC5_OUTPUT\0VA SWR_MIC5\0DMIC6_OUTPUT\0VA SWR_MIC6\0DMIC7_OUTPUT\0VA SWR_MIC7\0DMIC8_OUTPUT"; | |
| qcom,ext-disp-audio-rx = <0x01>; | |
| qcom,msm-mbhc-gnd-swh = <0x00>; | |
| asoc-codec = <0x5cd 0x5db 0x663 0x664 0x665 0x666 0x667>; | |
| qcom.msm-dmic-en-gpio = <0x626 0x0c 0x01>; | |
| clock-names = "lpass_audio_hw_vote"; | |
| asoc-cpu-names = "msm-dai-q6-dp.0\0msm-dai-q6-dp.1\0msm-dai-q6-mi2s.0\0msm-dai-q6-mi2s.1\0msm-dai-q6-mi2s.2\0msm-dai-q6-mi2s.3\0msm-dai-q6-mi2s.4\0msm-dai-q6-mi2s.5\0msm-dai-q6-auxpcm.1\0msm-dai-q6-auxpcm.2\0msm-dai-q6-auxpcm.3\0msm-dai-q6-auxpcm.4\0msm-dai-q6-auxpcm.5\0msm-dai-q6-auxpcm.6\0msm-dai-q6-dev.224\0msm-dai-q6-dev.225\0msm-dai-q6-dev.241\0msm-dai-q6-dev.240\0msm-dai-q6-dev.32771\0msm-dai-q6-dev.32772\0msm-dai-q6-dev.32773\0msm-dai-q6-dev.32770\0msm-dai-q6-dev.8194\0msm-dai-q6-dev.8195\0msm-dai-q6-dev.28672\0msm-dai-q6-dev.28673\0msm-dai-q6-dev.16398\0msm-dai-q6-dev.16399\0msm-dai-q6-tdm.36864\0msm-dai-q6-tdm.36865\0msm-dai-q6-tdm.36880\0msm-dai-q6-tdm.36881\0msm-dai-q6-tdm.36896\0msm-dai-q6-tdm.36897\0msm-dai-q6-tdm.36912\0msm-dai-q6-tdm.36913\0msm-dai-q6-tdm.36928\0msm-dai-q6-tdm.36929\0msm-dai-q6-tdm.36944\0msm-dai-q6-tdm.36945\0msm-dai-cdc-dma-dev.45056\0msm-dai-cdc-dma-dev.45057\0msm-dai-cdc-dma-dev.45058\0msm-dai-cdc-dma-dev.45059\0msm-dai-cdc-dma-dev.45061\0msm-dai-cdc-dma-dev.45089\0msm-dai-cdc-dma-dev.45091\0msm-dai-cdc-dma-dev.45093\0msm-dai-cdc-dma-dev.45104\0msm-dai-cdc-dma-dev.45105\0msm-dai-cdc-dma-dev.45106\0msm-dai-cdc-dma-dev.45107\0msm-dai-cdc-dma-dev.45108\0msm-dai-cdc-dma-dev.45109\0msm-dai-cdc-dma-dev.45110\0msm-dai-cdc-dma-dev.45111\0msm-dai-cdc-dma-dev.45112\0msm-dai-cdc-dma-dev.45113\0msm-dai-cdc-dma-dev.45114\0msm-dai-cdc-dma-dev.45115\0msm-dai-cdc-dma-dev.45116\0msm-dai-cdc-dma-dev.45118\0msm-dai-q6-dev.24577"; | |
| qcom,cdc-dmic01-gpios = <0x660>; | |
| qcom,afe-rxtx-lb = <0x00>; | |
| asoc-codec-names = "msm-stub-codec.1\0bolero_codec\0cs35l41_1\0cs35l41_2\0cs35l41_3\0cs35l41_4\0msm-ext-disp-audio-codec-rx"; | |
| cirrus,prince-dev-prefix = "SPK1\0SPK2\0SPK3\0SPK4"; | |
| clocks = <0x2df 0x00>; | |
| cirrus,prince-devs = <0x663 0x664 0x665 0x666>; | |
| qcom,msm-mbhc-usbc-audio-supported = <0x01>; | |
| qcom,msm_audio_ssr_devs = <0x5d8 0x5da 0x669 0x5db>; | |
| qcom,codec-aux-devs = <0x668>; | |
| asoc-cpu = <0x2ed 0x2ee 0x2ef 0x2f0 0x2f1 0x2f2 0x2f3 0x2f4 0x2f5 0x2f6 0x2f7 0x2f8 0x2f9 0x2fa 0x2fb 0x2fc 0x2fd 0x2fe 0x2ff 0x300 0x301 0x302 0x303 0x304 0x305 0x306 0x307 0x308 0x309 0x30a 0x30b 0x30c 0x30d 0x30e 0x30f 0x310 0x311 0x312 0x313 0x314 0x315 0x316 0x317 0x318 0x319 0x31a 0x31b 0x31c 0x31d 0x31e 0x31f 0x320 0x321 0x322 0x323 0x324 0x325 0x326 0x327 0x328 0x329 0x32a 0x32b>; | |
| qcom,msm-mi2s-master = <0x01 0x01 0x00 0x01 0x01 0x01>; | |
| qcom,msm-dmic-sel-gpio = <0x626 0x01 0x00>; | |
| qcom,model = "kona-mtp-snd-card"; | |
| qcom,tdm-audio-intf = <0x01>; | |
| qcom,cdc-dmic45-gpios = <0x662>; | |
| compatible = "qcom,kona-asoc-snd"; | |
| fsa4480-i2c-handle = <0x32c>; | |
| qcom,wcn-bt = <0x01>; | |
| qcom,msm-mbhc-hphl-swh = <0x00>; | |
| qcom,pri-mi2s-gpios = <0x692>; | |
| qcom,auxpcm-audio-intf = <0x01>; | |
| phandle = <0x5e2>; | |
| qcom,codec-max-aux-devs = <0x01>; | |
| asoc-platform-names = "msm-pcm-dsp.0\0msm-pcm-dsp.1\0msm-pcm-dsp.2\0msm-voip-dsp\0msm-pcm-voice\0msm-pcm-loopback\0msm-compress-dsp\0msm-pcm-hostless\0msm-pcm-afe\0msm-lsm-client\0msm-pcm-routing\0msm-compr-dsp\0msm-pcm-dsp-noirq"; | |
| qcom,mi2s-audio-intf = <0x01>; | |
| qcom,wsa-aux-dev-prefix = "SpkrLeft\0SpkrRight\0SpkrLeft\0SpkrRight"; | |
| qcom,wsa-max-devs = <0x00>; | |
| asoc-platform = <0x2e0 0x2e1 0x2e2 0x2e3 0x2e4 0x2e5 0x2e6 0x2e7 0x2e8 0x2e9 0x2ea 0x2eb 0x2ec>; | |
| qcom,cdc-dmic23-gpios = <0x661>; | |
| }; | |
| lpi_pinctrl@33c0000 { | |
| qcom,num-gpios = <0x0e>; | |
| clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; | |
| gpio-controller; | |
| qcom,lpi-slew-offset-tbl = <0x00 0x02 0x04 0x08 0x0a 0x0c 0x00 0x00 0x00 0x00 0x10 0x12 0x00 0x00>; | |
| clocks = <0x2de 0x00 0x2df 0x00>; | |
| qcom,lpi-offset-tbl = <0x00 0x1000 0x2000 0x3000 0x4000 0x5000 0x6000 0x7000 0x8000 0x9000 0xa000 0xb000 0xc000 0xd000>; | |
| compatible = "qcom,lpi-pinctrl"; | |
| reg = <0x33c0000 0x00>; | |
| phandle = <0x669>; | |
| #gpio-cells = <0x02>; | |
| qcom,slew-reg = <0x355a000 0x00>; | |
| quat_mi2s_sd1 { | |
| quat_mi2s_sd1_sleep { | |
| phandle = <0x6ef>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio3"; | |
| }; | |
| config { | |
| pins = "gpio3"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| quat_mi2s_sd1_active { | |
| phandle = <0x6f0>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio3"; | |
| }; | |
| config { | |
| pins = "gpio3"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| quat_aux_sd3 { | |
| quat_aux_sd3_active { | |
| phandle = <0x72c>; | |
| mux { | |
| function = "func4"; | |
| pins = "gpio5"; | |
| }; | |
| config { | |
| pins = "gpio5"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| quat_aux_sd3_sleep { | |
| phandle = <0x72b>; | |
| mux { | |
| function = "func4"; | |
| pins = "gpio5"; | |
| }; | |
| config { | |
| pins = "gpio5"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| lpi_aux1_sck { | |
| lpi_aux1_sck_active { | |
| phandle = <0x72e>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio6"; | |
| }; | |
| config { | |
| pins = "gpio6"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_aux1_sck_sleep { | |
| phandle = <0x72d>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio6"; | |
| }; | |
| config { | |
| pins = "gpio6"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| rx_swr_clk_active { | |
| phandle = <0x67a>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio3"; | |
| }; | |
| config { | |
| pins = "gpio3"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| lpi_i2s2_sck { | |
| lpi_i2s2_sck_sleep { | |
| phandle = <0x6fd>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio10"; | |
| }; | |
| config { | |
| pins = "gpio10"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| lpi_i2s2_sck_active { | |
| phandle = <0x6fe>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio10"; | |
| }; | |
| config { | |
| pins = "gpio10"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| lpi_aux2_ws { | |
| lpi_aux2_ws_active { | |
| phandle = <0x738>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio11"; | |
| }; | |
| config { | |
| pins = "gpio11"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_aux2_ws_sleep { | |
| phandle = <0x737>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio11"; | |
| }; | |
| config { | |
| pins = "gpio11"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| quat_aux_sd1 { | |
| quat_aux_sd1_active { | |
| phandle = <0x728>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio3"; | |
| }; | |
| config { | |
| pins = "gpio3"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| quat_aux_sd1_sleep { | |
| phandle = <0x727>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio3"; | |
| }; | |
| config { | |
| pins = "gpio3"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| rx_swr_clk_sleep { | |
| phandle = <0x67d>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio3"; | |
| }; | |
| config { | |
| pins = "gpio3"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| quat_tdm_ws { | |
| quat_tdm_ws_active { | |
| phandle = <0x708>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio1"; | |
| }; | |
| config { | |
| pins = "gpio1"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| quat_tdm_ws_sleep { | |
| phandle = <0x707>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio1"; | |
| }; | |
| config { | |
| pins = "gpio1"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| lpi_aux1_sd0 { | |
| lpi_aux1_sd0_active { | |
| phandle = <0x732>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio8"; | |
| }; | |
| config { | |
| pins = "gpio8"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_aux1_sd0_sleep { | |
| phandle = <0x731>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio8"; | |
| }; | |
| config { | |
| pins = "gpio8"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| dmic45_data_sleep { | |
| phandle = <0x675>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio13"; | |
| }; | |
| config { | |
| pins = "gpio13"; | |
| drive-strength = <0x02>; | |
| pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| rx_swr_data1_active { | |
| phandle = <0x67c>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio5"; | |
| }; | |
| config { | |
| pins = "gpio5"; | |
| drive-strength = <0x02>; | |
| bias-bus-hold; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| lpi_i2s1_ws { | |
| lpi_i2s1_ws_active { | |
| phandle = <0x6f8>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio7"; | |
| }; | |
| config { | |
| pins = "gpio7"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_i2s1_ws_sleep { | |
| phandle = <0x6f7>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio7"; | |
| }; | |
| config { | |
| pins = "gpio7"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| dmic45_data_active { | |
| phandle = <0x673>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio13"; | |
| }; | |
| config { | |
| pins = "gpio13"; | |
| drive-strength = <0x08>; | |
| input-enable; | |
| }; | |
| }; | |
| lpi_i2s2_sd0 { | |
| lpi_i2s2_sd0_sleep { | |
| phandle = <0x701>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio12"; | |
| }; | |
| config { | |
| pins = "gpio12"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| lpi_i2s2_sd0_active { | |
| phandle = <0x702>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio12"; | |
| }; | |
| config { | |
| pins = "gpio12"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| lpi_tdm2_sd1 { | |
| lpi_tdm2_sd1_active { | |
| phandle = <0x720>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio13"; | |
| }; | |
| config { | |
| pins = "gpio13"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_tdm2_sd1_sleep { | |
| phandle = <0x71f>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio13"; | |
| }; | |
| config { | |
| pins = "gpio13"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| dmic01_clk_active { | |
| phandle = <0x66a>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio6"; | |
| }; | |
| config { | |
| pins = "gpio6"; | |
| drive-strength = <0x08>; | |
| output-high; | |
| }; | |
| }; | |
| dmic01_clk_sleep { | |
| phandle = <0x66c>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio6"; | |
| }; | |
| config { | |
| pins = "gpio6"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| output-low; | |
| }; | |
| }; | |
| lpi_aux2_sck { | |
| lpi_aux2_sck_sleep { | |
| phandle = <0x735>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio10"; | |
| }; | |
| config { | |
| pins = "gpio10"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| lpi_aux2_sck_active { | |
| phandle = <0x736>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio10"; | |
| }; | |
| config { | |
| pins = "gpio10"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| lpi_tdm1_ws { | |
| lpi_tdm1_ws_active { | |
| phandle = <0x714>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio7"; | |
| }; | |
| config { | |
| pins = "gpio7"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_tdm1_ws_sleep { | |
| phandle = <0x713>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio7"; | |
| }; | |
| config { | |
| pins = "gpio7"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| quat_aux_ws { | |
| quat_aux_ws_sleep { | |
| phandle = <0x723>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio1"; | |
| }; | |
| config { | |
| pins = "gpio1"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| quat_aux_ws_active { | |
| phandle = <0x724>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio1"; | |
| }; | |
| config { | |
| pins = "gpio1"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| rx_swr_data_active { | |
| phandle = <0x67b>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio4"; | |
| }; | |
| config { | |
| pins = "gpio4"; | |
| drive-strength = <0x02>; | |
| bias-bus-hold; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| dmic23_data_sleep { | |
| phandle = <0x671>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio9"; | |
| }; | |
| config { | |
| pins = "gpio9"; | |
| drive-strength = <0x02>; | |
| pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| lpi_i2s1_sd1 { | |
| lpi_i2s1_sd1_active { | |
| phandle = <0x6fc>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio9"; | |
| }; | |
| config { | |
| pins = "gpio9"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_i2s1_sd1_sleep { | |
| phandle = <0x6fb>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio9"; | |
| }; | |
| config { | |
| pins = "gpio9"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| lpi_aux2_sd0 { | |
| lpi_aux2_sd0_sleep { | |
| phandle = <0x739>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio12"; | |
| }; | |
| config { | |
| pins = "gpio12"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| lpi_aux2_sd0_active { | |
| phandle = <0x73a>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio12"; | |
| }; | |
| config { | |
| pins = "gpio12"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| lpi_tdm1_sck { | |
| lpi_tdm1_sck_active { | |
| phandle = <0x712>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio6"; | |
| }; | |
| config { | |
| pins = "gpio6"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_tdm1_sck_sleep { | |
| phandle = <0x711>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio6"; | |
| }; | |
| config { | |
| pins = "gpio6"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| wsa_swr_data_pin { | |
| wsa_swr_data_active { | |
| phandle = <0x677>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio11"; | |
| }; | |
| config { | |
| pins = "gpio11"; | |
| drive-strength = <0x02>; | |
| bias-bus-hold; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| wsa_swr_data_sleep { | |
| phandle = <0x679>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio11"; | |
| }; | |
| config { | |
| pins = "gpio11"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| rx_swr_data_sleep { | |
| phandle = <0x67e>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio4"; | |
| }; | |
| config { | |
| pins = "gpio4"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| quat_tdm_sd2 { | |
| quat_tdm_sd2_sleep { | |
| phandle = <0x70d>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio4"; | |
| }; | |
| config { | |
| pins = "gpio4"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| quat_tdm_sd2_active { | |
| phandle = <0x70e>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio4"; | |
| }; | |
| config { | |
| pins = "gpio4"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| quat_tdm_sck { | |
| quat_tdm_sck_active { | |
| phandle = <0x706>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio0"; | |
| }; | |
| config { | |
| pins = "gpio0"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| quat_tdm_sck_sleep { | |
| phandle = <0x705>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio0"; | |
| }; | |
| config { | |
| pins = "gpio0"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| lpi_aux1_ws { | |
| lpi_aux1_ws_active { | |
| phandle = <0x730>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio7"; | |
| }; | |
| config { | |
| pins = "gpio7"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_aux1_ws_sleep { | |
| phandle = <0x72f>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio7"; | |
| }; | |
| config { | |
| pins = "gpio7"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| dmic45_clk_sleep { | |
| phandle = <0x674>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio12"; | |
| }; | |
| config { | |
| pins = "gpio12"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| output-low; | |
| }; | |
| }; | |
| quat_mi2s_sd2 { | |
| quat_mi2s_sd2_sleep { | |
| phandle = <0x6f1>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio4"; | |
| }; | |
| config { | |
| pins = "gpio4"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| quat_mi2s_sd2_active { | |
| phandle = <0x6f2>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio4"; | |
| }; | |
| config { | |
| pins = "gpio4"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| quat_mi2s_sck { | |
| quat_mi2s_sck_sleep { | |
| phandle = <0x6e9>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio0"; | |
| }; | |
| config { | |
| pins = "gpio0"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| quat_mi2s_sck_active { | |
| phandle = <0x6ea>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio0"; | |
| }; | |
| config { | |
| pins = "gpio0"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| lpi_tdm1_sd0 { | |
| lpi_tdm1_sd0_active { | |
| phandle = <0x716>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio8"; | |
| }; | |
| config { | |
| pins = "gpio8"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_tdm1_sd0_sleep { | |
| phandle = <0x715>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio8"; | |
| }; | |
| config { | |
| pins = "gpio8"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| quat_mi2s_ws { | |
| quat_mi2s_ws_sleep { | |
| phandle = <0x6eb>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio1"; | |
| }; | |
| config { | |
| pins = "gpio1"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| quat_mi2s_ws_active { | |
| phandle = <0x6ec>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio1"; | |
| }; | |
| config { | |
| pins = "gpio1"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| quat_tdm_sd0 { | |
| quat_tdm_sd0_sleep { | |
| phandle = <0x709>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio2"; | |
| }; | |
| config { | |
| pins = "gpio2"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| quat_tdm_sd0_active { | |
| phandle = <0x70a>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio2"; | |
| }; | |
| config { | |
| pins = "gpio2"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| tx_swr_data1_sleep { | |
| phandle = <0x684>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio1"; | |
| }; | |
| config { | |
| pins = "gpio1"; | |
| drive-strength = <0x02>; | |
| bias-bus-hold; | |
| input-enable; | |
| }; | |
| }; | |
| quat_mi2s_sd0 { | |
| quat_mi2s_sd0_sleep { | |
| phandle = <0x6ed>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio2"; | |
| }; | |
| config { | |
| pins = "gpio2"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| quat_mi2s_sd0_active { | |
| phandle = <0x6ee>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio2"; | |
| }; | |
| config { | |
| pins = "gpio2"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| dmic01_data_sleep { | |
| phandle = <0x66d>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio7"; | |
| }; | |
| config { | |
| pins = "gpio7"; | |
| drive-strength = <0x02>; | |
| pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| quat_aux_sd2 { | |
| quat_aux_sd2_active { | |
| phandle = <0x72a>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio4"; | |
| }; | |
| config { | |
| pins = "gpio4"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| quat_aux_sd2_sleep { | |
| phandle = <0x729>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio4"; | |
| }; | |
| config { | |
| pins = "gpio4"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| dmic23_data_active { | |
| phandle = <0x66f>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio9"; | |
| }; | |
| config { | |
| pins = "gpio9"; | |
| drive-strength = <0x08>; | |
| input-enable; | |
| }; | |
| }; | |
| quat_aux_sck { | |
| quat_aux_sck_active { | |
| phandle = <0x722>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio0"; | |
| }; | |
| config { | |
| pins = "gpio0"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| quat_aux_sck_sleep { | |
| phandle = <0x721>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio0"; | |
| }; | |
| config { | |
| pins = "gpio0"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| lpi_aux1_sd1 { | |
| lpi_aux1_sd1_active { | |
| phandle = <0x734>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio9"; | |
| }; | |
| config { | |
| pins = "gpio9"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_aux1_sd1_sleep { | |
| phandle = <0x733>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio9"; | |
| }; | |
| config { | |
| pins = "gpio9"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| rx_swr_data1_sleep { | |
| phandle = <0x67f>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio5"; | |
| }; | |
| config { | |
| pins = "gpio5"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| lpi_i2s2_sd1 { | |
| lpi_i2s2_sd1_sleep { | |
| phandle = <0x703>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio13"; | |
| }; | |
| config { | |
| pins = "gpio13"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| lpi_i2s2_sd1_active { | |
| phandle = <0x704>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio13"; | |
| }; | |
| config { | |
| pins = "gpio13"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| lpi_tdm2_sck { | |
| lpi_tdm2_sck_active { | |
| phandle = <0x71a>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio10"; | |
| }; | |
| config { | |
| pins = "gpio10"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_tdm2_sck_sleep { | |
| phandle = <0x719>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio10"; | |
| }; | |
| config { | |
| pins = "gpio10"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| quat_aux_sd0 { | |
| quat_aux_sd0_active { | |
| phandle = <0x726>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio2"; | |
| }; | |
| config { | |
| pins = "gpio2"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| quat_aux_sd0_sleep { | |
| phandle = <0x725>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio2"; | |
| }; | |
| config { | |
| pins = "gpio2"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| tx_swr_clk_sleep { | |
| phandle = <0x683>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio0"; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| config { | |
| pins = "gpio0"; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| lpi_tdm2_sd0 { | |
| lpi_tdm2_sd0_active { | |
| phandle = <0x71e>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio12"; | |
| }; | |
| config { | |
| pins = "gpio12"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_tdm2_sd0_sleep { | |
| phandle = <0x71d>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio12"; | |
| }; | |
| config { | |
| pins = "gpio12"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| dmic45_clk_active { | |
| phandle = <0x672>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio12"; | |
| }; | |
| config { | |
| pins = "gpio12"; | |
| drive-strength = <0x08>; | |
| output-high; | |
| }; | |
| }; | |
| tx_swr_clk_active { | |
| phandle = <0x680>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio0"; | |
| }; | |
| config { | |
| pins = "gpio0"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| wsa_swr_clk_pin { | |
| wsa_swr_clk_active { | |
| phandle = <0x676>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio10"; | |
| }; | |
| config { | |
| pins = "gpio10"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| wsa_swr_clk_sleep { | |
| phandle = <0x678>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio10"; | |
| }; | |
| config { | |
| pins = "gpio10"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| lpi_i2s2_ws { | |
| lpi_i2s2_ws_sleep { | |
| phandle = <0x6ff>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio11"; | |
| }; | |
| config { | |
| pins = "gpio11"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| lpi_i2s2_ws_active { | |
| phandle = <0x700>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio11"; | |
| }; | |
| config { | |
| pins = "gpio11"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| lpi_i2s1_sck { | |
| lpi_i2s1_sck_active { | |
| phandle = <0x6f6>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio6"; | |
| }; | |
| config { | |
| pins = "gpio6"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_i2s1_sck_sleep { | |
| phandle = <0x6f5>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio6"; | |
| }; | |
| config { | |
| pins = "gpio6"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| tx_swr_data1_active { | |
| phandle = <0x681>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio1"; | |
| }; | |
| config { | |
| pins = "gpio1"; | |
| drive-strength = <0x02>; | |
| bias-bus-hold; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| tx_swr_data2_sleep { | |
| phandle = <0x685>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio2"; | |
| }; | |
| config { | |
| pins = "gpio2"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| lpi_aux2_sd1 { | |
| lpi_aux2_sd1_sleep { | |
| phandle = <0x73b>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio13"; | |
| }; | |
| config { | |
| pins = "gpio13"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| lpi_aux2_sd1_active { | |
| phandle = <0x73c>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio13"; | |
| }; | |
| config { | |
| pins = "gpio13"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| dmic23_clk_sleep { | |
| phandle = <0x670>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio8"; | |
| }; | |
| config { | |
| pins = "gpio8"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| output-low; | |
| }; | |
| }; | |
| quat_tdm_sd3 { | |
| quat_tdm_sd3_sleep { | |
| phandle = <0x70f>; | |
| mux { | |
| function = "func4"; | |
| pins = "gpio5"; | |
| }; | |
| config { | |
| pins = "gpio5"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| quat_tdm_sd3_active { | |
| phandle = <0x710>; | |
| mux { | |
| function = "func4"; | |
| pins = "gpio5"; | |
| }; | |
| config { | |
| pins = "gpio5"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| tx_swr_data2_active { | |
| phandle = <0x682>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio2"; | |
| }; | |
| config { | |
| pins = "gpio2"; | |
| drive-strength = <0x02>; | |
| bias-bus-hold; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| lpi_i2s1_sd0 { | |
| lpi_i2s1_sd0_active { | |
| phandle = <0x6fa>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio8"; | |
| }; | |
| config { | |
| pins = "gpio8"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_i2s1_sd0_sleep { | |
| phandle = <0x6f9>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio8"; | |
| }; | |
| config { | |
| pins = "gpio8"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| quat_mi2s_sd3 { | |
| quat_mi2s_sd3_sleep { | |
| phandle = <0x6f3>; | |
| mux { | |
| function = "func4"; | |
| pins = "gpio5"; | |
| }; | |
| config { | |
| pins = "gpio5"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| quat_mi2s_sd3_active { | |
| phandle = <0x6f4>; | |
| mux { | |
| function = "func4"; | |
| pins = "gpio5"; | |
| }; | |
| config { | |
| pins = "gpio5"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| lpi_tdm1_sd1 { | |
| lpi_tdm1_sd1_active { | |
| phandle = <0x718>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio9"; | |
| }; | |
| config { | |
| pins = "gpio9"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| lpi_tdm1_sd1_sleep { | |
| phandle = <0x717>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio9"; | |
| }; | |
| config { | |
| pins = "gpio9"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| lpi_tdm2_ws { | |
| lpi_tdm2_ws_sleep { | |
| phandle = <0x71b>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio11"; | |
| }; | |
| config { | |
| pins = "gpio11"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| lpi_tdm2_ws_active { | |
| phandle = <0x71c>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio11"; | |
| }; | |
| config { | |
| pins = "gpio11"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| quat_tdm_sd1 { | |
| quat_tdm_sd1_active { | |
| phandle = <0x70c>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio3"; | |
| }; | |
| config { | |
| pins = "gpio3"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| quat_tdm_sd1_sleep { | |
| phandle = <0x70b>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio3"; | |
| }; | |
| config { | |
| pins = "gpio3"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| dmic23_clk_active { | |
| phandle = <0x66e>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio8"; | |
| }; | |
| config { | |
| pins = "gpio8"; | |
| drive-strength = <0x08>; | |
| output-high; | |
| }; | |
| }; | |
| dmic01_data_active { | |
| phandle = <0x66b>; | |
| mux { | |
| function = "func1"; | |
| pins = "gpio7"; | |
| }; | |
| config { | |
| pins = "gpio7"; | |
| drive-strength = <0x08>; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| cdc_dmic23_pinctrl { | |
| pinctrl-names = "aud_active\0aud_sleep"; | |
| pinctrl-0 = <0x66e 0x66f>; | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| qcom,lpi-gpios; | |
| pinctrl-1 = <0x670 0x671>; | |
| status = "okay"; | |
| phandle = <0x661>; | |
| }; | |
| rx_swr_clk_data_pinctrl { | |
| pinctrl-names = "aud_active\0aud_sleep"; | |
| pinctrl-0 = <0x67a 0x67b 0x67c>; | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| qcom,lpi-gpios; | |
| pinctrl-1 = <0x67d 0x67e 0x67f>; | |
| phandle = <0x65c>; | |
| }; | |
| }; | |
| }; | |
| dbmdx { | |
| va-preboot-firmware-name = "dbmd8_va_preboot_fw.bin"; | |
| default_va_clock = <0x5dc0000>; | |
| multi-interface-support = <0x01>; | |
| va_backlog_length_okg = <0x3e8>; | |
| detection_buffer_channels = <0x00>; | |
| send_uevent_after_buffering = <0x01>; | |
| asrp_tx_out_gain = <0x59f>; | |
| va-interfaces = <0x00 0x00 0x00 0x00>; | |
| firmware_id = <0xdbd8>; | |
| wakeup-gpio = <0x66 0x0f 0x00>; | |
| auto_buffering = <0x01>; | |
| change_clock_src_options = <0x4003>; | |
| asrp_vcpf_out_gain = <0x2cfc>; | |
| asrp_rx_out_gain = <0x2cfc>; | |
| default-streaming-usecase-name = "uc_melon_ga_2mic_aec_48k"; | |
| va-firmware-name = "dbmd8_va_fw.bin"; | |
| alsa_streaming_options = <0x08>; | |
| cd-interfaces = <0x652>; | |
| send_uevent_on_detection = <0x01>; | |
| wakeup_disabled = <0x00>; | |
| reset-gpio = <0x66 0x0a 0x00>; | |
| wakeup_set_value = <0x00>; | |
| vdd-supply = <0x386>; | |
| buffering_timeout = <0x05>; | |
| hw_revision = <0x00>; | |
| pcm_streaming_mode = <0x01>; | |
| compatible = "dspg,dbmdx-codec"; | |
| feature-va_ve; | |
| use_gpio_for_wakeup = <0x01>; | |
| low_power_mode_disabled = <0x00>; | |
| va-config = <0x80000000 0x80000000 0x80000000 0x80290020 0x801b0020 0x80091800 0x80221001 0x80330076 0x80230000 0x801a0013 0x80159494 0x80104002 0x8aab0040 0x800c2710 0x80240248 0x80250267 0x8aab0064 0x80250000 0x80240000 0x80000000 0x80000000 0x80000000>; | |
| status = "okay"; | |
| amodel_options = <0x01>; | |
| va-mic-config = <0x5076 0xa061 0x08>; | |
| va-mic-mode = <0x02>; | |
| va_ve-mic-config = <0x5076 0xa061 0xa093 0x00>; | |
| va_backlog_length = <0x1f6>; | |
| asrp_delay = <0x01>; | |
| detection_after_buffering = <0x02>; | |
| master-clk-rate = <0x8000>; | |
| project_sub_type = <0x01>; | |
| reset_gpio_shared = <0x00>; | |
| boot_options = <0x220>; | |
| va-speeds = <0x00 0x70800 0x00 0xf4240 0x00 0x1e8480 0x00 0x2dc6c0 0x00 0x2dc6c0 0x00 0x4c4b40>; | |
| uart_low_speed_enabled = <0x01>; | |
| send_wakeup_seq = <0x00>; | |
| auto_detection = <0x01>; | |
| }; | |
| ipcc-self-ping-npu { | |
| interrupts-extended = <0x8a 0x07 0x03 0x04>; | |
| compatible = "qcom,ipcc-self-ping"; | |
| phandle = <0x612>; | |
| mboxes = <0x3f 0x07 0x03>; | |
| }; | |
| qcom,msm-dai-fe { | |
| compatible = "qcom,msm-dai-fe"; | |
| }; | |
| funnel@6c0b000 { | |
| arm,primecell-periphid = <0xbb908>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "funnel-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-funnel-dl-mm"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6c0b000 0x1000>; | |
| phandle = <0x501>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x211>; | |
| phandle = <0x1ff>; | |
| }; | |
| }; | |
| port@3 { | |
| reg = <0x03>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x214>; | |
| phandle = <0x219>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x00>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x212>; | |
| phandle = <0x215>; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x01>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x213>; | |
| phandle = <0x218>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| cti@6982000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti-turing_dl_cti"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6982000 0x1000>; | |
| phandle = <0x541>; | |
| }; | |
| ipcc-self-ping-apss { | |
| interrupts-extended = <0x8a 0x08 0x02 0x04>; | |
| compatible = "qcom,ipcc-self-ping"; | |
| phandle = <0x60e>; | |
| mboxes = <0x8a 0x08 0x02>; | |
| }; | |
| spi@a90000 { | |
| pinctrl-names = "default\0sleep"; | |
| #address-cells = <0x01>; | |
| pinctrl-0 = <0x2b8>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| reg-names = "se_phys"; | |
| interrupts = <0x00 0x165 0x04>; | |
| clocks = <0x16 0x72 0x16 0x86 0x16 0x87>; | |
| #size-cells = <0x00>; | |
| qcom,wrapper-core = <0x2a3>; | |
| spi-max-frequency = <0x2faf080>; | |
| dma-names = "tx\0rx"; | |
| compatible = "qcom,spi-geni"; | |
| pinctrl-1 = <0x2b9>; | |
| status = "disabled"; | |
| reg = <0xa90000 0x4000>; | |
| phandle = <0x5bb>; | |
| dmas = <0x2a4 0x00 0x04 0x01 0x40 0x00 0x2a4 0x01 0x04 0x01 0x40 0x00>; | |
| }; | |
| i2c@99c000 { | |
| pinctrl-names = "default\0sleep"; | |
| #address-cells = <0x01>; | |
| pinctrl-0 = <0x28f>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| interrupts = <0x00 0x260 0x04>; | |
| clocks = <0x16 0x66 0x16 0x84 0x16 0x85>; | |
| #size-cells = <0x00>; | |
| qcom,wrapper-core = <0x274>; | |
| dma-names = "tx\0rx"; | |
| compatible = "qcom,i2c-geni"; | |
| pinctrl-1 = <0x290>; | |
| status = "disabled"; | |
| reg = <0x99c000 0x4000>; | |
| phandle = <0x5a7>; | |
| dmas = <0x280 0x00 0x07 0x03 0x40 0x00 0x280 0x01 0x07 0x03 0x40 0x00>; | |
| }; | |
| qcom,kgsl-3d0@3d00000 { | |
| qcom,bus-accesses-ddr7 = <0x3ca>; | |
| qcom,ubwc-mode = <0x04>; | |
| nvmem-cells = <0x334 0x335>; | |
| vddcx-supply = <0x17c>; | |
| clock-names = "rbbmtimer_clk\0mem_clk\0mem_iface_clk\0gmu_clk\0gpu_cc_ahb\0l3_vote"; | |
| reg-names = "kgsl_3d0_reg_memory\0cx_dbgc\0rscc\0isense_cntl\0qdss_gfx"; | |
| qcom,id = <0x00>; | |
| qcom,highest-bank-bit = <0x10>; | |
| interrupts = <0x00 0x12c 0x04>; | |
| clocks = <0x6e 0x09 0x16 0x16 0x16 0x26 0x6e 0x03 0x6e 0x00 0x1ae 0x03>; | |
| qcom,chipid = <0x6050002>; | |
| label = "kgsl-3d0"; | |
| qcom,bus-accesses-ddr8 = <0x48a>; | |
| vdd-supply = <0x1af>; | |
| qcom,pm-qos-active-latency = <0x2c>; | |
| compatible = "qcom,kgsl-3d0\0qcom,kgsl-3d"; | |
| status = "ok"; | |
| qcom,gpu-qdss-stm = <0x161c0000 0x40000>; | |
| qcom,bus-control; | |
| interrupt-names = "kgsl_3d0_irq"; | |
| qcom,snapshot-size = <0x200000>; | |
| nvmem-cell-names = "isense_slope\0speed_bin"; | |
| qcom,tzone-name = "gpuss-max-step"; | |
| qcom,isense-clk-on-level = <0x01>; | |
| reg = <0x3d00000 0x40000 0x3d61000 0x800 0x3de0000 0x10000 0x3d8b000 0x2000 0x6900000 0x80000>; | |
| regulator-names = "vddcx\0vdd"; | |
| phandle = <0x1c>; | |
| operating-points-v2 = <0x332>; | |
| qcom,no-nap; | |
| qcom,idle-timeout = <0x50>; | |
| qcom,gpubw-dev = <0x333>; | |
| qcom,min-access-length = <0x20>; | |
| #cooling-cells = <0x02>; | |
| qcom,gpu-mempools { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,gpu-mempools"; | |
| qcom,gpu-mempool@2 { | |
| reg = <0x02>; | |
| qcom,mempool-reserved = <0x100>; | |
| qcom,mempool-page-size = <0x10000>; | |
| }; | |
| qcom,gpu-mempool@0 { | |
| qcom,mempool-allocate; | |
| reg = <0x00>; | |
| qcom,mempool-reserved = <0x800>; | |
| qcom,mempool-page-size = <0x1000>; | |
| }; | |
| qcom,gpu-mempool@3 { | |
| reg = <0x03>; | |
| qcom,mempool-reserved = <0x20>; | |
| qcom,mempool-page-size = <0x100000>; | |
| }; | |
| qcom,gpu-mempool@1 { | |
| qcom,mempool-allocate; | |
| reg = <0x01>; | |
| qcom,mempool-reserved = <0x400>; | |
| qcom,mempool-page-size = <0x2000>; | |
| }; | |
| }; | |
| qcom,l3-pwrlevels { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,l3-pwrlevels"; | |
| qcom,l3-pwrlevel@1 { | |
| reg = <0x01>; | |
| qcom,l3-freq = <0x337f9800>; | |
| }; | |
| qcom,l3-pwrlevel@2 { | |
| reg = <0x02>; | |
| qcom,l3-freq = <0x501bd000>; | |
| }; | |
| qcom,l3-pwrlevel@0 { | |
| reg = <0x00>; | |
| qcom,l3-freq = <0x00>; | |
| }; | |
| }; | |
| qcom,gpu-bus-table-1 { | |
| qcom,msm-bus,name = "grp3d"; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x0c>; | |
| compatible = "qcom,gpu-bus-table\0qcom,gpu-bus-table-ddr8"; | |
| qcom,msm-bus,vectors-KBps = <0x1a 0x200 0x00 0x00 0x1a 0x200 0x00 0xbebc2 0x1a 0x200 0x00 0x11e1a3 0x1a 0x200 0x00 0x1ae1b6 0x1a 0x200 0x00 0x209a8e 0x1a 0x200 0x00 0x28973c 0x1a 0x200 0x00 0x2dc6c0 0x1a 0x200 0x00 0x3c9e30 0x1a 0x200 0x00 0x5caf6a 0x1a 0x200 0x00 0x6b86db 0x1a 0x200 0x00 0x7cb163 0x1a 0x200 0x00 0xa3140c>; | |
| }; | |
| qcom,gpu-pwrlevel-bins { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,gpu-pwrlevel-bins"; | |
| qcom,gpu-pwrlevels-2 { | |
| #address-cells = <0x01>; | |
| qcom,initial-pwrlevel = <0x04>; | |
| #size-cells = <0x00>; | |
| qcom,speed-bin = <0x03>; | |
| qcom,gpu-pwrlevel@1 { | |
| qcom,bus-max-ddr7 = <0x09>; | |
| qcom,bus-min-ddr8 = <0x07>; | |
| qcom,bus-freq-ddr8 = <0x08>; | |
| qcom,bus-max-ddr8 = <0x09>; | |
| qcom,bus-min-ddr7 = <0x06>; | |
| qcom,acd-level = <0xa02b5ffd>; | |
| qcom,gpu-freq = <0x1d34ce80>; | |
| reg = <0x01>; | |
| qcom,bus-freq-ddr7 = <0x09>; | |
| }; | |
| qcom,gpu-pwrlevel@4 { | |
| qcom,bus-max-ddr7 = <0x09>; | |
| qcom,bus-min-ddr8 = <0x02>; | |
| qcom,bus-freq-ddr8 = <0x03>; | |
| qcom,bus-max-ddr8 = <0x09>; | |
| qcom,bus-min-ddr7 = <0x02>; | |
| qcom,acd-level = <0xa02b5ffd>; | |
| qcom,gpu-freq = <0x122dee40>; | |
| reg = <0x04>; | |
| qcom,bus-freq-ddr7 = <0x03>; | |
| }; | |
| qcom,gpu-pwrlevel@2 { | |
| qcom,bus-max-ddr7 = <0x09>; | |
| qcom,bus-min-ddr8 = <0x07>; | |
| qcom,bus-freq-ddr8 = <0x08>; | |
| qcom,bus-max-ddr8 = <0x09>; | |
| qcom,bus-min-ddr7 = <0x06>; | |
| qcom,acd-level = <0xa02b5ffd>; | |
| qcom,gpu-freq = <0x1a524800>; | |
| reg = <0x02>; | |
| qcom,bus-freq-ddr7 = <0x09>; | |
| }; | |
| qcom,gpu-pwrlevel@0 { | |
| qcom,bus-max-ddr7 = <0x0b>; | |
| qcom,bus-min-ddr8 = <0x0a>; | |
| qcom,bus-freq-ddr8 = <0x0b>; | |
| qcom,bus-max-ddr8 = <0x0b>; | |
| qcom,bus-min-ddr7 = <0x0a>; | |
| qcom,acd-level = <0x802b5ffd>; | |
| qcom,gpu-freq = <0x1f4add40>; | |
| reg = <0x00>; | |
| qcom,bus-freq-ddr7 = <0x0b>; | |
| }; | |
| qcom,gpu-pwrlevel@5 { | |
| qcom,bus-min = <0x00>; | |
| qcom,bus-freq = <0x00>; | |
| qcom,bus-max = <0x00>; | |
| qcom,gpu-freq = <0x00>; | |
| reg = <0x05>; | |
| }; | |
| qcom,gpu-pwrlevel@3 { | |
| qcom,bus-max-ddr7 = <0x09>; | |
| qcom,bus-min-ddr8 = <0x06>; | |
| qcom,bus-freq-ddr8 = <0x08>; | |
| qcom,bus-max-ddr8 = <0x09>; | |
| qcom,bus-min-ddr7 = <0x06>; | |
| qcom,acd-level = <0xa02b5ffd>; | |
| qcom,gpu-freq = <0x17d78400>; | |
| reg = <0x03>; | |
| qcom,bus-freq-ddr7 = <0x07>; | |
| }; | |
| }; | |
| qcom,gpu-pwrlevels-0 { | |
| qcom,throttle-pwrlevel = <0x00>; | |
| #address-cells = <0x01>; | |
| qcom,initial-pwrlevel = <0x05>; | |
| #size-cells = <0x00>; | |
| qcom,speed-bin = <0x00>; | |
| qcom,gpu-pwrlevel@1 { | |
| qcom,bus-max-ddr7 = <0x0b>; | |
| qcom,bus-min-ddr8 = <0x08>; | |
| qcom,bus-freq-ddr8 = <0x08>; | |
| qcom,bus-max-ddr8 = <0x0b>; | |
| qcom,bus-min-ddr7 = <0x09>; | |
| qcom,acd-level = <0x802b5ffd>; | |
| qcom,gpu-freq = <0x1f4add40>; | |
| reg = <0x01>; | |
| qcom,bus-freq-ddr7 = <0x09>; | |
| }; | |
| qcom,gpu-pwrlevel@6 { | |
| qcom,bus-min = <0x00>; | |
| qcom,bus-freq = <0x00>; | |
| qcom,bus-max = <0x00>; | |
| qcom,gpu-freq = <0x00>; | |
| reg = <0x06>; | |
| }; | |
| qcom,gpu-pwrlevel@4 { | |
| qcom,bus-max-ddr7 = <0x09>; | |
| qcom,bus-min-ddr8 = <0x06>; | |
| qcom,bus-freq-ddr8 = <0x08>; | |
| qcom,bus-max-ddr8 = <0x09>; | |
| qcom,bus-min-ddr7 = <0x06>; | |
| qcom,acd-level = <0xa02b5ffd>; | |
| qcom,gpu-freq = <0x17d78400>; | |
| reg = <0x04>; | |
| qcom,bus-freq-ddr7 = <0x07>; | |
| }; | |
| qcom,gpu-pwrlevel@2 { | |
| qcom,bus-max-ddr7 = <0x09>; | |
| qcom,bus-min-ddr8 = <0x07>; | |
| qcom,bus-freq-ddr8 = <0x08>; | |
| qcom,bus-max-ddr8 = <0x09>; | |
| qcom,bus-min-ddr7 = <0x06>; | |
| qcom,acd-level = <0xa02b5ffd>; | |
| qcom,gpu-freq = <0x1d34ce80>; | |
| reg = <0x02>; | |
| qcom,bus-freq-ddr7 = <0x09>; | |
| }; | |
| qcom,gpu-pwrlevel@0 { | |
| qcom,bus-max-ddr7 = <0x0b>; | |
| qcom,bus-min-ddr8 = <0x0b>; | |
| qcom,bus-freq-ddr8 = <0x0b>; | |
| qcom,bus-max-ddr8 = <0x0b>; | |
| qcom,bus-min-ddr7 = <0x0b>; | |
| qcom,acd-level = <0x802b5ffd>; | |
| qcom,gpu-freq = <0x22fce8c0>; | |
| reg = <0x00>; | |
| qcom,bus-freq-ddr7 = <0x0b>; | |
| }; | |
| qcom,gpu-pwrlevel@5 { | |
| qcom,bus-max-ddr7 = <0x09>; | |
| qcom,bus-min-ddr8 = <0x02>; | |
| qcom,bus-freq-ddr8 = <0x03>; | |
| qcom,bus-max-ddr8 = <0x09>; | |
| qcom,bus-min-ddr7 = <0x02>; | |
| qcom,acd-level = <0xa02b5ffd>; | |
| qcom,gpu-freq = <0x122dee40>; | |
| reg = <0x05>; | |
| qcom,bus-freq-ddr7 = <0x03>; | |
| }; | |
| qcom,gpu-pwrlevel@3 { | |
| qcom,bus-max-ddr7 = <0x09>; | |
| qcom,bus-min-ddr8 = <0x07>; | |
| qcom,bus-freq-ddr8 = <0x08>; | |
| qcom,bus-max-ddr8 = <0x09>; | |
| qcom,bus-min-ddr7 = <0x06>; | |
| qcom,acd-level = <0xa02b5ffd>; | |
| qcom,gpu-freq = <0x1a524800>; | |
| reg = <0x03>; | |
| qcom,bus-freq-ddr7 = <0x09>; | |
| }; | |
| }; | |
| qcom,gpu-pwrlevels-3 { | |
| qcom,throttle-pwrlevel = <0x01>; | |
| #address-cells = <0x01>; | |
| qcom,initial-pwrlevel = <0x06>; | |
| #size-cells = <0x00>; | |
| qcom,speed-bin = <0x02>; | |
| qcom,gpu-pwrlevel@1 { | |
| qcom,bus-max-ddr7 = <0x0b>; | |
| qcom,bus-min-ddr8 = <0x0b>; | |
| qcom,bus-freq-ddr8 = <0x0b>; | |
| qcom,bus-max-ddr8 = <0x0b>; | |
| qcom,bus-min-ddr7 = <0x0b>; | |
| qcom,acd-level = <0x802b5ffd>; | |
| qcom,gpu-freq = <0x22fce8c0>; | |
| reg = <0x01>; | |
| qcom,bus-freq-ddr7 = <0x0b>; | |
| }; | |
| qcom,gpu-pwrlevel@6 { | |
| qcom,bus-max-ddr7 = <0x09>; | |
| qcom,bus-min-ddr8 = <0x02>; | |
| qcom,bus-freq-ddr8 = <0x03>; | |
| qcom,bus-max-ddr8 = <0x09>; | |
| qcom,bus-min-ddr7 = <0x02>; | |
| qcom,acd-level = <0xa02b5ffd>; | |
| qcom,gpu-freq = <0x122dee40>; | |
| reg = <0x06>; | |
| qcom,bus-freq-ddr7 = <0x03>; | |
| }; | |
| qcom,gpu-pwrlevel@4 { | |
| qcom,bus-max-ddr7 = <0x09>; | |
| qcom,bus-min-ddr8 = <0x07>; | |
| qcom,bus-freq-ddr8 = <0x08>; | |
| qcom,bus-max-ddr8 = <0x09>; | |
| qcom,bus-min-ddr7 = <0x06>; | |
| qcom,acd-level = <0xa02b5ffd>; | |
| qcom,gpu-freq = <0x1a524800>; | |
| reg = <0x04>; | |
| qcom,bus-freq-ddr7 = <0x09>; | |
| }; | |
| qcom,gpu-pwrlevel@2 { | |
| qcom,bus-max-ddr7 = <0x0b>; | |
| qcom,bus-min-ddr8 = <0x08>; | |
| qcom,bus-freq-ddr8 = <0x08>; | |
| qcom,bus-max-ddr8 = <0x0b>; | |
| qcom,bus-min-ddr7 = <0x09>; | |
| qcom,acd-level = <0x802b5ffd>; | |
| qcom,gpu-freq = <0x1f4add40>; | |
| reg = <0x02>; | |
| qcom,bus-freq-ddr7 = <0x09>; | |
| }; | |
| qcom,gpu-pwrlevel@0 { | |
| qcom,bus-max-ddr7 = <0x0b>; | |
| qcom,bus-min-ddr8 = <0x0b>; | |
| qcom,bus-freq-ddr8 = <0x0b>; | |
| qcom,bus-max-ddr8 = <0x0b>; | |
| qcom,bus-min-ddr7 = <0x0b>; | |
| qcom,acd-level = <0x802b5ffd>; | |
| qcom,gpu-freq = <0x27ef6380>; | |
| reg = <0x00>; | |
| qcom,bus-freq-ddr7 = <0x0b>; | |
| }; | |
| qcom,gpu-pwrlevel@7 { | |
| qcom,bus-min = <0x00>; | |
| qcom,bus-freq = <0x00>; | |
| qcom,bus-max = <0x00>; | |
| qcom,gpu-freq = <0x00>; | |
| reg = <0x07>; | |
| }; | |
| qcom,gpu-pwrlevel@5 { | |
| qcom,bus-max-ddr7 = <0x09>; | |
| qcom,bus-min-ddr8 = <0x06>; | |
| qcom,bus-freq-ddr8 = <0x08>; | |
| qcom,bus-max-ddr8 = <0x09>; | |
| qcom,bus-min-ddr7 = <0x06>; | |
| qcom,acd-level = <0xa02b5ffd>; | |
| qcom,gpu-freq = <0x17d78400>; | |
| reg = <0x05>; | |
| qcom,bus-freq-ddr7 = <0x07>; | |
| }; | |
| qcom,gpu-pwrlevel@3 { | |
| qcom,bus-max-ddr7 = <0x09>; | |
| qcom,bus-min-ddr8 = <0x07>; | |
| qcom,bus-freq-ddr8 = <0x08>; | |
| qcom,bus-max-ddr8 = <0x09>; | |
| qcom,bus-min-ddr7 = <0x06>; | |
| qcom,acd-level = <0xa02b5ffd>; | |
| qcom,gpu-freq = <0x1d34ce80>; | |
| reg = <0x03>; | |
| qcom,bus-freq-ddr7 = <0x09>; | |
| }; | |
| }; | |
| qcom,gpu-pwrlevels-1 { | |
| qcom,throttle-pwrlevel = <0x01>; | |
| #address-cells = <0x01>; | |
| qcom,initial-pwrlevel = <0x06>; | |
| #size-cells = <0x00>; | |
| qcom,speed-bin = <0x01>; | |
| qcom,gpu-pwrlevel@1 { | |
| qcom,bus-max-ddr7 = <0x0b>; | |
| qcom,bus-min-ddr8 = <0x0b>; | |
| qcom,bus-freq-ddr8 = <0x0b>; | |
| qcom,bus-max-ddr8 = <0x0b>; | |
| qcom,bus-min-ddr7 = <0x0b>; | |
| qcom,acd-level = <0x802b5ffd>; | |
| qcom,gpu-freq = <0x22fce8c0>; | |
| reg = <0x01>; | |
| qcom,bus-freq-ddr7 = <0x0b>; | |
| }; | |
| qcom,gpu-pwrlevel@6 { | |
| qcom,bus-max-ddr7 = <0x09>; | |
| qcom,bus-min-ddr8 = <0x02>; | |
| qcom,bus-freq-ddr8 = <0x03>; | |
| qcom,bus-max-ddr8 = <0x09>; | |
| qcom,bus-min-ddr7 = <0x02>; | |
| qcom,acd-level = <0xa02b5ffd>; | |
| qcom,gpu-freq = <0x122dee40>; | |
| reg = <0x06>; | |
| qcom,bus-freq-ddr7 = <0x03>; | |
| }; | |
| qcom,gpu-pwrlevel@4 { | |
| qcom,bus-max-ddr7 = <0x09>; | |
| qcom,bus-min-ddr8 = <0x07>; | |
| qcom,bus-freq-ddr8 = <0x08>; | |
| qcom,bus-max-ddr8 = <0x09>; | |
| qcom,bus-min-ddr7 = <0x06>; | |
| qcom,acd-level = <0xa02b5ffd>; | |
| qcom,gpu-freq = <0x1a524800>; | |
| reg = <0x04>; | |
| qcom,bus-freq-ddr7 = <0x09>; | |
| }; | |
| qcom,gpu-pwrlevel@2 { | |
| qcom,bus-max-ddr7 = <0x0b>; | |
| qcom,bus-min-ddr8 = <0x08>; | |
| qcom,bus-freq-ddr8 = <0x08>; | |
| qcom,bus-max-ddr8 = <0x0b>; | |
| qcom,bus-min-ddr7 = <0x09>; | |
| qcom,acd-level = <0x802b5ffd>; | |
| qcom,gpu-freq = <0x1f4add40>; | |
| reg = <0x02>; | |
| qcom,bus-freq-ddr7 = <0x09>; | |
| }; | |
| qcom,gpu-pwrlevel@0 { | |
| qcom,bus-max-ddr7 = <0x0b>; | |
| qcom,bus-min-ddr8 = <0x0b>; | |
| qcom,bus-freq-ddr8 = <0x0b>; | |
| qcom,bus-max-ddr8 = <0x0b>; | |
| qcom,bus-min-ddr7 = <0x0b>; | |
| qcom,acd-level = <0x802b5ffd>; | |
| qcom,gpu-freq = <0x27ef6380>; | |
| reg = <0x00>; | |
| qcom,bus-freq-ddr7 = <0x0b>; | |
| }; | |
| qcom,gpu-pwrlevel@7 { | |
| qcom,bus-min = <0x00>; | |
| qcom,bus-freq = <0x00>; | |
| qcom,bus-max = <0x00>; | |
| qcom,gpu-freq = <0x00>; | |
| reg = <0x07>; | |
| }; | |
| qcom,gpu-pwrlevel@5 { | |
| qcom,bus-max-ddr7 = <0x09>; | |
| qcom,bus-min-ddr8 = <0x06>; | |
| qcom,bus-freq-ddr8 = <0x08>; | |
| qcom,bus-max-ddr8 = <0x09>; | |
| qcom,bus-min-ddr7 = <0x06>; | |
| qcom,acd-level = <0xa02b5ffd>; | |
| qcom,gpu-freq = <0x17d78400>; | |
| reg = <0x05>; | |
| qcom,bus-freq-ddr7 = <0x07>; | |
| }; | |
| qcom,gpu-pwrlevel@3 { | |
| qcom,bus-max-ddr7 = <0x09>; | |
| qcom,bus-min-ddr8 = <0x07>; | |
| qcom,bus-freq-ddr8 = <0x08>; | |
| qcom,bus-max-ddr8 = <0x09>; | |
| qcom,bus-min-ddr7 = <0x06>; | |
| qcom,acd-level = <0xa02b5ffd>; | |
| qcom,gpu-freq = <0x1d34ce80>; | |
| reg = <0x03>; | |
| qcom,bus-freq-ddr7 = <0x09>; | |
| }; | |
| }; | |
| }; | |
| qcom,gpu-bus-table-0 { | |
| qcom,msm-bus,name = "grp3d"; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x0c>; | |
| compatible = "qcom,gpu-bus-table\0qcom,gpu-bus-table-ddr7"; | |
| qcom,msm-bus,vectors-KBps = <0x1a 0x200 0x00 0x00 0x1a 0x200 0x00 0xbebc2 0x1a 0x200 0x00 0x11e1a3 0x1a 0x200 0x00 0x1ae1b6 0x1a 0x200 0x00 0x209a8e 0x1a 0x200 0x00 0x28973c 0x1a 0x200 0x00 0x2dc6c0 0x1a 0x200 0x00 0x3c9e30 0x1a 0x200 0x00 0x50a524 0x1a 0x200 0x00 0x5caf6a 0x1a 0x200 0x00 0x6b86db 0x1a 0x200 0x00 0x7cb163>; | |
| }; | |
| }; | |
| qcom,pcie@1c08000 { | |
| pinctrl-names = "default"; | |
| qcom,vreg-0p9-voltage-level = <0xd6d80 0xd6d80 0x181f0>; | |
| #address-cells = <0x03>; | |
| dma-coherent; | |
| pinctrl-0 = <0x16f 0x170 0x171>; | |
| clock-names = "pcie_1_pipe_clk\0pcie_1_ref_clk_src\0pcie_1_aux_clk\0pcie_1_cfg_ahb_clk\0pcie_1_mstr_axi_clk\0pcie_1_slv_axi_clk\0pcie_1_ldo\0pcie_1_slv_q2a_axi_clk\0pcie_tbu_clk\0pcie_phy_refgen_clk\0pcie_ddrss_sf_tbu_clk"; | |
| reg-names = "parf\0phy\0dm_core\0elbi\0iatu\0conf"; | |
| qcom,phy-power-down-offset = <0xa40>; | |
| qcom,msm-bus,name = "pcie1"; | |
| qcom,pcie-phy-ver = <0x44e>; | |
| cell-index = <0x01>; | |
| resets = <0x16 0x09 0x16 0x0c>; | |
| qcom,bw-scale = <0x40 0x124f800 0x40 0x124f800 0x100 0x5f5e100>; | |
| interrupts = <0x00 0x01 0x02 0x03 0x04>; | |
| clocks = <0x16 0x3d 0x15 0x00 0x16 0x39 0x16 0x3b 0x16 0x3c 0x16 0x3e 0x16 0x4b 0x16 0x3f 0x16 0x03 0x16 0x30 0x16 0x17>; | |
| qcom,smmu-sid-base = <0x1c80>; | |
| interrupt-map = <0x00 0x00 0x00 0x00 0x01 0x00 0x132 0x04 0x00 0x00 0x00 0x01 0x01 0x00 0x1b2 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0x1b3 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x1b6 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0x1b7 0x04>; | |
| max-clock-frequency-hz = <0x00 0x00 0x124f800 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x5f5e100 0x00>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| #size-cells = <0x02>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| qcom,boot-option = <0x01>; | |
| interrupt-parent = <0xad>; | |
| qcom,vreg-1p8-voltage-level = <0x124f80 0x124f80 0x61a8>; | |
| qcom,phy-status-offset = <0xa14>; | |
| interrupt-map-mask = <0x00 0x00 0x00 0xffffffff>; | |
| wake-gpio = <0x66 0x54 0x00>; | |
| vreg-0p9-supply = <0x7c>; | |
| qcom,drv-supported; | |
| compatible = "qcom,pci-msm"; | |
| ranges = <0x1000000 0x00 0x40200000 0x40200000 0x00 0x100000 0x2000000 0x00 0x40300000 0x40300000 0x00 0x1fd00000>; | |
| #interrupt-cells = <0x01>; | |
| interrupt-names = "int_global_int\0int_a\0int_b\0int_c\0int_d"; | |
| vreg-1p8-supply = <0x7d>; | |
| reg = <0x1c08000 0x3000 0x1c0e000 0x2000 0x40000000 0xf1d 0x40000f20 0xa8 0x40001000 0x1000 0x40100000 0x100000>; | |
| linux,pci-domain = <0x01>; | |
| phandle = <0xad>; | |
| qcom,msm-bus,vectors-KBps = <0x64 0x200 0x00 0x00 0x64 0x200 0x1f4 0x320>; | |
| gdsc-vdd-supply = <0x172>; | |
| iommu-map = <0x00 0x47 0x1c80 0x01 0x100 0x47 0x1c81 0x01>; | |
| msi-parent = <0x16e>; | |
| qcom,no-l0s-supported; | |
| reset-names = "pcie_1_core_reset\0pcie_1_phy_reset"; | |
| qcom,ep-latency = <0x0a>; | |
| vreg-cx-supply = <0x67>; | |
| qcom,use-19p2mhz-aux-clk; | |
| perst-gpio = <0x66 0x52 0x00>; | |
| qcom,vreg-cx-voltage-level = <0xffff 0x100 0x00>; | |
| qcom,phy-status-bit = <0x06>; | |
| qcom,slv-addr-space-size = <0x20000000>; | |
| qcom,phy-sequence = <0xa40 0x03 0x00 0x10 0x01 0x00 0x1c 0x31 0x00 0x20 0x01 0x00 0x24 0xde 0x00 0x28 0x07 0x00 0x30 0x4c 0x00 0x34 0x06 0x00 0x48 0x90 0x00 0x58 0x0f 0x00 0x74 0x06 0x00 0x78 0x06 0x00 0x7c 0x16 0x00 0x80 0x16 0x00 0x84 0x36 0x00 0x88 0x36 0x00 0x94 0x08 0x00 0xa4 0x42 0x00 0xac 0x0a 0x00 0xb0 0x1a 0x00 0xb4 0x14 0x00 0xb8 0x34 0x00 0xbc 0x82 0x00 0xc4 0x68 0x00 0xcc 0x55 0x00 0xd0 0x55 0x00 0xd4 0x03 0x00 0xd8 0xab 0x00 0xdc 0xaa 0x00 0xe0 0x02 0x00 0x10c 0x02 0x00 0x110 0x24 0x00 0x118 0xb4 0x00 0x11c 0x03 0x00 0x154 0x34 0x00 0x158 0x01 0x00 0x16c 0x08 0x00 0x1ac 0xca 0x00 0x1b0 0x1e 0x00 0x1b4 0xa2 0x00 0x1b8 0x18 0x00 0x1bc 0x11 0x00 0x23c 0x11 0x00 0x284 0x75 0x00 0x29c 0x12 0x00 0x304 0x02 0x00 0x408 0x0c 0x00 0x414 0x03 0x00 0x434 0x7f 0x00 0x444 0x70 0x00 0x460 0x30 0x00 0x4d4 0x04 0x00 0x4d8 0x07 0x00 0x4dc 0x1b 0x00 0x4e8 0x04 0x00 0x4ec 0x0e 0x00 0x4f0 0x4a 0x00 0x4f4 0x0f 0x00 0x4f8 0xc0 0x00 0x4fc 0x00 0x00 0x510 0x17 0x00 0x518 0x1c 0x00 0x51c 0x03 0x00 0x524 0x1e 0x00 0x570 0xbf 0x00 0x574 0x3f 0x00 0x578 0xff 0x00 0x57c 0x7f 0x00 0x580 0x15 0x00 0x584 0x24 0x00 0x588 0xe4 0x00 0x58c 0xec 0x00 0x590 0x3b 0x00 0x594 0x36 0x00 0x598 0xd4 0x00 0x59c 0x54 0x00 0x5a0 0xdb 0x00 0x5a4 0x3b 0x00 0x5a8 0x31 0x00 0x5bc 0x0c 0x00 0x5b8 0x38 0x00 0x63c 0x11 0x00 0x684 0x75 0x00 0x69c 0x12 0x00 0x704 0x20 0x00 0x808 0x0c 0x00 0x814 0x03 0x00 0x834 0x7f 0x00 0x844 0x70 0x00 0x860 0x30 0x00 0x8d4 0x04 0x00 0x8d8 0x07 0x00 0x8dc 0x1b 0x00 0x8e8 0x04 0x00 0x8ec 0x0e 0x00 0x8f0 0x4a 0x00 0x8f4 0x0f 0x00 0x8f8 0xc0 0x00 0x8fc 0x00 0x00 0x910 0x17 0x00 0x918 0x1c 0x00 0x91c 0x03 0x00 0x924 0x1e 0x00 0x970 0xbf 0x00 0x974 0x3f 0x00 0x978 0xff 0x00 0x97c 0x7f 0x00 0x980 0x15 0x00 0x984 0x24 0x00 0x988 0xe4 0x00 0x98c 0xec 0x00 0x990 0x3b 0x00 0x994 0x36 0x00 0x998 0xd4 0x00 0x99c 0x54 0x00 0x9a0 0xdb 0x00 0x9a4 0x3b 0x00 0x9a8 0x31 0x00 0x9bc 0x0c 0x00 0x9b8 0x38 0x00 0xadc 0x05 0x00 0xb88 0x77 0x00 0xb98 0x0b 0x00 0xba4 0x01 0x00 0xbe0 0x0f 0x00 0xe0c 0x0d 0x00 0xe14 0x07 0x00 0xe1c 0xc1 0x00 0xe40 0x01 0x00 0xe48 0x01 0x00 0xe90 0x00 0x00 0xeb4 0x33 0x00 0xebc 0x00 0x00 0xee0 0x58 0x00 0xa00 0x00 0x00 0xa44 0x03 0x00>; | |
| pcie1_rp { | |
| #address-cells = <0x05>; | |
| #size-cells = <0x00>; | |
| reg = <0x00 0x00 0x00 0x00 0x00>; | |
| phandle = <0x3db>; | |
| wil6210_pci { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| qcom,iommu-group = <0x89>; | |
| reg = <0x00 0x00 0x00 0x00 0x00>; | |
| phandle = <0x3dc>; | |
| wil6210_pci_iommu_group { | |
| qcom,iommu-dma-addr-pool = <0x60000000 0xa0000000>; | |
| reg = <0x00 0x00>; | |
| phandle = <0x89>; | |
| qcom,iommu-pagetable = "coherent"; | |
| qcom,iommu-dma = "fastmap"; | |
| }; | |
| }; | |
| }; | |
| }; | |
| mailbox@188501c { | |
| #mbox-cells = <0x01>; | |
| compatible = "qcom,kona-spcs-global"; | |
| reg = <0x188501c 0x04>; | |
| phandle = <0x90>; | |
| }; | |
| audio_etm0 { | |
| qcom,inst-id = <0x05>; | |
| coresight-name = "coresight-audio-etm0"; | |
| compatible = "qcom,coresight-remote-etm"; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x235>; | |
| phandle = <0x198>; | |
| }; | |
| }; | |
| }; | |
| funnel@6846000 { | |
| arm,primecell-periphid = <0xbb908>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "funnel-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-funnel-lpass"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6846000 0x1000>; | |
| phandle = <0x4f1>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x1cc>; | |
| phandle = <0x200>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x00>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x1cd>; | |
| phandle = <0x1ce>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,cpas-cdm1@acb4200 { | |
| camss-supply = <0x253>; | |
| clock-names = "cam_cc_cpas_slow_ahb_clk\0cam_cc_cpas_ahb_clk"; | |
| reg-names = "cpas-cdm"; | |
| reg-cam-base = "\0\vB"; | |
| cdm-client-names = "ife0"; | |
| cell-index = <0x01>; | |
| interrupts = <0x00 0x1c8 0x01>; | |
| clocks = <0x6d 0x6d 0x6d 0x0d>; | |
| label = "cpas-cdm"; | |
| clock-cntl-level = "svs"; | |
| compatible = "qcom,cam480-cpas-cdm1"; | |
| status = "disabled"; | |
| interrupt-names = "cpas-cdm"; | |
| reg = <0xacb4200 0x1000>; | |
| regulator-names = "camss"; | |
| clock-rates = <0x00 0x00>; | |
| }; | |
| spi@998000 { | |
| pinctrl-names = "default\0sleep"; | |
| #address-cells = <0x01>; | |
| pinctrl-0 = <0x29d>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| reg-names = "se_phys"; | |
| interrupts = <0x00 0x25f 0x04>; | |
| clocks = <0x16 0x64 0x16 0x84 0x16 0x85>; | |
| #size-cells = <0x00>; | |
| qcom,wrapper-core = <0x274>; | |
| spi-max-frequency = <0x2faf080>; | |
| dma-names = "tx\0rx"; | |
| compatible = "qcom,spi-geni"; | |
| pinctrl-1 = <0x29e>; | |
| status = "disabled"; | |
| reg = <0x998000 0x4000>; | |
| phandle = <0x5ae>; | |
| dmas = <0x280 0x00 0x06 0x01 0x40 0x00 0x280 0x01 0x06 0x01 0x40 0x00>; | |
| }; | |
| i2c@a8c000 { | |
| pinctrl-names = "default\0sleep"; | |
| #address-cells = <0x01>; | |
| pinctrl-0 = <0x2ab>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| interrupts = <0x00 0x164 0x04>; | |
| clocks = <0x16 0x70 0x16 0x86 0x16 0x87>; | |
| #size-cells = <0x00>; | |
| qcom,wrapper-core = <0x2a3>; | |
| dma-names = "tx\0rx"; | |
| compatible = "qcom,i2c-geni"; | |
| pinctrl-1 = <0x2ac>; | |
| status = "disabled"; | |
| reg = <0xa8c000 0x4000>; | |
| phandle = <0x5b4>; | |
| dmas = <0x2a4 0x00 0x03 0x03 0x40 0x00 0x2a4 0x01 0x03 0x03 0x40 0x00>; | |
| }; | |
| tpdm@6b26000 { | |
| qcom,dummy-source; | |
| coresight-name = "coresight-tpdm-lpass-lpi"; | |
| compatible = "qcom,coresight-dummy"; | |
| phandle = <0x4f3>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x1d0>; | |
| phandle = <0x19b>; | |
| }; | |
| }; | |
| }; | |
| qcom,ipe0 { | |
| ipe0-vdd-supply = <0x26f>; | |
| clock-control-debugfs = "true"; | |
| clock-names = "ipe_0_ahb_clk\0ipe_0_areg_clk\0ipe_0_axi_clk\0ipe_0_clk_src\0ipe_0_clk"; | |
| reg-names = "ipe0_top"; | |
| reg-cam-base = <0x9a000>; | |
| cell-index = <0x00>; | |
| clocks = <0x6d 0x42 0x6d 0x43 0x6d 0x44 0x6d 0x46 0x6d 0x45>; | |
| clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; | |
| compatible = "qcom,cam-ipe"; | |
| src-clock-name = "ipe_0_clk_src"; | |
| status = "ok"; | |
| reg = <0xac9a000 0xc000>; | |
| regulator-names = "ipe0-vdd"; | |
| phandle = <0x597>; | |
| clock-rates = <0x00 0x00 0x00 0x11e1a300 0x00 0x00 0x00 0x00 0x1c4fecc0 0x00 0x00 0x00 0x00 0x1f4add40 0x00 0x00 0x00 0x00 0x29b92700 0x00 0x00 0x00 0x00 0x29b92700 0x00>; | |
| }; | |
| qcom,jpegenc@ac53000 { | |
| clock-names = "jpegenc_clk_src\0jpegenc_clk"; | |
| reg-names = "jpege_hw"; | |
| reg-cam-base = <0x53000>; | |
| cell-index = <0x00>; | |
| camss-vdd-supply = <0x253>; | |
| interrupts = <0x00 0x1da 0x01>; | |
| clocks = <0x6d 0x48 0x6d 0x47>; | |
| clock-cntl-level = "nominal"; | |
| compatible = "qcom,cam_jpeg_enc"; | |
| src-clock-name = "jpegenc_clk_src"; | |
| status = "ok"; | |
| interrupt-names = "jpeg"; | |
| reg = <0xac53000 0x4000>; | |
| regulator-names = "camss-vdd"; | |
| phandle = <0x599>; | |
| clock-rates = <0x23c34600 0x00>; | |
| }; | |
| dsu_pmu@0 { | |
| interrupts = <0x00 0x32 0x04>; | |
| compatible = "arm,dsu-pmu"; | |
| cpus = <0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14>; | |
| }; | |
| qcom,cpu0-llcc-ddr-lat { | |
| qcom,src-dst-ports = <0x81 0x200>; | |
| governor = "performance"; | |
| compatible = "qcom,devbw-ddr"; | |
| phandle = <0x59>; | |
| qcom,active-only; | |
| operating-points-v2 = <0x4d>; | |
| }; | |
| spi@a88000 { | |
| pinctrl-names = "default\0sleep"; | |
| #address-cells = <0x01>; | |
| pinctrl-0 = <0x2b4>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| reg-names = "se_phys"; | |
| interrupts = <0x00 0x163 0x04>; | |
| clocks = <0x16 0x6e 0x16 0x86 0x16 0x87>; | |
| #size-cells = <0x00>; | |
| qcom,wrapper-core = <0x2a3>; | |
| spi-max-frequency = <0x2faf080>; | |
| dma-names = "tx\0rx"; | |
| compatible = "qcom,spi-geni"; | |
| pinctrl-1 = <0x2b5>; | |
| status = "disabled"; | |
| reg = <0xa88000 0x4000>; | |
| phandle = <0x5b9>; | |
| dmas = <0x2a4 0x00 0x02 0x01 0x40 0x00 0x2a4 0x01 0x02 0x01 0x40 0x00>; | |
| }; | |
| timer { | |
| interrupts = <0x01 0x0d 0xff08 0x01 0x0e 0xff08 0x01 0x0b 0xff08 0x01 0x0c 0xff08>; | |
| clock-frequency = <0x124f800>; | |
| compatible = "arm,armv8-timer"; | |
| phandle = <0x34e>; | |
| }; | |
| replicator@6b06000 { | |
| arm,primecell-periphid = <0xbb909>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "replicator-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-replicator-swao"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6b06000 0x1000>; | |
| phandle = <0x4de>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0x18d>; | |
| phandle = <0x190>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x18e>; | |
| phandle = <0x18c>; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x00>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x18f>; | |
| phandle = <0x194>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,smp2p-cdsp { | |
| qcom,local-pid = <0x00>; | |
| interrupts = <0x06 0x02 0x01>; | |
| interrupt-parent = <0x8a>; | |
| qcom,remote-pid = <0x05>; | |
| compatible = "qcom,smp2p"; | |
| mboxes = <0x8a 0x06 0x02>; | |
| qcom,smem = <0x5e 0x1b0>; | |
| qcom,smp2p-rdbg5-out { | |
| qcom,entry-name = "rdbg"; | |
| #qcom,smem-state-cells = <0x01>; | |
| phandle = <0x251>; | |
| }; | |
| qcom,smp2p-qvrexternal5-out { | |
| qcom,entry-name = "qvrexternal"; | |
| #qcom,smem-state-cells = <0x01>; | |
| phandle = <0x336>; | |
| }; | |
| slave-kernel { | |
| qcom,entry-name = "slave-kernel"; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x97>; | |
| interrupt-controller; | |
| }; | |
| master-kernel { | |
| qcom,entry-name = "master-kernel"; | |
| #qcom,smem-state-cells = <0x01>; | |
| phandle = <0x98>; | |
| }; | |
| qcom,smp2p-rdbg5-in { | |
| qcom,entry-name = "rdbg"; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x252>; | |
| interrupt-controller; | |
| }; | |
| }; | |
| qcom,ssc@5c00000 { | |
| qcom,smem-state-names = "qcom,force-stop"; | |
| qcom,smem-id = <0x1a8>; | |
| qcom,sysmon-id = <0x03>; | |
| qcom,vdd_mx-uV-uA = <0x180 0x00>; | |
| qcom,ssctl-instance-id = <0x16>; | |
| clock-names = "xo"; | |
| qcom,proxy-timeout-ms = <0x2710>; | |
| memory-region = <0xa2>; | |
| clocks = <0x15 0x00>; | |
| qcom,signal-aop; | |
| qcom,complete-ramdump; | |
| vdd_mx-supply = <0x92>; | |
| qcom,pas-id = <0x0c>; | |
| interrupts-extended = <0x76 0x09 0x04 0xa3 0x00 0x00 0xa3 0x02 0x00 0xa3 0x01 0x00 0xa3 0x03 0x00>; | |
| compatible = "qcom,pil-tz-generic"; | |
| status = "ok"; | |
| qcom,vdd_cx-uV-uA = <0x180 0x00>; | |
| interrupt-names = "qcom,wdog\0qcom,err-fatal\0qcom,proxy-unvote\0qcom,err-ready\0qcom,stop-ack"; | |
| reg = <0x5c00000 0x4000>; | |
| qcom,smem-states = <0xa4 0x00>; | |
| mboxes = <0x02 0x00>; | |
| vdd_cx-supply = <0x91>; | |
| qcom,proxy-clock-names = "xo"; | |
| qcom,proxy-reg-names = "vdd_cx\0vdd_mx"; | |
| qcom,firmware-name = "slpi"; | |
| mbox-names = "slpi-pil"; | |
| }; | |
| qcom,npu-llcc-ddr-bwmon@0x9093000 { | |
| reg-names = "base"; | |
| interrupts = <0x00 0x51 0x04>; | |
| compatible = "qcom,bimc-bwmon5"; | |
| qcom,hw-timer-hz = <0x124f800>; | |
| qcom,count-unit = <0x10000>; | |
| reg = <0x9093000 0x1000>; | |
| phandle = <0x360>; | |
| qcom,target-dev = <0x52>; | |
| }; | |
| dsi_panel_pwr_supply { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| phandle = <0x638>; | |
| qcom,panel-supply-entry@3 { | |
| qcom,supply-disable-load = <0x64>; | |
| qcom,supply-enable-load = <0x186a0>; | |
| qcom,supply-post-on-sleep = <0x14>; | |
| qcom,supply-name = "ibb"; | |
| qcom,supply-max-voltage = <0x5b8d80>; | |
| reg = <0x03>; | |
| qcom,supply-min-voltage = <0x4630c0>; | |
| }; | |
| qcom,panel-supply-entry@1 { | |
| qcom,supply-disable-load = <0x00>; | |
| qcom,supply-enable-load = <0xd13a8>; | |
| qcom,supply-post-on-sleep = <0x00>; | |
| qcom,supply-name = "vdd"; | |
| qcom,supply-max-voltage = <0x325aa0>; | |
| qcom,supply-pre-off-sleep = <0x02>; | |
| qcom,supply-post-off-sleep = <0x03>; | |
| reg = <0x01>; | |
| qcom,supply-min-voltage = <0x325aa0>; | |
| }; | |
| qcom,panel-supply-entry@2 { | |
| qcom,supply-disable-load = <0x64>; | |
| qcom,supply-enable-load = <0x186a0>; | |
| qcom,supply-name = "lab"; | |
| qcom,supply-max-voltage = <0x5b8d80>; | |
| reg = <0x02>; | |
| qcom,supply-min-voltage = <0x4630c0>; | |
| }; | |
| qcom,panel-supply-entry@0 { | |
| qcom,supply-disable-load = <0x50>; | |
| qcom,supply-enable-load = <0x493e0>; | |
| qcom,supply-post-on-sleep = <0x14>; | |
| qcom,supply-name = "vddio"; | |
| qcom,supply-max-voltage = <0x1cafc0>; | |
| qcom,supply-pre-off-sleep = <0x00>; | |
| reg = <0x00>; | |
| qcom,supply-min-voltage = <0x1cafc0>; | |
| }; | |
| }; | |
| cti@7520000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| cpu = <0x12>; | |
| coresight-name = "coresight-cti-cpu5"; | |
| compatible = "arm,primecell"; | |
| reg = <0x7520000 0x1000>; | |
| phandle = <0x52d>; | |
| }; | |
| qcom,fd@ac5f000 { | |
| clock-control-debugfs = "true"; | |
| clock-names = "fd_core_clk_src\0fd_core_clk\0fd_core_uar_clk"; | |
| reg-names = "fd_core\0fd_wrapper"; | |
| reg-cam-base = <0x5f000 0x60000>; | |
| cell-index = <0x00>; | |
| camss-vdd-supply = <0x253>; | |
| interrupts = <0x00 0x1ce 0x01>; | |
| clocks = <0x6d 0x23 0x6d 0x22 0x6d 0x24>; | |
| clock-cntl-level = "svs\0svs_l1\0turbo"; | |
| compatible = "qcom,fd600"; | |
| src-clock-name = "fd_core_clk_src"; | |
| status = "ok"; | |
| interrupt-names = "fd"; | |
| reg = <0xac5f000 0x1000 0xac60000 0x400>; | |
| regulator-names = "camss-vdd"; | |
| phandle = <0x59b>; | |
| clock-rates = <0x17d78400 0x00 0x00 0x1c9c3800 0x00 0x00 0x23c34600 0x00 0x00>; | |
| }; | |
| qcom,gdsc@110004 { | |
| qcom,retain-regs; | |
| regulator-name = "usb30_sec_gdsc"; | |
| compatible = "qcom,gdsc"; | |
| reg = <0x110004 0x04>; | |
| phandle = <0x188>; | |
| }; | |
| tpda@6b08000 { | |
| arm,primecell-periphid = <0xbb969>; | |
| qcom,cmb-elem-size = <0x00 0x40>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpda-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-tpda-swao"; | |
| qcom,dsb-elem-size = <0x01 0x20>; | |
| compatible = "arm,primecell"; | |
| qcom,tpda-atid = <0x47>; | |
| reg = <0x6b08000 0x1000>; | |
| phandle = <0x4e2>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x19c>; | |
| phandle = <0x199>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x00>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x19d>; | |
| phandle = <0x19f>; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x01>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x19e>; | |
| phandle = <0x1a0>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,bus_proxy_client { | |
| qcom,msm-bus,name = "bus-proxy-client"; | |
| qcom,msm-bus,active-only; | |
| qcom,msm-bus,num-paths = <0x02>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| compatible = "qcom,bus-proxy-client"; | |
| status = "ok"; | |
| phandle = <0x35a>; | |
| qcom,msm-bus,vectors-KBps = <0x16 0x200 0x00 0x00 0x17 0x200 0x00 0x00 0x16 0x200 0x16e360 0x16e360 0x17 0x200 0x16e360 0x16e360>; | |
| }; | |
| qcom,ipa@1e00000 { | |
| qcom,use-ipa-tethering-bridge; | |
| qcom,ipa-hw-mode = <0x00>; | |
| qcom,ipa-hw-ver = <0x11>; | |
| qcom,ram-collection-on-crash; | |
| qcom,smmu-fast-map; | |
| reg-names = "ipa-base\0gsi-base"; | |
| qcom,bus-vector-names = "MIN\0SVS2\0SVS\0NOMINAL\0TURBO"; | |
| qcom,msm-bus,name = "ipa"; | |
| qcom,throughput-threshold = <0x258 0x9c4 0x1388>; | |
| interrupts = <0x00 0x137 0x04 0x00 0x1b0 0x04>; | |
| qcom,platform-type = <0x02>; | |
| qcom,non-tn-collection-on-crash; | |
| qcom,msm-bus,num-paths = <0x05>; | |
| qcom,msm-bus,num-cases = <0x05>; | |
| qcom,register-collection-on-crash; | |
| compatible = "qcom,ipa"; | |
| qcom,arm-smmu; | |
| interrupt-names = "ipa-irq\0gsi-irq"; | |
| qcom,mhi-event-ring-id-limits = <0x09 0x0b>; | |
| qcom,use-64-bit-dma-mask; | |
| qcom,bandwidth-vote-for-ipa; | |
| reg = <0x1e00000 0x84000 0x1e04000 0x23000>; | |
| qcom,ipa-wdi3-over-gsi; | |
| phandle = <0x397>; | |
| qcom,msm-bus,vectors-KBps = <0x5a 0x302 0x00 0x00 0x81 0x200 0x00 0x00 0x5a 0x249 0x00 0x00 0x01 0x2a4 0x00 0x00 0x8f 0x309 0x00 0x00 0x5a 0x302 0x249f0 0x927c0 0x81 0x200 0x249f0 0x1b86e0 0x5a 0x249 0x124f8 0x493e0 0x01 0x2a4 0x00 0x12c00 0x8f 0x309 0x00 0x96 0x5a 0x302 0x98968 0x124f80 0x81 0x200 0x98968 0x2ee000 0x5a 0x249 0x4c4b4 0xaae60 0x01 0x2a4 0x00 0x249f0 0x8f 0x309 0x00 0xf0 0x5a 0x302 0x1312d0 0x249f00 0x81 0x200 0x1312d0 0x5eec00 0x5a 0x249 0x98968 0x16e360 0x01 0x2a4 0x00 0x61a80 0x8f 0x309 0x00 0x1d2 0x5a 0x302 0x1e8480 0x3567e0 0x81 0x200 0x1e8480 0x6e2800 0x5a 0x249 0xf4240 0x1d4c00 0x01 0x2a4 0x00 0x61a80 0x8f 0x309 0x00 0x215>; | |
| mboxes = <0x02 0x00>; | |
| qcom,ee = <0x00>; | |
| qcom,testbus-collection-on-crash; | |
| qcom,entire-ipa-block-size = <0x100000>; | |
| qcom,modem-cfg-emb-pipe-flt; | |
| qcom,scaling-exceptions = "wdi\00\0600\01200\0USB DPL\00\02500\05000\0ODL\00\02500\05000"; | |
| qcom,secure-debug-check-action = <0x00>; | |
| qcom,ipa-endp-delay-wa; | |
| ipa_smmu_uc { | |
| iommus = <0x47 0x5c2 0x00>; | |
| compatible = "qcom,ipa-smmu-uc-cb"; | |
| qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>; | |
| phandle = <0x39a>; | |
| qcom,iommu-dma = "fastmap"; | |
| }; | |
| ipa_smmu_ap { | |
| iommus = <0x47 0x5c0 0x00>; | |
| dma-coherent; | |
| qcom,additional-mapping = <0x146bd000 0x146bd000 0x2000>; | |
| compatible = "qcom,ipa-smmu-ap-cb"; | |
| qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>; | |
| phandle = <0x398>; | |
| qcom,iommu-dma = "fastmap"; | |
| }; | |
| ipa_smmu_11ad { | |
| iommus = <0x47 0x5c3 0x00>; | |
| dma-coherent; | |
| qcom,shared-cb; | |
| compatible = "qcom,ipa-smmu-11ad-cb"; | |
| qcom,iommu-group = <0x89>; | |
| phandle = <0x39b>; | |
| }; | |
| ipa_smmu_wlan { | |
| iommus = <0x47 0x5c1 0x00>; | |
| dma-coherent; | |
| compatible = "qcom,ipa-smmu-wlan-cb"; | |
| phandle = <0x399>; | |
| qcom,iommu-dma = "fastmap"; | |
| }; | |
| }; | |
| tpdm@6c47000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| qcom,proxy-regs = "vdd\0vdd_cx"; | |
| clock-names = "apb_pclk\0gcc_npu_axi_clk\0gcc_npu_cfg_ahb_clk\0npu_cc_xo_clk\0npu_core_clk\0npu_core_clk_src\0npu_cc_atb_clk"; | |
| reg-names = "tpdm-base"; | |
| qcom,proxy-clks = "gcc_npu_axi_clk\0gcc_npu_cfg_ahb_clk\0npu_cc_xo_clk\0npu_core_clk\0npu_core_clk_src\0npu_cc_atb_clk"; | |
| clocks = <0x49 0x00 0x16 0x28 0x16 0x2b 0x55 0x28 0x55 0x0d 0x55 0x0e 0x55 0x00>; | |
| coresight-name = "coresight-tpdm-npu"; | |
| vdd-supply = <0x1de>; | |
| compatible = "arm,primecell"; | |
| reg = <0x6c47000 0x1000>; | |
| phandle = <0x1f5>; | |
| vdd_cx-supply = <0x67>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x1df>; | |
| phandle = <0x21b>; | |
| }; | |
| }; | |
| }; | |
| qcom,msm-dai-q6-dp { | |
| compatible = "qcom,msm-dai-q6-hdmi"; | |
| qcom,msm-dai-q6-dev-id = <0x00>; | |
| phandle = <0x2ed>; | |
| }; | |
| syscon@1f40000 { | |
| compatible = "syscon"; | |
| reg = <0x1f40000 0x20000>; | |
| phandle = <0x81>; | |
| }; | |
| cti@6b02000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti-swao_cti2"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6b02000 0x1000>; | |
| phandle = <0x540>; | |
| }; | |
| qcom,snoc_cnoc_keepalive { | |
| qcom,src-dst-ports = <0x01 0x273>; | |
| governor = "powersave"; | |
| compatible = "qcom,devbw"; | |
| status = "ok"; | |
| phandle = <0x35b>; | |
| qcom,active-only; | |
| operating-points-v2 = <0x4a>; | |
| }; | |
| regulator-haptics-boost { | |
| pinctrl-names = "default"; | |
| gpio = <0x626 0x05 0x00>; | |
| pinctrl-0 = <0x636>; | |
| enable-active-high; | |
| regulator-name = "vdd_hap_boost"; | |
| startup-delay-us = <0x3e8>; | |
| compatible = "regulator-fixed"; | |
| status = "ok"; | |
| phandle = <0x62c>; | |
| }; | |
| qcom,rmnet-ipa { | |
| qcom,ipa-napi-enable; | |
| qcom,rmnet-ipa-ssr; | |
| qcom,ipa-advertise-sg-support; | |
| compatible = "qcom,rmnet-ipa3"; | |
| }; | |
| cti@78f0000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti-apss_cti1"; | |
| compatible = "arm,primecell"; | |
| reg = <0x78f0000 0x1000>; | |
| phandle = <0x50a>; | |
| }; | |
| qcom,kgsl-busmon { | |
| label = "kgsl-busmon"; | |
| compatible = "qcom,kgsl-busmon"; | |
| phandle = <0x606>; | |
| operating-points-v2 = <0x332>; | |
| }; | |
| tpdm@6b0a000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-tpdm-swao-1"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6b0a000 0x1000>; | |
| phandle = <0x4e4>; | |
| qcom,msr-fix-req; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x1a0>; | |
| phandle = <0x19e>; | |
| }; | |
| }; | |
| }; | |
| i2c@880000 { | |
| pinctrl-names = "default\0sleep"; | |
| #address-cells = <0x01>; | |
| pinctrl-0 = <0x2c3>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| interrupts = <0x00 0x175 0x04>; | |
| clocks = <0x16 0x78 0x16 0x88 0x16 0x89>; | |
| #size-cells = <0x00>; | |
| qcom,wrapper-core = <0x2bf>; | |
| dma-names = "tx\0rx"; | |
| compatible = "qcom,i2c-geni"; | |
| pinctrl-1 = <0x2c4>; | |
| status = "disabled"; | |
| reg = <0x880000 0x4000>; | |
| phandle = <0x5bf>; | |
| dmas = <0x2c2 0x00 0x00 0x03 0x40 0x00 0x2c2 0x01 0x00 0x03 0x40 0x00>; | |
| }; | |
| qcom,pcie0_msi@17a10040 { | |
| interrupts = <0x00 0x300 0x01 0x00 0x301 0x01 0x00 0x302 0x01 0x00 0x303 0x01 0x00 0x304 0x01 0x00 0x305 0x01 0x00 0x306 0x01 0x00 0x307 0x01 0x00 0x308 0x01 0x00 0x309 0x01 0x00 0x30a 0x01 0x00 0x30b 0x01 0x00 0x30c 0x01 0x00 0x30d 0x01 0x00 0x30e 0x01 0x00 0x30f 0x01 0x00 0x310 0x01 0x00 0x311 0x01 0x00 0x312 0x01 0x00 0x313 0x01 0x00 0x314 0x01 0x00 0x315 0x01 0x00 0x316 0x01 0x00 0x317 0x01 0x00 0x318 0x01 0x00 0x319 0x01 0x00 0x31a 0x01 0x00 0x31b 0x01 0x00 0x31c 0x01 0x00 0x31d 0x01 0x00 0x31e 0x01 0x00 0x31f 0x01>; | |
| interrupt-parent = <0x01>; | |
| msi-controller; | |
| compatible = "qcom,pci-msi"; | |
| reg = <0x17a10040 0x00>; | |
| phandle = <0x166>; | |
| }; | |
| qcom,ife1@acc3000 { | |
| camss-supply = <0x253>; | |
| clock-control-debugfs = "true"; | |
| clock-names = "ife_1_ahb\0ife_1_areg\0ife_clk_src\0ife_clk\0ife_axi_clk"; | |
| clocks-option = <0x6d 0x3a>; | |
| reg-names = "ife\0cam_camnoc"; | |
| clock-rates-option = <0x2aea5400>; | |
| reg-cam-base = <0xc3000 0x42000>; | |
| cell-index = <0x01>; | |
| ife1-supply = <0x26e>; | |
| interrupts = <0x00 0x1d3 0x01>; | |
| clocks = <0x6d 0x32 0x6d 0x33 0x6d 0x36 0x6d 0x35 0x6d 0x34>; | |
| ubwc-static-cfg = <0x1026 0x1036>; | |
| clock-cntl-level = "lowsvs\0svs\0svs_l1\0turbo"; | |
| compatible = "qcom,vfe480"; | |
| src-clock-name = "ife_clk_src"; | |
| status = "ok"; | |
| clock-names-option = "ife_dsp_clk"; | |
| interrupt-names = "ife"; | |
| scl-clk-names = "ife_1_areg"; | |
| reg = <0xacc3000 0xd000 0xac42000 0x8000>; | |
| regulator-names = "camss\0ife1"; | |
| phandle = <0x591>; | |
| clock-rates = <0x00 0x5f5e100 0x14dc9380 0x00 0x00 0x00 0xbebc200 0x1c4fecc0 0x00 0x00 0x00 0x11e1a300 0x22551000 0x00 0x00 0x00 0x17d78400 0x2aea5400 0x00 0x00>; | |
| }; | |
| tpdm@6e00000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-tpdm-ddr"; | |
| compatible = "arm,primecell"; | |
| status = "disabled"; | |
| reg = <0x6e00000 0x1000>; | |
| phandle = <0x1ef>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x22f>; | |
| phandle = <0x228>; | |
| }; | |
| }; | |
| }; | |
| tpdm@7861000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-tpdm-apss"; | |
| compatible = "arm,primecell"; | |
| reg = <0x7861000 0x1000>; | |
| phandle = <0x500>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x210>; | |
| phandle = <0x20c>; | |
| }; | |
| }; | |
| }; | |
| i2c@a94000 { | |
| pinctrl-names = "default\0sleep"; | |
| #address-cells = <0x01>; | |
| pinctrl-0 = <0x2af>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| interrupts = <0x00 0x166 0x04>; | |
| clocks = <0x16 0x74 0x16 0x86 0x16 0x87>; | |
| #size-cells = <0x00>; | |
| qcom,i2c-touch-active = "goodix,gt738x"; | |
| qcom,wrapper-core = <0x2a3>; | |
| dma-names = "tx\0rx"; | |
| compatible = "qcom,i2c-geni"; | |
| pinctrl-1 = <0x2b0>; | |
| status = "ok"; | |
| reg = <0xa94000 0x4000>; | |
| phandle = <0x5b6>; | |
| dmas = <0x2a4 0x00 0x05 0x03 0x40 0x00 0x2a4 0x01 0x05 0x03 0x40 0x00>; | |
| st_fts@49 { | |
| pinctrl-names = "pmx_ts_active\0pmx_ts_suspend"; | |
| avdd-supply = <0x37f>; | |
| st,irq-gpio = <0x66 0x27 0x2008>; | |
| st,y-flip = <0x01>; | |
| pinctrl-0 = <0x3f5>; | |
| st,x-flip = <0x01>; | |
| interrupts = <0x27 0x2008>; | |
| interrupt-parent = <0x66>; | |
| st,regulator_dvdd = "vdd"; | |
| st,regulator_avdd = "avdd"; | |
| vdd-supply = <0x384>; | |
| compatible = "st,fts"; | |
| st,reset-gpio = <0x66 0x26 0x00>; | |
| pinctrl-1 = <0x3f6 0x3f7>; | |
| reg = <0x49>; | |
| panel = <0x63f 0x697 0x698>; | |
| }; | |
| goodix-gt738x@5d { | |
| pinctrl-names = "pmx_ts_active\0pmx_ts_suspend\0pmx_ts_release"; | |
| avdd-supply = <0x37f>; | |
| pinctrl-2 = <0x3f8>; | |
| goodix,reset-gpio = <0x66 0x26 0x00>; | |
| pinctrl-0 = <0x3f5>; | |
| goodix,panel-max-x = <0xa00>; | |
| goodix,avdd-name = "avdd"; | |
| vdd-supply = <0x384>; | |
| compatible = "goodix,gt738x"; | |
| vddio-supply = <0x7e>; | |
| pinctrl-1 = <0x3f6 0x3f7>; | |
| goodix,vddio-name = "vddio"; | |
| goodix,irq-flags = <0x02>; | |
| goodix,panel-max-y = <0x640>; | |
| reg = <0x5d>; | |
| goodix,panel-max-w = <0x940>; | |
| panel = <0x699 0x69a>; | |
| goodix,vdd-name = "vdd"; | |
| goodix,irq-gpio = <0x66 0x27 0x2008>; | |
| }; | |
| }; | |
| apps_iommu_test_device { | |
| iommus = <0x47 0x21 0x00>; | |
| compatible = "iommu-debug-test"; | |
| qcom,iommu-dma = "disabled"; | |
| }; | |
| tpdm@6c41000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| qcom,proxy-regs = "vdd\0vdd_cx"; | |
| clock-names = "apb_pclk\0gcc_npu_axi_clk\0gcc_npu_cfg_ahb_clk\0npu_cc_xo_clk\0npu_core_clk\0npu_core_clk_src\0npu_cc_atb_clk\0npu_cc_dpm_clk\0npu_cc_dpm_xo_clk\0npu_cc_dl_dpm_clk"; | |
| reg-names = "tpdm-base"; | |
| qcom,proxy-clks = "gcc_npu_axi_clk\0gcc_npu_cfg_ahb_clk\0npu_cc_xo_clk\0npu_core_clk\0npu_core_clk_src\0npu_cc_atb_clk\0npu_cc_dpm_clk\0npu_cc_dpm_xo_clk\0npu_cc_dl_dpm_clk"; | |
| clocks = <0x49 0x00 0x16 0x28 0x16 0x2b 0x55 0x28 0x55 0x0d 0x55 0x0e 0x55 0x00 0x55 0x11 0x55 0x13 0x55 0x0f>; | |
| coresight-name = "coresight-tpdm-npu-dpm"; | |
| vdd-supply = <0x1de>; | |
| compatible = "arm,primecell"; | |
| reg = <0x6c41000 0x1000>; | |
| phandle = <0x1f9>; | |
| vdd_cx-supply = <0x67>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x1e1>; | |
| phandle = <0x21d>; | |
| }; | |
| }; | |
| }; | |
| etm@7240000 { | |
| arm,primecell-periphid = <0xbb95d>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x49 0x00>; | |
| cpu = <0x0f>; | |
| qcom,tupwr-disable; | |
| coresight-name = "coresight-etm2"; | |
| compatible = "arm,primecell"; | |
| reg = <0x7240000 0x1000>; | |
| phandle = <0x549>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x23d>; | |
| phandle = <0x246>; | |
| }; | |
| }; | |
| }; | |
| qcom,qmp-aop@c300000 { | |
| qcom,early-boot; | |
| reg-names = "msgram"; | |
| interrupts = <0x00 0x00 0x01>; | |
| #mbox-cells = <0x01>; | |
| interrupt-parent = <0x8a>; | |
| label = "aop"; | |
| mbox-desc-offset = <0x00>; | |
| priority = <0x00>; | |
| compatible = "qcom,qmp-mbox"; | |
| reg = <0xc300000 0x1000>; | |
| phandle = <0x02>; | |
| mboxes = <0x8a 0x00 0x00>; | |
| mbox-names = "aop_qmp"; | |
| }; | |
| qcedev@1de0000 { | |
| iommus = <0x47 0x586 0x11 0x47 0x596 0x11>; | |
| qcom,ce-hw-shared; | |
| qcom,ce-device = <0x00>; | |
| reg-names = "crypto-base\0crypto-bam-base"; | |
| qcom,msm-bus,name = "qcedev-noc"; | |
| qcom,bam-ee = <0x00>; | |
| interrupts = <0x00 0x110 0x04>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| compatible = "qcom,qcedev"; | |
| qcom,no-clock-support; | |
| qcom,bam-pipe-pair = <0x03>; | |
| reg = <0x1de0000 0x20000 0x1dc4000 0x24000>; | |
| phandle = <0x3a0>; | |
| qcom,msm-bus,vectors-KBps = <0x7d 0x200 0x00 0x00 0x7d 0x200 0x60180 0x60180>; | |
| qcom,smmu-s1-enable; | |
| qcom,ce-hw-instance = <0x00>; | |
| qcom,iommu-dma = "atomic"; | |
| qcom_cedev_s_cb { | |
| iommus = <0x47 0x593 0x00 0x47 0x59c 0x00 0x47 0x59d 0x00 0x47 0x59e 0x00>; | |
| qcom,secure-context-bank; | |
| label = "secure_context"; | |
| compatible = "qcom,qcedev,context-bank"; | |
| qcom,iommu-vmid = <0x09>; | |
| }; | |
| qcom_cedev_ns_cb { | |
| iommus = <0x47 0x592 0x00 0x47 0x598 0x00 0x47 0x599 0x00 0x47 0x59f 0x00>; | |
| label = "ns_context"; | |
| compatible = "qcom,qcedev,context-bank"; | |
| }; | |
| }; | |
| tgu@6b0b000 { | |
| arm,primecell-periphid = <0xbb999>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tgu-base"; | |
| clocks = <0x49 0x00>; | |
| tgu-regs = <0x04>; | |
| tgu-steps = <0x03>; | |
| coresight-name = "coresight-tgu-ipcb"; | |
| tgu-conditions = <0x04>; | |
| compatible = "arm,primecell"; | |
| reg = <0x6b0b000 0x1000>; | |
| phandle = <0x544>; | |
| tgu-timer-counters = <0x08>; | |
| }; | |
| funnel@6e12000 { | |
| arm,primecell-periphid = <0xbb908>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "funnel-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-funnel-ddr-ch02"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6e12000 0x1000>; | |
| phandle = <0x506>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x229>; | |
| phandle = <0x226>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x00>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x22a>; | |
| phandle = <0x22d>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| csr@6001000 { | |
| qcom,set-byte-cntr-support; | |
| qcom,blk-size = <0x01>; | |
| qcom,hwctrl-set-support; | |
| reg-names = "csr-base"; | |
| coresight-name = "coresight-csr"; | |
| qcom,usb-bam-support; | |
| compatible = "qcom,coresight-csr"; | |
| reg = <0x6001000 0x1000>; | |
| phandle = <0x1a2>; | |
| }; | |
| qcom,msm-dai-q6-spdif-pri-tx { | |
| compatible = "qcom,msm-dai-q6-spdif"; | |
| qcom,msm-dai-q6-dev-id = <0x5001>; | |
| phandle = <0x5f3>; | |
| }; | |
| cti@6c0a000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti-dlmm_cti1"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6c0a000 0x1000>; | |
| phandle = <0x515>; | |
| }; | |
| qcom,qup_uart@890000 { | |
| pinctrl-names = "default\0sleep"; | |
| pinctrl-0 = <0x2c0 0x2c1>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| reg-names = "se_phys"; | |
| clocks = <0x16 0x80 0x16 0x88 0x16 0x89>; | |
| qcom,wrapper-core = <0x2bf>; | |
| interrupts-extended = <0x01 0x00 0x24a 0x04 0x66 0x3b 0x00>; | |
| compatible = "qcom,msm-geni-serial-hs"; | |
| pinctrl-1 = <0x2c0 0x2c1>; | |
| status = "disabled"; | |
| reg = <0x890000 0x4000>; | |
| phandle = <0x5be>; | |
| qcom,wakeup-byte = <0xfd>; | |
| }; | |
| jtagmm@7340000 { | |
| clock-names = "core_clk"; | |
| reg-names = "etm-base"; | |
| clocks = <0x49 0x00>; | |
| compatible = "qcom,jtagv8-mm"; | |
| qcom,coresight-jtagmm-cpu = <0x10>; | |
| reg = <0x7340000 0x1000>; | |
| phandle = <0x355>; | |
| }; | |
| qcom,sde_rscc@af20000 { | |
| qcom,sde-rsc-version = <0x03>; | |
| clock-names = "vsync_clk\0gdsc_clk\0iface_clk"; | |
| reg-names = "drv\0wrapper"; | |
| cell-index = <0x00>; | |
| qcom,sde-dram-channels = <0x02>; | |
| clocks = <0x6c 0x35 0x6c 0x2d 0x6c 0x34>; | |
| vdd-supply = <0x71>; | |
| compatible = "qcom,sde-rsc"; | |
| reg = <0xaf20000 0x3c50 0xaf30000 0x3fd4>; | |
| phandle = <0x553>; | |
| qcom,sde-reg-bus { | |
| qcom,msm-bus,name = "disp_rsc_reg"; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x04>; | |
| qcom,msm-bus,vectors-KBps = <0x01 0x24e 0x00 0x00 0x01 0x24e 0x00 0x12c00 0x01 0x24e 0x00 0x249f0 0x01 0x24e 0x00 0x493e0>; | |
| }; | |
| qcom,sde-data-bus { | |
| qcom,msm-bus,name = "disp_rsc_mnoc_llcc"; | |
| qcom,msm-bus,active-only; | |
| qcom,msm-bus,num-paths = <0x02>; | |
| qcom,msm-bus,num-cases = <0x03>; | |
| qcom,msm-bus,vectors-KBps = <0x4e23 0x5021 0x00 0x00 0x4e24 0x5021 0x00 0x00 0x4e23 0x5021 0x00 0x61a800 0x4e24 0x5021 0x00 0x61a800 0x4e23 0x5021 0x00 0x61a800 0x4e24 0x5021 0x00 0x61a800>; | |
| }; | |
| qcom,sde-ebi-bus { | |
| qcom,msm-bus,name = "disp_rsc_ebi"; | |
| qcom,msm-bus,active-only; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x03>; | |
| qcom,msm-bus,vectors-KBps = <0x4e20 0x5020 0x00 0x00 0x4e20 0x5020 0x00 0x61a800 0x4e20 0x5020 0x00 0x61a800>; | |
| }; | |
| }; | |
| gpu-opp-table_v2 { | |
| compatible = "operating-points-v2"; | |
| phandle = <0x332>; | |
| opp-490000000 { | |
| opp-microvolt = <0xc0>; | |
| opp-hz = <0x00 0x1d34ce80>; | |
| }; | |
| opp-670000000 { | |
| opp-microvolt = <0x140>; | |
| opp-hz = <0x00 0x27ef6380>; | |
| }; | |
| opp-441600000 { | |
| opp-microvolt = <0x90>; | |
| opp-hz = <0x00 0x1a524800>; | |
| }; | |
| opp-305000000 { | |
| opp-microvolt = <0x40>; | |
| opp-hz = <0x00 0x122dee40>; | |
| }; | |
| opp-587000000 { | |
| opp-microvolt = <0x100>; | |
| opp-hz = <0x00 0x22fce8c0>; | |
| }; | |
| opp-400000000 { | |
| opp-microvolt = <0x80>; | |
| opp-hz = <0x00 0x17d78400>; | |
| }; | |
| opp-525000000 { | |
| opp-microvolt = <0xe0>; | |
| opp-hz = <0x00 0x1f4add40>; | |
| }; | |
| }; | |
| cti@6e0c000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti-ddr_dl_1_cti_0"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6e0c000 0x1000>; | |
| phandle = <0x50f>; | |
| }; | |
| qcom,cpu4-cpu-ddr-latfloor { | |
| qcom,src-dst-ports = <0x81 0x200>; | |
| governor = "performance"; | |
| compatible = "qcom,devbw-ddr"; | |
| phandle = <0x5e>; | |
| qcom,active-only; | |
| operating-points-v2 = <0x4d>; | |
| }; | |
| qcom,videocc@abf0000 { | |
| #reset-cells = <0x01>; | |
| clock-names = "cfg_ahb_clk"; | |
| reg-names = "cc_base"; | |
| clocks = <0x16 0xcd>; | |
| vdd_mm-supply = <0x69>; | |
| #clock-cells = <0x01>; | |
| vdd_mx-supply = <0x6a>; | |
| compatible = "qcom,videocc-kona-v2\0syscon"; | |
| reg = <0xabf0000 0x10000>; | |
| phandle = <0x6b>; | |
| }; | |
| cti@601f000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti15"; | |
| compatible = "arm,primecell"; | |
| reg = <0x601f000 0x1000>; | |
| phandle = <0x527>; | |
| }; | |
| cti@6845000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti-lpass_dl_cti"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6845000 0x1000>; | |
| phandle = <0x533>; | |
| }; | |
| qcom,msm-pcm-dsp-noirq { | |
| qcom,latency-level = "ultra"; | |
| compatible = "qcom,msm-pcm-dsp-noirq"; | |
| phandle = <0x2ec>; | |
| qcom,msm-pcm-low-latency; | |
| }; | |
| qcom,dp_display@ae90000 { | |
| qcom,aux-cfg1-settings = [24 13]; | |
| pinctrl-names = "mdss_dp_active\0mdss_dp_sleep"; | |
| qcom,usbplug-cc-gpio = <0x66 0x41 0x00>; | |
| qcom,aux-cfg6-settings = [38 0a]; | |
| pinctrl-0 = <0x40c>; | |
| qcom,ext-disp = <0x642>; | |
| clock-names = "core_aux_clk\0core_usb_ref_clk_src\0core_usb_pipe_clk\0link_clk\0link_iface_clk\0pixel_clk_rcg\0pixel_parent\0pixel1_clk_rcg\0pixel1_parent\0strm0_pixel_clk\0strm1_pixel_clk"; | |
| reg-names = "dp_ahb\0dp_aux\0dp_link\0dp_p0\0dp_phy\0dp_ln_tx0\0dp_ln_tx1\0dp_mmss_cc\0dp_pll\0usb3_dp_com\0hdcp_physical\0dp_p1"; | |
| qcom,mst-enable; | |
| qcom,aux-cfg2-settings = [28 a4]; | |
| cell-index = <0x00>; | |
| qcom,dp-aux-switch = <0x32c>; | |
| interrupts = <0x0c 0x00>; | |
| clocks = <0x6c 0x0c 0x15 0x00 0x16 0xc5 0x6c 0x12 0x6c 0x15 0x6c 0x1b 0x24d 0x05 0x6c 0x17 0x24d 0x05 0x6c 0x1a 0x6c 0x16>; | |
| qcom,max-pclk-frequency-khz = <0xa4cb8>; | |
| qcom,aux-cfg7-settings = [3c 03]; | |
| qcom,dsc-feature-enable; | |
| extcon = <0x637>; | |
| interrupt-parent = <0x24c>; | |
| qcom,aux-cfg3-settings = ","; | |
| vdda-1p2-supply = <0x7d>; | |
| qcom,aux-cfg8-settings = [40 b7]; | |
| qcom,fec-feature-enable; | |
| compatible = "qcom,dp-display"; | |
| pinctrl-1 = <0x40d>; | |
| vdda-0p9-supply = <0x187>; | |
| qcom,aux-cfg4-settings = [30 0a]; | |
| reg = <0xae90000 0xdc 0xae90200 0xc0 0xae90400 0x508 0xae91000 0x94 0x88eaa00 0x200 0x88ea200 0x200 0x88ea600 0x200 0xaf02000 0x1a0 0x88ea040 0x10 0x88e8000 0x20 0xaee1000 0x34 0xae91400 0x94>; | |
| qcom,phy-version = <0x420>; | |
| phandle = <0x552>; | |
| qcom,max-dp-dsc-blks = <0x02>; | |
| qcom,aux-cfg9-settings = [44 03]; | |
| qcom,max-dp-dsc-input-width-pixs = <0x800>; | |
| qcom,aux-cfg0-settings = " "; | |
| qcom,dp-usbpd-detection = <0x637>; | |
| qcom,aux-cfg5-settings = [34 26]; | |
| qcom,widebus-enable; | |
| qcom,ctrl-supply-entries { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,ctrl-supply-entry@0 { | |
| qcom,supply-disable-load = <0x00>; | |
| qcom,supply-enable-load = <0x80e8>; | |
| qcom,supply-name = "vdda-1p2"; | |
| qcom,supply-max-voltage = <0x124f80>; | |
| reg = <0x00>; | |
| qcom,supply-min-voltage = <0x124f80>; | |
| }; | |
| }; | |
| qcom,phy-supply-entries { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,phy-supply-entry@0 { | |
| qcom,supply-disable-load = <0x00>; | |
| qcom,supply-enable-load = <0x1ec30>; | |
| qcom,supply-name = "vdda-0p9"; | |
| qcom,supply-max-voltage = <0xdea80>; | |
| reg = <0x00>; | |
| qcom,supply-min-voltage = <0xdea80>; | |
| }; | |
| }; | |
| qcom,core-supply-entries { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,core-supply-entry@0 { | |
| qcom,supply-disable-load = <0x00>; | |
| qcom,supply-enable-load = <0x00>; | |
| qcom,supply-name = "refgen"; | |
| qcom,supply-max-voltage = <0x00>; | |
| reg = <0x00>; | |
| qcom,supply-min-voltage = <0x00>; | |
| }; | |
| }; | |
| }; | |
| qcom,npu-npu-ddr-latfloor { | |
| qcom,src-dst-ports = <0x9a 0x200>; | |
| governor = "powersave"; | |
| compatible = "qcom,devbw-ddr"; | |
| phandle = <0x54>; | |
| operating-points-v2 = <0x51>; | |
| }; | |
| qcom,camera-flash2 { | |
| cell-index = <0x02>; | |
| torch-source = <0x648 0x649>; | |
| switch-source = <0x64a>; | |
| compatible = "qcom,camera-flash"; | |
| status = "ok"; | |
| phandle = <0x651>; | |
| flash-source = <0x646 0x647>; | |
| }; | |
| tmc@6048000 { | |
| iommus = <0x47 0x480 0x00 0x47 0x520 0x00>; | |
| arm,buffer-size = <0x400000>; | |
| arm,primecell-periphid = <0xbb961>; | |
| coresight-ctis = <0x1a1 0x192>; | |
| #address-cells = <0x01>; | |
| arm,scatter-gather; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tmc-base\0bam-base"; | |
| interrupts = <0x00 0x10e 0x01>; | |
| clocks = <0x49 0x00>; | |
| #size-cells = <0x01>; | |
| coresight-name = "coresight-tmc-etr"; | |
| compatible = "arm,primecell"; | |
| ranges; | |
| interrupt-names = "byte-cntr-irq"; | |
| reg = <0x6048000 0x1000 0x6064000 0x15000>; | |
| phandle = <0x4e5>; | |
| coresight-csr = <0x1a2>; | |
| port { | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x1a3>; | |
| phandle = <0x18b>; | |
| }; | |
| }; | |
| }; | |
| funnel@6832000 { | |
| arm,primecell-periphid = <0xbb908>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "funnel-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-funnel-venus"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6832000 0x1000>; | |
| phandle = <0x502>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x215>; | |
| phandle = <0x212>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x00>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x216>; | |
| phandle = <0x217>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| spi@984000 { | |
| pinctrl-names = "default\0sleep"; | |
| #address-cells = <0x01>; | |
| pinctrl-0 = <0x293>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| reg-names = "se_phys"; | |
| interrupts = <0x00 0x25a 0x04>; | |
| clocks = <0x16 0x5a 0x16 0x84 0x16 0x85>; | |
| #size-cells = <0x00>; | |
| qcom,wrapper-core = <0x274>; | |
| spi-max-frequency = <0x2faf080>; | |
| dma-names = "tx\0rx"; | |
| compatible = "qcom,spi-geni"; | |
| pinctrl-1 = <0x294>; | |
| status = "disabled"; | |
| reg = <0x984000 0x4000>; | |
| phandle = <0x5a9>; | |
| dmas = <0x280 0x00 0x01 0x01 0x40 0x00 0x280 0x01 0x01 0x01 0x40 0x00>; | |
| }; | |
| cti@601c000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti12"; | |
| compatible = "arm,primecell"; | |
| reg = <0x601c000 0x1000>; | |
| phandle = <0x524>; | |
| }; | |
| qcom,gdsc@ad0c144 { | |
| clock-names = "ahb_clk"; | |
| qcom,gds-timeout = <0x1f4>; | |
| qcom,msm-bus,name = "titan_top_gdsc_ahb"; | |
| parent-supply = <0x69>; | |
| qcom,retain-regs; | |
| clocks = <0x16 0x0b>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| regulator-name = "titan_top_gdsc"; | |
| vdd_parent-supply = <0x69>; | |
| compatible = "qcom,gdsc"; | |
| reg = <0xad0c144 0x04>; | |
| phandle = <0x253>; | |
| qcom,msm-bus,vectors-KBps = <0x01 0x24d 0x00 0x00 0x01 0x24d 0x00 0x01>; | |
| }; | |
| qcom,msm-dai-tdm-quin-tx { | |
| qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
| qcom,msm-cpudai-tdm-data-out = <0x00>; | |
| qcom,msm-cpudai-tdm-data-delay = <0x01>; | |
| qcom,msm-cpudai-tdm-group-port-id = <0x9041>; | |
| qcom,msm-cpudai-tdm-group-num-ports = <0x01>; | |
| qcom,msm-cpudai-tdm-invert-sync = <0x01>; | |
| compatible = "qcom,msm-dai-tdm"; | |
| qcom,msm-cpudai-tdm-group-id = <0x9141>; | |
| phandle = <0x5ef>; | |
| qcom,msm-cpudai-tdm-sync-src = <0x01>; | |
| qcom,msm-cpudai-tdm-clk-internal = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-mode = <0x01>; | |
| qcom,msm-dai-q6-tdm-quin-tx-0 { | |
| qcom,msm-cpudai-tdm-dev-id = <0x9041>; | |
| qcom,msm-cpudai-tdm-data-align = <0x00>; | |
| compatible = "qcom,msm-dai-q6-tdm"; | |
| phandle = <0x312>; | |
| }; | |
| }; | |
| qcom,cam-fd { | |
| compat-hw-name = "qcom,fd"; | |
| compatible = "qcom,cam-fd"; | |
| status = "ok"; | |
| num-fd = <0x01>; | |
| }; | |
| qcom,mdss_dsi_pll@ae96900 { | |
| clock-names = "iface_clk"; | |
| reg-names = "pll_base\0phy_base\0gdsc_base\0dynamic_pll_base"; | |
| cell-index = <0x01>; | |
| clocks = <0x6c 0x00>; | |
| #clock-cells = <0x01>; | |
| label = "MDSS DSI 1 PLL"; | |
| compatible = "qcom,mdss_dsi_pll_7nm_v4_1"; | |
| clock-rate = <0x00>; | |
| qcom,dsi-pll-ssc-mode = "down-spread"; | |
| reg = <0xae96900 0x260 0xae96400 0x800 0xaf03000 0x08 0xae96200 0x100>; | |
| phandle = <0x55c>; | |
| qcom,dsi-pll-ssc-en; | |
| }; | |
| qcom,gdsc@17d050 { | |
| qcom,no-status-check-on-disable; | |
| qcom,gds-timeout = <0x1f4>; | |
| regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc"; | |
| compatible = "qcom,gdsc"; | |
| reg = <0x17d050 0x04>; | |
| phandle = <0x17d>; | |
| }; | |
| qcom,msm-dai-q6-spdif-pri-rx { | |
| compatible = "qcom,msm-dai-q6-spdif"; | |
| qcom,msm-dai-q6-dev-id = <0x5000>; | |
| phandle = <0x5f2>; | |
| }; | |
| funnel@6e04000 { | |
| arm,primecell-periphid = <0xbb908>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "funnel-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-funnel-ddr-0"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6e04000 0x1000>; | |
| phandle = <0x505>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x225>; | |
| phandle = <0x201>; | |
| }; | |
| }; | |
| port@3 { | |
| reg = <0x02>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x228>; | |
| phandle = <0x22f>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x00>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x226>; | |
| phandle = <0x229>; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x01>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x227>; | |
| phandle = <0x22b>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| suspendable-ddr-bw-opp-table { | |
| compatible = "operating-points-v2"; | |
| phandle = <0x51>; | |
| opp-1017 { | |
| opp-hz = <0x00 0xf27>; | |
| opp-supported-hw = <0x180>; | |
| }; | |
| opp-2736 { | |
| opp-hz = <0x00 0x28c5>; | |
| opp-supported-hw = <0x100>; | |
| }; | |
| opp-300 { | |
| opp-hz = <0x00 0x478>; | |
| opp-supported-hw = <0x180>; | |
| }; | |
| opp-451 { | |
| opp-hz = <0x00 0x6b8>; | |
| opp-supported-hw = <0x180>; | |
| }; | |
| opp-1353 { | |
| opp-hz = <0x00 0x1429>; | |
| opp-supported-hw = <0x80>; | |
| }; | |
| opp-2092 { | |
| opp-hz = <0x00 0x1f2c>; | |
| opp-supported-hw = <0x180>; | |
| }; | |
| opp-1804 { | |
| opp-hz = <0x00 0x1ae1>; | |
| opp-supported-hw = <0x180>; | |
| }; | |
| opp-768 { | |
| opp-hz = <0x00 0xb71>; | |
| opp-supported-hw = <0x180>; | |
| }; | |
| opp-200 { | |
| opp-hz = <0x00 0x2fa>; | |
| opp-supported-hw = <0x180>; | |
| }; | |
| opp-681 { | |
| opp-hz = <0x00 0xa25>; | |
| opp-supported-hw = <0x180>; | |
| }; | |
| opp-1555 { | |
| opp-hz = <0x00 0x172b>; | |
| opp-supported-hw = <0x180>; | |
| }; | |
| opp-547 { | |
| opp-hz = <0x00 0x826>; | |
| opp-supported-hw = <0x180>; | |
| }; | |
| opp-0 { | |
| opp-hz = <0x00 0x00>; | |
| opp-supported-hw = <0x180>; | |
| }; | |
| }; | |
| qcom,qupv3_0_geni_se@9c0000 { | |
| iommus = <0x47 0x5a3 0x00>; | |
| qcom,bus-mas-id = <0x97>; | |
| qcom,bus-slv-id = <0x200>; | |
| compatible = "qcom,qupv3-geni-se"; | |
| qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>; | |
| reg = <0x9c0000 0x2000>; | |
| phandle = <0x274>; | |
| qcom,iommu-dma = "fastmap"; | |
| }; | |
| qcom,csiphy@ac6c000 { | |
| clock-names = "cphy_rx_clk_src\0csiphy1_clk\0csi1phytimer_clk_src\0csi1phytimer_clk"; | |
| reg-names = "csiphy"; | |
| reg-cam-base = <0x6c000>; | |
| csi-vdd-voltage = <0x124f80>; | |
| cell-index = <0x01>; | |
| interrupts = <0x00 0x1de 0x01>; | |
| clocks = <0x6d 0x0e 0x6d 0x1c 0x6d 0x12 0x6d 0x11>; | |
| gdscr-supply = <0x253>; | |
| clock-cntl-level = "turbo"; | |
| compatible = "qcom,csiphy-v1.2.1\0qcom,csiphy"; | |
| src-clock-name = "csi1phytimer_clk_src"; | |
| mipi-csi-vdd-supply = <0x7d>; | |
| status = "ok"; | |
| interrupt-names = "csiphy"; | |
| reg = <0xac6c000 0x2000>; | |
| regulator-names = "gdscr\0refgen"; | |
| phandle = <0x55e>; | |
| refgen-supply = <0xb4>; | |
| clock-rates = <0x17d78400 0x00 0x11e1a300 0x00>; | |
| }; | |
| qcom,ife-lite1@acdb200 { | |
| camss-supply = <0x253>; | |
| clock-control-debugfs = "true"; | |
| clock-names = "ife_lite_ahb\0ife_lite_axi\0ife_clk_src\0ife_clk"; | |
| reg-names = "ife-lite"; | |
| reg-cam-base = <0xdb200>; | |
| cell-index = <0x03>; | |
| interrupts = <0x00 0x168 0x01>; | |
| clocks = <0x6d 0x3b 0x6d 0x3c 0x6d 0x3e 0x6d 0x3d>; | |
| clock-cntl-level = "lowsvs\0svs\0svs_l1\0turbo"; | |
| compatible = "qcom,vfe-lite480"; | |
| src-clock-name = "ife_clk_src"; | |
| status = "ok"; | |
| interrupt-names = "ife-lite"; | |
| reg = <0xacdb200 0x2200>; | |
| regulator-names = "camss"; | |
| phandle = <0x595>; | |
| clock-rates = <0x00 0x00 0x17d78400 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x1c9c3800 0x00>; | |
| }; | |
| aop-msg-client { | |
| compatible = "qcom,debugfs-qmp-client"; | |
| mboxes = <0x02 0x00>; | |
| mbox-names = "aop"; | |
| }; | |
| qcom,bps { | |
| clock-control-debugfs = "true"; | |
| clock-names = "bps_ahb_clk\0bps_areg_clk\0bps_axi_clk\0bps_clk_src\0bps_clk"; | |
| reg-names = "bps_top"; | |
| reg-cam-base = <0x7a000>; | |
| cell-index = <0x00>; | |
| bps-vdd-supply = <0x270>; | |
| clocks = <0x6d 0x00 0x6d 0x01 0x6d 0x02 0x6d 0x04 0x6d 0x03>; | |
| clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; | |
| compatible = "qcom,cam-bps"; | |
| src-clock-name = "bps_clk_src"; | |
| status = "ok"; | |
| reg = <0xac7a000 0x8000>; | |
| regulator-names = "bps-vdd"; | |
| phandle = <0x598>; | |
| clock-rates = <0x00 0x00 0x00 0xbebc200 0x00 0x00 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x23c34600 0x00 0x00 0x00 0x00 0x23c34600 0x00>; | |
| }; | |
| i2c@990000 { | |
| pinctrl-names = "default\0sleep"; | |
| #address-cells = <0x01>; | |
| pinctrl-0 = <0x289>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| interrupts = <0x00 0x25d 0x04>; | |
| clocks = <0x16 0x60 0x16 0x84 0x16 0x85>; | |
| #size-cells = <0x00>; | |
| qcom,wrapper-core = <0x274>; | |
| dma-names = "tx\0rx"; | |
| compatible = "qcom,i2c-geni"; | |
| pinctrl-1 = <0x28a>; | |
| status = "ok"; | |
| reg = <0x990000 0x4000>; | |
| phandle = <0x5a4>; | |
| dmas = <0x280 0x00 0x04 0x03 0x40 0x00 0x280 0x01 0x04 0x03 0x40 0x00>; | |
| qcom,clk-freq-out = <0x61a80>; | |
| cs35l41@40 { | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x686 0x687>; | |
| cirrus,boost-ind-nanohenry = <0x3e8>; | |
| VA-supply = <0x2c7>; | |
| interrupts = <0x43 0x08>; | |
| interrupt-parent = <0x66>; | |
| cirrus,runtime-channel-switch = <0x01>; | |
| cirrus,asp-sdout-hiz = <0x03>; | |
| reset-gpios = <0x66 0x83 0x00>; | |
| compatible = "cirrus,cs35l41"; | |
| cirrus,fast-switch = "spk1_fast_switch1.txt\0spk1_fast_switch2.txt\0spk1_fast_switch3.txt"; | |
| #interrupt-cells = <0x02>; | |
| interrupt-names = "cs35l41_1_irq"; | |
| cirrus,boost-cap-microfarad = <0x0f>; | |
| reg = <0x40>; | |
| cirrus,boost-peak-milliamp = <0xdac>; | |
| phandle = <0x663>; | |
| interrupt-controller; | |
| cirrus,gpio-config2 { | |
| cirrus,gpio-output-enable; | |
| cirrus,gpio-type = <0x01>; | |
| cirrus,gpio-src-select = <0x04>; | |
| }; | |
| adsps { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| adsp@2b80000 { | |
| reg = <0x2b80000>; | |
| firmware { | |
| calibration { | |
| cirrus,wmfw-file = "cs35l41-dsp1-spk-diag.wmfw"; | |
| cirrus,bin-file = "cs35l41-dsp1-spk-cali.bin"; | |
| cirrus,full-name; | |
| }; | |
| protection { | |
| cirrus,wmfw-file = "cs35l41-dsp1-spk-prot.wmfw"; | |
| cirrus,bin-file = "cs35l41-dsp1-spk-prot1.bin"; | |
| cirrus,full-name; | |
| }; | |
| }; | |
| }; | |
| }; | |
| }; | |
| keyboard@61 { | |
| pinctrl-names = "mcu_pin"; | |
| pinctrl-0 = <0x4d8>; | |
| interrupts = <0x0b 0x2002>; | |
| interrupt-parent = <0x66>; | |
| vdd-supply = <0x2c7>; | |
| compatible = "hid-over-i2c"; | |
| post-power-on-delay-ms = <0x64>; | |
| reg = <0x61>; | |
| phandle = <0x743>; | |
| vddl-supply = <0x2c8>; | |
| hid-descr-addr = <0x01>; | |
| }; | |
| redriver@19 { | |
| output-comp = <0x3030303 0x3030303>; | |
| flat-gain = <0x3010103 0x30300>; | |
| extcon = <0x637 0x637>; | |
| loss-match = <0x1030301 0x3030303>; | |
| vdd-supply = <0x2c7>; | |
| compatible = "onnn,redriver"; | |
| eq = <0x4040404 0x4060604>; | |
| reg = <0x19>; | |
| phandle = <0x745>; | |
| }; | |
| cs35l41@43 { | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x68a 0x687>; | |
| cirrus,boost-ind-nanohenry = <0x3e8>; | |
| VA-supply = <0x2c7>; | |
| interrupts = <0x44 0x08>; | |
| interrupt-parent = <0x66>; | |
| cirrus,runtime-channel-switch = <0x01>; | |
| cirrus,asp-sdout-hiz = <0x03>; | |
| reset-gpios = <0x66 0x83 0x00>; | |
| compatible = "cirrus,cs35l41"; | |
| cirrus,fast-switch = "spk4_fast_switch1.txt\0spk4_fast_switch2.txt\0spk4_fast_switch3.txt"; | |
| #interrupt-cells = <0x02>; | |
| interrupt-names = "cs35l41_4_irq"; | |
| cirrus,boost-cap-microfarad = <0x0f>; | |
| reg = <0x43>; | |
| cirrus,boost-peak-milliamp = <0xdac>; | |
| phandle = <0x666>; | |
| interrupt-controller; | |
| cirrus,gpio-config2 { | |
| cirrus,gpio-output-enable; | |
| cirrus,gpio-type = <0x01>; | |
| cirrus,gpio-src-select = <0x04>; | |
| }; | |
| adsps { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| adsp@2b80000 { | |
| reg = <0x2b80000>; | |
| firmware { | |
| calibration { | |
| cirrus,wmfw-file = "cs35l41-dsp1-spk-diag.wmfw"; | |
| cirrus,bin-file = "cs35l41-dsp1-spk-cali.bin"; | |
| cirrus,full-name; | |
| }; | |
| protection { | |
| cirrus,wmfw-file = "cs35l41-dsp1-spk-prot.wmfw"; | |
| cirrus,bin-file = "cs35l41-dsp1-spk-prot4.bin"; | |
| cirrus,full-name; | |
| }; | |
| }; | |
| }; | |
| }; | |
| }; | |
| cs35l41@41 { | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x688 0x687>; | |
| cirrus,boost-ind-nanohenry = <0x3e8>; | |
| VA-supply = <0x2c7>; | |
| interrupts = <0x71 0x08>; | |
| interrupt-parent = <0x66>; | |
| cirrus,runtime-channel-switch = <0x01>; | |
| cirrus,asp-sdout-hiz = <0x03>; | |
| reset-gpios = <0x66 0x83 0x00>; | |
| compatible = "cirrus,cs35l41"; | |
| cirrus,fast-switch = "spk2_fast_switch1.txt\0spk2_fast_switch2.txt\0spk2_fast_switch3.txt"; | |
| #interrupt-cells = <0x02>; | |
| interrupt-names = "cs35l41_2_irq"; | |
| cirrus,boost-cap-microfarad = <0x0f>; | |
| reg = <0x41>; | |
| cirrus,boost-peak-milliamp = <0xdac>; | |
| phandle = <0x664>; | |
| interrupt-controller; | |
| cirrus,gpio-config2 { | |
| cirrus,gpio-output-enable; | |
| cirrus,gpio-type = <0x01>; | |
| cirrus,gpio-src-select = <0x04>; | |
| }; | |
| adsps { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| adsp@2b80000 { | |
| reg = <0x2b80000>; | |
| firmware { | |
| calibration { | |
| cirrus,wmfw-file = "cs35l41-dsp1-spk-diag.wmfw"; | |
| cirrus,bin-file = "cs35l41-dsp1-spk-cali.bin"; | |
| cirrus,full-name; | |
| }; | |
| protection { | |
| cirrus,wmfw-file = "cs35l41-dsp1-spk-prot.wmfw"; | |
| cirrus,bin-file = "cs35l41-dsp1-spk-prot2.bin"; | |
| cirrus,full-name; | |
| }; | |
| }; | |
| }; | |
| }; | |
| }; | |
| cs35l41@42 { | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x689 0x687>; | |
| cirrus,boost-ind-nanohenry = <0x3e8>; | |
| VA-supply = <0x2c7>; | |
| interrupts = <0x7e 0x08>; | |
| interrupt-parent = <0x66>; | |
| cirrus,runtime-channel-switch = <0x01>; | |
| cirrus,asp-sdout-hiz = <0x03>; | |
| reset-gpios = <0x66 0x83 0x00>; | |
| compatible = "cirrus,cs35l41"; | |
| cirrus,fast-switch = "spk3_fast_switch1.txt\0spk3_fast_switch2.txt\0spk3_fast_switch3.txt"; | |
| #interrupt-cells = <0x02>; | |
| interrupt-names = "cs35l41_3_irq"; | |
| cirrus,boost-cap-microfarad = <0x0f>; | |
| reg = <0x42>; | |
| cirrus,boost-peak-milliamp = <0xdac>; | |
| phandle = <0x665>; | |
| interrupt-controller; | |
| cirrus,gpio-config2 { | |
| cirrus,gpio-output-enable; | |
| cirrus,gpio-type = <0x01>; | |
| cirrus,gpio-src-select = <0x04>; | |
| }; | |
| adsps { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| adsp@2b80000 { | |
| reg = <0x2b80000>; | |
| firmware { | |
| calibration { | |
| cirrus,wmfw-file = "cs35l41-dsp1-spk-diag.wmfw"; | |
| cirrus,bin-file = "cs35l41-dsp1-spk-cali.bin"; | |
| cirrus,full-name; | |
| }; | |
| protection { | |
| cirrus,wmfw-file = "cs35l41-dsp1-spk-prot.wmfw"; | |
| cirrus,bin-file = "cs35l41-dsp1-spk-prot3.bin"; | |
| cirrus,full-name; | |
| }; | |
| }; | |
| }; | |
| }; | |
| }; | |
| }; | |
| snfuse@0x786134 { | |
| reg-names = "sn-base"; | |
| compatible = "qcom,sn-fuse"; | |
| reg = <0x786134 0x04>; | |
| phandle = <0x350>; | |
| }; | |
| cti@6e11000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti-ddr_ch02_dl_cti_0"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6e11000 0x1000>; | |
| phandle = <0x512>; | |
| }; | |
| kgsl_iommu_test_device { | |
| iommus = <0x181 0x07 0x00>; | |
| compatible = "iommu-debug-test"; | |
| qcom,iommu-dma = "disabled"; | |
| }; | |
| qcom,msm_gsi { | |
| compatible = "qcom,msm_gsi"; | |
| }; | |
| qcom,cpu-cpu-llcc-bw { | |
| qcom,src-dst-ports = <0x01 0x302>; | |
| governor = "performance"; | |
| compatible = "qcom,devbw"; | |
| phandle = <0x4c>; | |
| qcom,active-only; | |
| operating-points-v2 = <0x4b>; | |
| }; | |
| qcom,cpas-cdm2@acc3200 { | |
| camss-supply = <0x253>; | |
| clock-names = "cam_cc_cpas_slow_ahb_clk\0cam_cc_cpas_ahb_clk"; | |
| reg-names = "cpas-cdm"; | |
| reg-cam-base = "\0\f2"; | |
| cdm-client-names = "ife1"; | |
| cell-index = <0x02>; | |
| interrupts = <0x00 0x11f 0x01>; | |
| clocks = <0x6d 0x6d 0x6d 0x0d>; | |
| label = "cpas-cdm"; | |
| clock-cntl-level = "svs"; | |
| compatible = "qcom,cam480-cpas-cdm2"; | |
| status = "disabled"; | |
| interrupt-names = "cpas-cdm"; | |
| reg = <0xacc3200 0x1000>; | |
| regulator-names = "camss"; | |
| clock-rates = <0x00 0x00>; | |
| }; | |
| qcom,cpufreq-hw { | |
| qcom,lut-row-size = <0x04>; | |
| clock-names = "xo\0alternate"; | |
| reg-names = "freq-domain0\0freq-domain1\0freq-domain2"; | |
| qcom,skip-enable-check; | |
| #freq-domain-cells = <0x02>; | |
| interrupts = <0x00 0x1e 0x04 0x00 0x1f 0x04 0x00 0x13 0x04>; | |
| clocks = <0x15 0x00 0x16 0xd1>; | |
| compatible = "qcom,cpufreq-hw-epss"; | |
| interrupt-names = "dcvsh0_int\0dcvsh1_int\0dcvsh2_int"; | |
| reg = <0x18591000 0x1000 0x18592000 0x1000 0x18593000 0x1000>; | |
| phandle = <0x04>; | |
| cpu7-notify { | |
| qcom,cooling-cpu = <0x14>; | |
| phandle = <0x27>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| qcom,cpu-isolation { | |
| compatible = "qcom,cpu-isolate"; | |
| cpu3-isolate { | |
| qcom,cpu = <0x10>; | |
| phandle = <0x25>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| cpu5-isolate { | |
| qcom,cpu = <0x12>; | |
| phandle = <0x2c>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| cpu7-isolate { | |
| qcom,cpu = <0x14>; | |
| phandle = <0x32>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| cpu0-isolate { | |
| qcom,cpu = <0x0d>; | |
| phandle = <0x1f>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| cpu2-isolate { | |
| qcom,cpu = <0x0f>; | |
| phandle = <0x23>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| cpu4-isolate { | |
| qcom,cpu = <0x11>; | |
| phandle = <0x29>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| cpu6-isolate { | |
| qcom,cpu = <0x13>; | |
| phandle = <0x2f>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| cpu1-isolate { | |
| qcom,cpu = <0x0e>; | |
| phandle = <0x21>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| }; | |
| qcom,limits-dcvs { | |
| isens_vref_0p8-supply = <0x17>; | |
| isens-vref-0p8-settings = <0xd6d80 0xd6d80 0x4e20>; | |
| isens_vref_1p8-supply = <0x18>; | |
| isens-vref-1p8-settings = <0x1b7740 0x1b7740 0x4e20>; | |
| compatible = "qcom,msm-hw-limits"; | |
| }; | |
| }; | |
| i2c@a80000 { | |
| pinctrl-names = "default\0sleep"; | |
| #address-cells = <0x01>; | |
| pinctrl-0 = <0x2a5>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| interrupts = <0x00 0x161 0x04>; | |
| clocks = <0x16 0x6a 0x16 0x86 0x16 0x87>; | |
| #size-cells = <0x00>; | |
| qcom,wrapper-core = <0x2a3>; | |
| dma-names = "tx\0rx"; | |
| compatible = "qcom,i2c-geni"; | |
| pinctrl-1 = <0x2a6>; | |
| status = "disabled"; | |
| reg = <0xa80000 0x4000>; | |
| phandle = <0x5b1>; | |
| dmas = <0x2a4 0x00 0x00 0x03 0x40 0x00 0x2a4 0x01 0x00 0x03 0x40 0x00>; | |
| }; | |
| qcom,gdsc@abf0d98 { | |
| clock-names = "ahb_clk"; | |
| qcom,msm-bus,name = "mvs1_gdsc_ahb"; | |
| parent-supply = <0x69>; | |
| qcom,support-hw-trigger; | |
| qcom,retain-regs; | |
| clocks = <0x16 0xcd>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| regulator-name = "mvs1_gdsc"; | |
| vdd_parent-supply = <0x69>; | |
| compatible = "qcom,gdsc"; | |
| reg = <0xabf0d98 0x04>; | |
| phandle = <0x330>; | |
| qcom,msm-bus,vectors-KBps = <0x01 0x254 0x00 0x00 0x01 0x254 0x00 0x01>; | |
| }; | |
| qcom,npucc@9980000 { | |
| #reset-cells = <0x01>; | |
| reg-names = "cc\0qdsp6ss\0qdsp6ss_pll"; | |
| #clock-cells = <0x01>; | |
| compatible = "qcom,npucc-kona-v2\0syscon"; | |
| reg = <0x9980000 0x10000 0x9800000 0x10000 0x9810000 0x10000>; | |
| phandle = <0x55>; | |
| vdd_cx-supply = <0x67>; | |
| }; | |
| tpdm@6c28000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-tpdm-dlct"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6c28000 0x1000>; | |
| phandle = <0x1fb>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x205>; | |
| phandle = <0x203>; | |
| }; | |
| }; | |
| }; | |
| funnel@6902000 { | |
| arm,primecell-periphid = <0xbb908>; | |
| qcom,proxy-regs = "vddcx\0vdd"; | |
| vddcx-supply = <0x17c>; | |
| clock-names = "apb_pclk\0rbbmtimer_clk\0mem_clk\0mem_iface_clk\0gmu_clk\0gpu_cc_ahb\0l3_vote"; | |
| reg-names = "funnel-base"; | |
| qcom,proxy-clks = "rbbmtimer_clk\0mem_clk\0mem_iface_clk\0gmu_clk\0gpu_cc_ahb\0l3_vote"; | |
| clocks = <0x49 0x00 0x6e 0x09 0x16 0x16 0x16 0x26 0x6e 0x03 0x6e 0x00 0x1ae 0x03>; | |
| coresight-name = "coresight-funnel-gpu"; | |
| vdd-supply = <0x1af>; | |
| compatible = "arm,primecell"; | |
| reg = <0x6902000 0x1000>; | |
| regulator-names = "vddcx\0vdd"; | |
| phandle = <0x4ea>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x1b0>; | |
| phandle = <0x1b4>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x00>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x1b1>; | |
| phandle = <0x1b2>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| i2c@988000 { | |
| pinctrl-names = "default\0sleep"; | |
| #address-cells = <0x01>; | |
| pinctrl-0 = <0x285>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| interrupts = <0x00 0x25b 0x04>; | |
| clocks = <0x16 0x5c 0x16 0x84 0x16 0x85>; | |
| #size-cells = <0x00>; | |
| qcom,wrapper-core = <0x274>; | |
| dma-names = "tx\0rx"; | |
| compatible = "qcom,i2c-geni"; | |
| pinctrl-1 = <0x286>; | |
| status = "disabled"; | |
| reg = <0x988000 0x4000>; | |
| phandle = <0x5a2>; | |
| dmas = <0x280 0x00 0x02 0x03 0x40 0x00 0x280 0x01 0x02 0x03 0x40 0x00>; | |
| }; | |
| qcom,smp2p_interrupt_rdbg_5_in { | |
| interrupts-extended = <0x252 0x00 0x00>; | |
| compatible = "qcom,smp2p-interrupt-rdbg-5-in"; | |
| interrupt-names = "rdbg-smp2p-in"; | |
| }; | |
| ipcc-self-ping-slpi { | |
| interrupts-extended = <0x8a 0x04 0x03 0x04>; | |
| compatible = "qcom,ipcc-self-ping"; | |
| phandle = <0x611>; | |
| mboxes = <0x8a 0x04 0x03>; | |
| }; | |
| usb_nop_phy { | |
| compatible = "usb-nop-xceiv"; | |
| phandle = <0x4db>; | |
| }; | |
| cti@7420000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| cpu = <0x11>; | |
| coresight-name = "coresight-cti-cpu4"; | |
| compatible = "arm,primecell"; | |
| reg = <0x7420000 0x1000>; | |
| phandle = <0x52c>; | |
| }; | |
| qcom,msm-dai-tdm-quin-rx { | |
| qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
| qcom,msm-cpudai-tdm-data-out = <0x00>; | |
| qcom,msm-cpudai-tdm-data-delay = <0x01>; | |
| qcom,msm-cpudai-tdm-group-port-id = <0x9040>; | |
| qcom,msm-cpudai-tdm-group-num-ports = <0x01>; | |
| qcom,msm-cpudai-tdm-invert-sync = <0x01>; | |
| compatible = "qcom,msm-dai-tdm"; | |
| qcom,msm-cpudai-tdm-group-id = <0x9140>; | |
| phandle = <0x5ee>; | |
| qcom,msm-cpudai-tdm-sync-src = <0x01>; | |
| qcom,msm-cpudai-tdm-clk-internal = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-mode = <0x01>; | |
| qcom,msm-dai-q6-tdm-quin-rx-0 { | |
| qcom,msm-cpudai-tdm-dev-id = <0x9040>; | |
| qcom,msm-cpudai-tdm-data-align = <0x00>; | |
| compatible = "qcom,msm-dai-q6-tdm"; | |
| phandle = <0x311>; | |
| }; | |
| }; | |
| qcom,gpucc@3d90000 { | |
| #reset-cells = <0x01>; | |
| reg-names = "cc_base"; | |
| #clock-cells = <0x01>; | |
| vdd_mx-supply = <0x6a>; | |
| compatible = "qcom,gpucc-kona\0syscon"; | |
| reg = <0x3d90000 0x9000>; | |
| phandle = <0x6e>; | |
| vdd_cx-supply = <0x67>; | |
| }; | |
| qcom,ddr-stats@c3f0000 { | |
| reg-names = "phys_addr_base\0offset_addr"; | |
| compatible = "qcom,ddr-stats"; | |
| reg = <0xc300000 0x1000 0xc3f001c 0x04>; | |
| }; | |
| qcom,qup_uart@a90000 { | |
| pinctrl-names = "default\0sleep"; | |
| pinctrl-0 = <0x2a1>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| reg-names = "se_phys"; | |
| interrupts = <0x00 0x165 0x04>; | |
| clocks = <0x16 0x72 0x16 0x86 0x16 0x87>; | |
| qcom,change-sampling-rate; | |
| qcom,wrapper-core = <0x2a3>; | |
| compatible = "qcom,msm-geni-console"; | |
| pinctrl-1 = <0x2a2>; | |
| status = "ok"; | |
| reg = <0xa90000 0x4000>; | |
| phandle = <0x5b0>; | |
| }; | |
| apps_iommu_coherent_test_device { | |
| iommus = <0x47 0x23 0x00>; | |
| dma-coherent; | |
| compatible = "iommu-debug-test"; | |
| qcom,iommu-dma = "disabled"; | |
| }; | |
| cti@6831000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti-iris_dl_cti"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6831000 0x1000>; | |
| phandle = <0x532>; | |
| }; | |
| qcom,camera-flash0 { | |
| cell-index = <0x00>; | |
| torch-source = <0x648 0x649>; | |
| switch-source = <0x64a>; | |
| compatible = "qcom,camera-flash"; | |
| status = "ok"; | |
| phandle = <0x64c>; | |
| flash-source = <0x646 0x647>; | |
| }; | |
| qcom,gdsc@177004 { | |
| qcom,retain-regs; | |
| regulator-name = "ufs_phy_gdsc"; | |
| compatible = "qcom,gdsc"; | |
| reg = <0x177004 0x04>; | |
| phandle = <0x374>; | |
| }; | |
| qcom,msm-stub-codec { | |
| compatible = "qcom,msm-stub-codec"; | |
| phandle = <0x5cd>; | |
| }; | |
| qcom,smp2p_interrupt_rdbg_2_in { | |
| interrupts-extended = <0x250 0x00 0x00>; | |
| compatible = "qcom,smp2p-interrupt-rdbg-2-in"; | |
| interrupt-names = "rdbg-smp2p-in"; | |
| }; | |
| qcom,qup_uart@998000 { | |
| pinctrl-names = "default\0active\0sleep"; | |
| pinctrl-2 = <0x27d 0x27e 0x27f>; | |
| pinctrl-0 = <0x27a 0x27b 0x27c>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| reg-names = "se_phys"; | |
| clocks = <0x16 0x64 0x16 0x84 0x16 0x85>; | |
| qcom,wrapper-core = <0x274>; | |
| interrupts-extended = <0x01 0x00 0x25f 0x04 0x66 0x13 0x00>; | |
| compatible = "qcom,msm-geni-serial-hs"; | |
| pinctrl-1 = <0x27d 0x27e 0x27f>; | |
| status = "ok"; | |
| reg = <0x998000 0x4000>; | |
| phandle = <0x59f>; | |
| qcom,wakeup-byte = <0xfd>; | |
| }; | |
| qcom,avtimer@39f0000 { | |
| reg-names = "avtimer_lsb_addr\0avtimer_msb_addr"; | |
| qcom,clk-div = <0xc0>; | |
| compatible = "qcom,avtimer"; | |
| qcom,clk-mult = <0x0a>; | |
| reg = <0x39f000c 0x04 0x39f0010 0x04>; | |
| }; | |
| kgsl-smmu@3da0000 { | |
| #global-interrupts = <0x02>; | |
| #address-cells = <0x01>; | |
| clock-names = "gcc_gpu_memnoc_gfx\0gcc_gpu_snoc_dvm_gfx\0gpu_cc_ahb"; | |
| reg-names = "base\0tcu-base"; | |
| interrupts = <0x00 0x2a0 0x04 0x00 0x2a1 0x04 0x00 0x2a6 0x04 0x00 0x2a7 0x04 0x00 0x2a8 0x04 0x00 0x2a9 0x04 0x00 0x2aa 0x04 0x00 0x2ab 0x04 0x00 0x2ac 0x04 0x00 0x2ad 0x04>; | |
| clocks = <0x16 0x26 0x16 0x27 0x6e 0x00>; | |
| qcom,actlr = <0x02 0x400 0x32b 0x04 0x400 0x32b 0x05 0x400 0x32b 0x07 0x400 0x32b 0x00 0x401 0x32b>; | |
| #size-cells = <0x01>; | |
| qcom,skip-init; | |
| qcom,regulator-names = "vdd"; | |
| vdd-supply = <0x17c>; | |
| qcom,use-3-lvl-tables; | |
| #iommu-cells = <0x02>; | |
| compatible = "qcom,qsmmu-v500"; | |
| ranges; | |
| reg = <0x3da0000 0x10000 0x3dc2000 0x20>; | |
| phandle = <0x181>; | |
| qcom,msm-bus,vectors-KBps = <0x9b 0x200 0x00 0x00 0x9b 0x200 0x00 0x3e8>; | |
| qcom,no-dynamic-asid; | |
| gfx_0_tbu@3dc5000 { | |
| reg-names = "base\0status-reg"; | |
| qcom,stream-id-range = <0x00 0x400>; | |
| compatible = "qcom,qsmmuv500-tbu"; | |
| reg = <0x3dc5000 0x1000 0x3dc2200 0x08>; | |
| phandle = <0x3e4>; | |
| }; | |
| gfx_1_tbu@3dc9000 { | |
| reg-names = "base\0status-reg"; | |
| qcom,stream-id-range = <0x400 0x400>; | |
| compatible = "qcom,qsmmuv500-tbu"; | |
| reg = <0x3dc9000 0x1000 0x3dc2208 0x08>; | |
| phandle = <0x3e5>; | |
| }; | |
| }; | |
| qcom,msm-eud@ff0000 { | |
| clock-names = "eud_ahb2phy_clk"; | |
| reg-names = "eud_base\0eud_mode_mgr2"; | |
| interrupts = <0x0b 0x04>; | |
| clocks = <0x16 0x2a>; | |
| interrupt-parent = <0x76>; | |
| qcom,secure-eud-en; | |
| compatible = "qcom,msm-eud"; | |
| status = "ok"; | |
| interrupt-names = "eud_irq"; | |
| reg = <0x88e0000 0x2000 0x88e2000 0x1000>; | |
| phandle = <0x39e>; | |
| qcom,eud-clock-vote-req; | |
| }; | |
| qcom,cci@ac50000 { | |
| pinctrl-names = "cam_default\0cam_suspend"; | |
| pinctrl-0 = <0x258 0x259>; | |
| clock-names = "cci_1_clk_src\0cci_1_clk"; | |
| reg-names = "cci"; | |
| reg-cam-base = <0x50000>; | |
| cell-index = <0x01>; | |
| gpio-req-tbl-num = <0x00 0x01 0x02 0x03>; | |
| interrupts = <0x00 0x10f 0x01>; | |
| clocks = <0x6d 0x0b 0x6d 0x0a>; | |
| gdscr-supply = <0x253>; | |
| gpio-req-tbl-label = "CCI_I2C_DATA2\0CCI_I2C_CLK2\0CCI_I2C_DATA3\0CCI_I2C_CLK3"; | |
| clock-cntl-level = "lowsvs"; | |
| compatible = "qcom,cci"; | |
| src-clock-name = "cci_1_clk_src"; | |
| pinctrl-1 = <0x25a 0x25b>; | |
| status = "ok"; | |
| interrupt-names = "cci"; | |
| reg = <0xac50000 0x1000>; | |
| regulator-names = "gdscr"; | |
| phandle = <0x568>; | |
| clock-rates = <0x23c3460 0x00>; | |
| gpio-req-tbl-flags = <0x01 0x01 0x01 0x01>; | |
| gpios = <0x66 0x69 0x00 0x66 0x6a 0x00 0x66 0x6b 0x00 0x66 0x6c 0x00>; | |
| qcom,i2c_custom_mode { | |
| hw-tsu-sto = <0x28>; | |
| cci-clk-src = <0x23c3460>; | |
| hw-tsp = <0x03>; | |
| hw-trdhld = <0x06>; | |
| hw-thigh = <0x26>; | |
| hw-tlow = <0x38>; | |
| status = "ok"; | |
| hw-thd-dat = <0x16>; | |
| hw-tsu-sta = <0x28>; | |
| hw-scl-stretch-en = <0x01>; | |
| phandle = <0x56b>; | |
| hw-tbuf = <0x3e>; | |
| hw-thd-sta = <0x23>; | |
| }; | |
| qcom,eeprom1 { | |
| rgltr-max-voltage = <0x1b7740 0x2dc6c0 0x124f80 0x00>; | |
| pinctrl-names = "cam_default\0cam_suspend"; | |
| pinctrl-0 = <0x46d 0x47b>; | |
| clock-names = "cam_clk"; | |
| cell-index = <0x01>; | |
| gpio-req-tbl-num = <0x00 0x01>; | |
| clocks = <0x6d 0x4d>; | |
| rgltr-load-current = <0x00 0x13880 0x101d00 0x00>; | |
| cam_vio-supply = <0x393>; | |
| rgltr-cntrl-support; | |
| cam_vana-supply = <0x392>; | |
| gpio-req-tbl-label = "CAMIF_MCLK2\0CAM_RESET2"; | |
| gpio-reset = <0x01>; | |
| clock-cntl-level = "turbo"; | |
| cam_vdig-supply = <0x38f>; | |
| sensor-mode = <0x00>; | |
| cci-master = <0x00>; | |
| gpio-no-mux = <0x00>; | |
| compatible = "qcom,eeprom"; | |
| rgltr-min-voltage = <0x1b7740 0x2ab980 0x124f80 0x00>; | |
| pinctrl-1 = <0x46e 0x47c>; | |
| status = "ok"; | |
| sensor-position = <0x01>; | |
| regulator-names = "cam_vio\0cam_vana\0cam_vdig\0cam_clk"; | |
| phandle = <0x64f>; | |
| cam_clk-supply = <0x253>; | |
| clock-rates = <0x16e3600>; | |
| gpio-req-tbl-flags = <0x01 0x00>; | |
| gpios = <0x66 0x60 0x00 0x66 0x4e 0x00>; | |
| }; | |
| qcom,cam-sensor2 { | |
| rgltr-max-voltage = <0x1b7740 0x2ab980 0x124f80 0x00>; | |
| pinctrl-names = "cam_default\0cam_suspend"; | |
| eeprom-src = <0x650>; | |
| pwm-switch; | |
| pinctrl-0 = <0x46f 0x47d>; | |
| clock-names = "cam_clk"; | |
| cell-index = <0x02>; | |
| gpio-req-tbl-num = <0x00 0x01>; | |
| sensor-position-yaw = <0xb4>; | |
| clocks = <0x6d 0x4f>; | |
| rgltr-load-current = <0x00 0x13880 0x124f80 0x00>; | |
| cam_vio-supply = <0x393>; | |
| rgltr-cntrl-support; | |
| cam_vana-supply = <0x392>; | |
| gpio-req-tbl-label = "CAMIF_MCLK3\0CAM_RESET3"; | |
| gpio-reset = <0x01>; | |
| csiphy-sd-index = <0x03>; | |
| clock-cntl-level = "turbo"; | |
| cam_vdig-supply = <0x38e>; | |
| sensor-mode = <0x00>; | |
| cci-master = <0x01>; | |
| gpio-no-mux = <0x00>; | |
| compatible = "qcom,cam-sensor"; | |
| rgltr-min-voltage = <0x1b7740 0x2ab980 0x124f80 0x00>; | |
| led-flash-src = <0x651>; | |
| sensor-position-roll = <0x5a>; | |
| pinctrl-1 = <0x470 0x47e>; | |
| status = "ok"; | |
| reg = <0x03>; | |
| regulator-names = "cam_vio\0cam_vana\0cam_vdig\0cam_clk"; | |
| sensor-position-pitch = <0x00>; | |
| cam_clk-supply = <0x253>; | |
| clock-rates = <0x16e3600>; | |
| gpio-req-tbl-flags = <0x01 0x00>; | |
| gpios = <0x66 0x61 0x00 0x66 0x6d 0x00>; | |
| }; | |
| qcom,i2c_standard_mode { | |
| hw-tsu-sto = <0xcc>; | |
| cci-clk-src = <0x23c3460>; | |
| hw-tsp = <0x03>; | |
| hw-trdhld = <0x06>; | |
| hw-thigh = <0xc9>; | |
| hw-tlow = <0xae>; | |
| status = "ok"; | |
| hw-thd-dat = <0x16>; | |
| hw-tsu-sta = <0xe7>; | |
| hw-scl-stretch-en = <0x00>; | |
| phandle = <0x569>; | |
| hw-tbuf = <0xe3>; | |
| hw-thd-sta = <0xa2>; | |
| }; | |
| qcom,eeprom2 { | |
| rgltr-max-voltage = <0x1b7740 0x2ab980 0x124f80 0x00>; | |
| pinctrl-names = "cam_default\0cam_suspend"; | |
| pinctrl-0 = <0x46f 0x47d>; | |
| clock-names = "cam_clk"; | |
| cell-index = <0x02>; | |
| gpio-req-tbl-num = <0x00 0x01>; | |
| clocks = <0x6d 0x4f>; | |
| rgltr-load-current = <0x00 0x13880 0x124f80 0x00>; | |
| cam_vio-supply = <0x393>; | |
| rgltr-cntrl-support; | |
| cam_vana-supply = <0x392>; | |
| gpio-req-tbl-label = "CAMIF_MCLK3\0CAM_RESET3"; | |
| gpio-reset = <0x01>; | |
| clock-cntl-level = "turbo"; | |
| cam_vdig-supply = <0x38e>; | |
| sensor-mode = <0x00>; | |
| cci-master = <0x01>; | |
| gpio-no-mux = <0x00>; | |
| compatible = "qcom,eeprom"; | |
| rgltr-min-voltage = <0x1b7740 0x2ab980 0x124f80 0x00>; | |
| pinctrl-1 = <0x470 0x47e>; | |
| status = "ok"; | |
| regulator-names = "cam_vio\0cam_vana\0cam_vdig\0cam_clk"; | |
| phandle = <0x650>; | |
| cam_clk-supply = <0x253>; | |
| clock-rates = <0x16e3600>; | |
| gpio-req-tbl-flags = <0x01 0x00>; | |
| gpios = <0x66 0x61 0x00 0x66 0x6d 0x00>; | |
| }; | |
| qcom,i2c_fast_plus_mode { | |
| hw-tsu-sto = <0x11>; | |
| cci-clk-src = <0x23c3460>; | |
| hw-tsp = <0x03>; | |
| hw-trdhld = <0x03>; | |
| hw-thigh = <0x10>; | |
| hw-tlow = <0x16>; | |
| status = "ok"; | |
| hw-thd-dat = <0x10>; | |
| hw-tsu-sta = <0x12>; | |
| hw-scl-stretch-en = <0x00>; | |
| phandle = <0x56c>; | |
| hw-tbuf = <0x18>; | |
| hw-thd-sta = <0x0f>; | |
| }; | |
| qcom,cam-sensor1 { | |
| rgltr-max-voltage = <0x1b7740 0x2dc6c0 0x124f80 0x00>; | |
| pinctrl-names = "cam_default\0cam_suspend"; | |
| eeprom-src = <0x64f>; | |
| pwm-switch; | |
| pinctrl-0 = <0x46d 0x47b>; | |
| clock-names = "cam_clk"; | |
| cell-index = <0x01>; | |
| gpio-req-tbl-num = <0x00 0x01>; | |
| sensor-position-yaw = <0x00>; | |
| clocks = <0x6d 0x4d>; | |
| rgltr-load-current = <0x00 0x13880 0x19a28 0x00>; | |
| cam_vio-supply = <0x393>; | |
| rgltr-cntrl-support; | |
| cam_vana-supply = <0x392>; | |
| gpio-req-tbl-label = "CAMIF_MCLK2\0CAM_RESET2"; | |
| gpio-reset = <0x01>; | |
| csiphy-sd-index = <0x02>; | |
| clock-cntl-level = "turbo"; | |
| cam_vdig-supply = <0x38f>; | |
| sensor-mode = <0x00>; | |
| cci-master = <0x00>; | |
| gpio-no-mux = <0x00>; | |
| compatible = "qcom,cam-sensor"; | |
| rgltr-min-voltage = <0x1b7740 0x2ab980 0x124f80 0x00>; | |
| sensor-position-roll = <0x10e>; | |
| pinctrl-1 = <0x46e 0x47c>; | |
| status = "ok"; | |
| regulator-names = "cam_vio\0cam_vana\0cam_vdig\0cam_clk"; | |
| sensor-position-pitch = <0x00>; | |
| cam_clk-supply = <0x253>; | |
| clock-rates = <0x16e3600>; | |
| gpio-req-tbl-flags = <0x01 0x00>; | |
| gpios = <0x66 0x60 0x00 0x66 0x4e 0x00>; | |
| }; | |
| qcom,i2c_fast_mode { | |
| hw-tsu-sto = <0x28>; | |
| cci-clk-src = <0x23c3460>; | |
| hw-tsp = <0x03>; | |
| hw-trdhld = <0x06>; | |
| hw-thigh = <0x26>; | |
| hw-tlow = <0x38>; | |
| status = "ok"; | |
| hw-thd-dat = <0x16>; | |
| hw-tsu-sta = <0x28>; | |
| hw-scl-stretch-en = <0x00>; | |
| phandle = <0x56a>; | |
| hw-tbuf = <0x3e>; | |
| hw-thd-sta = <0x23>; | |
| }; | |
| }; | |
| dsi_panel_pwr_supply_lab_ibb { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| phandle = <0x6e6>; | |
| qcom,panel-supply-entry@1 { | |
| qcom,supply-disable-load = <0x64>; | |
| qcom,supply-enable-load = <0x186a0>; | |
| qcom,supply-name = "lab"; | |
| qcom,supply-max-voltage = <0x5b8d80>; | |
| reg = <0x01>; | |
| qcom,supply-min-voltage = <0x4630c0>; | |
| }; | |
| qcom,panel-supply-entry@2 { | |
| qcom,supply-disable-load = <0x64>; | |
| qcom,supply-enable-load = <0x186a0>; | |
| qcom,supply-post-on-sleep = <0x14>; | |
| qcom,supply-name = "ibb"; | |
| qcom,supply-max-voltage = <0x5b8d80>; | |
| reg = <0x02>; | |
| qcom,supply-min-voltage = <0x4630c0>; | |
| }; | |
| qcom,panel-supply-entry@0 { | |
| qcom,supply-disable-load = <0x50>; | |
| qcom,supply-enable-load = <0xf230>; | |
| qcom,supply-post-on-sleep = <0x14>; | |
| qcom,supply-name = "vddio"; | |
| qcom,supply-max-voltage = <0x1b7740>; | |
| reg = <0x00>; | |
| qcom,supply-min-voltage = <0x1b7740>; | |
| }; | |
| }; | |
| dummy_sink { | |
| coresight-name = "coresight-eud"; | |
| qcom,dummy-sink; | |
| compatible = "qcom,coresight-dummy"; | |
| phandle = <0x4df>; | |
| port { | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x190>; | |
| phandle = <0x18d>; | |
| }; | |
| }; | |
| }; | |
| qcom,csiphy@ac74000 { | |
| clock-names = "cphy_rx_clk_src\0csiphy5_clk\0csi5phytimer_clk_src\0csi5phytimer_clk"; | |
| reg-names = "csiphy"; | |
| reg-cam-base = "\0\a@"; | |
| csi-vdd-voltage = <0x124f80>; | |
| cell-index = <0x05>; | |
| interrupts = <0x00 0x59 0x01>; | |
| clocks = <0x6d 0x0e 0x6d 0x20 0x6d 0x1a 0x6d 0x19>; | |
| gdscr-supply = <0x253>; | |
| clock-cntl-level = "turbo"; | |
| compatible = "qcom,csiphy-v1.2.1\0qcom,csiphy"; | |
| src-clock-name = "csi5phytimer_clk_src"; | |
| mipi-csi-vdd-supply = <0x7d>; | |
| status = "ok"; | |
| interrupt-names = "csiphy"; | |
| reg = <0xac74000 0x2000>; | |
| regulator-names = "gdscr\0refgen"; | |
| phandle = <0x562>; | |
| refgen-supply = <0xb4>; | |
| clock-rates = <0x17d78400 0x00 0x11e1a300 0x00>; | |
| }; | |
| cti@6019000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti9"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6019000 0x1000>; | |
| phandle = <0x521>; | |
| }; | |
| hsphy@88e4000 { | |
| qcom,vdd-voltage-level = <0x00 0xd6d80 0xd6d80>; | |
| clock-names = "ref_clk_src"; | |
| reg-names = "hsusb_phy_base"; | |
| resets = <0x16 0x1c>; | |
| qcom,param-override-seq = <0x43 0x70>; | |
| clocks = <0x15 0x00>; | |
| vdd-supply = <0x7c>; | |
| compatible = "qcom,usb-hsphy-snps-femto"; | |
| reg = <0x88e4000 0x110>; | |
| phandle = <0x189>; | |
| reset-names = "phy_reset"; | |
| vdda33-supply = <0x186>; | |
| vdda18-supply = <0x185>; | |
| }; | |
| dcc_v2@1023000 { | |
| dcc-ram-offset = <0x1a000>; | |
| reg-names = "dcc-base\0dcc-ram-base"; | |
| compatible = "qcom,dcc-v2"; | |
| reg = <0x1023000 0x1000 0x103a000 0x6000>; | |
| phandle = <0x36e>; | |
| link_list1 { | |
| qcom,data-sink = "sram"; | |
| qcom,link-list = <0x00 0x18220d14 0x03 0x00 0x00 0x18220d30 0x04 0x00 0x00 0x18220d44 0x04 0x00 0x00 0x18220d58 0x04 0x00 0x00 0x18220fb4 0x03 0x00 0x00 0x18220fd0 0x04 0x00 0x00 0x18220fe4 0x04 0x00 0x00 0x18220ff8 0x04 0x00 0x00 0x18220d04 0x01 0x00 0x00 0x18220d00 0x01 0x00 0x00 0x18000024 0x01 0x00 0x00 0x18000040 0x04 0x00 0x00 0x18010024 0x01 0x00 0x00 0x18010040 0x04 0x00 0x00 0x18020024 0x01 0x00 0x00 0x18020040 0x04 0x00 0x00 0x18030024 0x01 0x00 0x00 0x18030040 0x04 0x00 0x00 0x18040024 0x01 0x00 0x00 0x18040040 0x04 0x00 0x00 0x18050024 0x01 0x00 0x00 0x18050040 0x04 0x00 0x00 0x18060024 0x01 0x00 0x00 0x18060040 0x04 0x00 0x00 0x18070024 0x01 0x00 0x00 0x18070040 0x04 0x00 0x00 0x18080104 0x01 0x00 0x00 0x18080168 0x01 0x00 0x00 0x18080198 0x01 0x00 0x00 0x18080128 0x01 0x00 0x00 0x18080024 0x01 0x00 0x00 0x18080040 0x03 0x00 0x00 0x18200400 0x03 0x00 0x00 0xb201020 0x02 0x00 0x00 0xb204520 0x01 0x00 0x00 0x1800005c 0x01 0x00 0x00 0x1801005c 0x01 0x00 0x00 0x1802005c 0x01 0x00 0x00 0x1803005c 0x01 0x00 0x00 0x1804005c 0x01 0x00 0x00 0x1805005c 0x01 0x00 0x00 0x1806005c 0x01 0x00 0x00 0x1807005c 0x01 0x00 0x00 0x18101908 0x01 0x00 0x00 0x18101c18 0x01 0x00 0x00 0x18390810 0x01 0x00 0x00 0x18390c50 0x01 0x00 0x00 0x18390814 0x01 0x00 0x00 0x18390c54 0x01 0x00 0x00 0x18390818 0x01 0x00 0x00 0x18390c58 0x01 0x00 0x00 0x18393a84 0x02 0x00 0x00 0x18100908 0x01 0x00 0x00 0x18100c18 0x01 0x00 0x00 0x183a0810 0x01 0x00 0x00 0x183a0c50 0x01 0x00 0x00 0x183a0814 0x01 0x00 0x00 0x183a0c54 0x01 0x00 0x00 0x183a0818 0x01 0x00 0x00 0x183a0c58 0x01 0x00 0x00 0x183a3a84 0x02 0x00 0x00 0x18393500 0x01 0x00 0x00 0x18393580 0x01 0x00 0x00 0x183a3500 0x01 0x00 0x00 0x183a3580 0x01 0x00 0x00 0x18282000 0x04 0x00 0x00 0x18282028 0x01 0x00 0x00 0x18282038 0x01 0x00 0x00 0x18282080 0x05 0x00 0x00 0x18286000 0x04 0x00 0x00 0x18286028 0x01 0x00 0x00 0x18286038 0x01 0x00 0x00 0x18286080 0x05 0x00 0x00 0xc201244 0x01 0x00 0x00 0xc202244 0x01 0x00 0x00 0x18300000 0x01 0x00 0x00 0x1829208c 0x01 0x00 0x00 0x18292098 0x01 0x00 0x00 0x18292098 0x01 0x00 0x00 0x1829608c 0x01 0x00 0x00 0x18296098 0x01 0x00 0x00 0x18296098 0x01 0x00 0x00 0x91a9020 0x01 0x00 0x03 0x05 0x01 0x00 0x00 0x9102008 0x01 0x00 0x03 0x02 0x02 0x00 0x00 0x9142008 0x01 0x00 0x03 0x02 0x02 0x00 0x00 0x9102408 0x01 0x00 0x03 0x02 0x02 0x00 0x00 0x9142408 0x01 0x00 0x03 0x02 0x02 0x00 0x00 0x9103808 0x01 0x00 0x02 0x03 0x00 0x00 0x00 0x9103810 0x01 0x00 0x00 0x9103814 0x01 0x00 0x02 0x01 0x00 0x00 0x00 0x9103888 0x01 0x00 0x02 0x02 0x00 0x00 0x00 0x9103890 0x01 0x00 0x00 0x9103894 0x01 0x00 0x02 0x01 0x00 0x00 0x00 0x9143808 0x01 0x00 0x02 0x03 0x00 0x00 0x00 0x9143810 0x01 0x00 0x00 0x9143814 0x01 0x00 0x02 0x01 0x00 0x00 0x00 0x9143888 0x01 0x00 0x02 0x02 0x00 0x00 0x00 0x9143890 0x01 0x00 0x00 0x9143894 0x01 0x00 0x02 0x01 0x00 0x00 0x00 0x9182808 0x01 0x00 0x02 0x02 0x00 0x00 0x00 0x9182810 0x01 0x00 0x00 0x9182814 0x01 0x00 0x02 0x01 0x00 0x00 0x00 0x9182888 0x01 0x00 0x02 0x03 0x00 0x00 0x00 0x9182890 0x01 0x00 0x00 0x9182894 0x01 0x00 0x02 0x01 0x00 0x00 0x00 0x9103008 0x01 0x00 0x00 0x910300c 0x01 0x00 0x01 0x9103028 0x01 0x01 0x02 0x29 0x00 0x00 0x00 0x9103010 0x01 0x00 0x00 0x9103014 0x01 0x00 0x02 0x01 0x00 0x00 0x00 0x9103408 0x01 0x00 0x00 0x910340c 0x01 0x00 0x01 0x9103428 0x01 0x01 0x02 0x29 0x00 0x00 0x00 0x9103410 0x01 0x00 0x00 0x9103414 0x01 0x00 0x02 0x01 0x00 0x00 0x00 0x9143008 0x01 0x00 0x00 0x914300c 0x01 0x00 0x01 0x9143028 0x01 0x01 0x02 0x29 0x00 0x00 0x00 0x9143010 0x01 0x00 0x00 0x9143014 0x01 0x00 0x02 0x01 0x00 0x00 0x00 0x9143408 0x01 0x00 0x00 0x914340c 0x01 0x00 0x01 0x9143428 0x01 0x01 0x02 0x29 0x00 0x00 0x00 0x9143410 0x01 0x00 0x00 0x9143414 0x01 0x00 0x02 0x01 0x00 0x00 0x00 0x9182008 0x01 0x00 0x00 0x918200c 0x01 0x00 0x01 0x9182028 0x01 0x01 0x02 0x0b 0x00 0x00 0x00 0x9182010 0x01 0x00 0x00 0x9182014 0x01 0x00 0x02 0x01 0x00 0x00 0x00 0x9182408 0x01 0x00 0x00 0x918240c 0x01 0x00 0x01 0x9182428 0x01 0x01 0x02 0x0b 0x00 0x00 0x00 0x9182410 0x01 0x00 0x00 0x9182414 0x01 0x00 0x02 0x01 0x00 0x00>; | |
| qcom,curr-link-list = <0x03>; | |
| }; | |
| link_list2 { | |
| qcom,data-sink = "sram"; | |
| qcom,link-list = <0x00 0x9050078 0x01 0x00 0x00 0x9050110 0x08 0x00 0x00 0x9080058 0x02 0x00 0x00 0x90800c8 0x01 0x00 0x00 0x90800d4 0x01 0x00 0x00 0x90800e0 0x01 0x00 0x00 0x90800ec 0x01 0x00 0x00 0x90800f8 0x01 0x00 0x00 0x908401c 0x01 0x00 0x00 0x908403c 0x01 0x00 0x00 0x908404c 0x02 0x00 0x00 0x90840d4 0x01 0x00 0x00 0x9084204 0x01 0x00 0x00 0x908420c 0x01 0x00 0x00 0x9084250 0x02 0x00 0x00 0x9084260 0x03 0x00 0x00 0x9084280 0x01 0x00 0x00 0x90ba280 0x01 0x00 0x00 0x90ba288 0x07 0x00 0x00 0x9258610 0x04 0x00 0x00 0x92d8610 0x04 0x00 0x00 0x9358610 0x04 0x00 0x00 0x93d8610 0x04 0x00 0x00 0x9220344 0x08 0x00 0x00 0x9220370 0x06 0x00 0x00 0x9220480 0x01 0x00 0x00 0x9222400 0x01 0x00 0x00 0x922240c 0x01 0x00 0x00 0x9223214 0x02 0x00 0x00 0x9223220 0x03 0x00 0x00 0x9223308 0x01 0x00 0x00 0x9223318 0x01 0x00 0x00 0x9232100 0x01 0x00 0x00 0x9236040 0x06 0x00 0x00 0x92360b0 0x01 0x00 0x00 0x923e030 0x02 0x00 0x00 0x9241000 0x01 0x00 0x00 0x9242028 0x01 0x00 0x00 0x9242044 0x03 0x00 0x00 0x9242070 0x01 0x00 0x00 0x9248030 0x01 0x00 0x00 0x9248048 0x08 0x00 0x00 0x92a0344 0x08 0x00 0x00 0x92a0370 0x06 0x00 0x00 0x92a0480 0x01 0x00 0x00 0x92a2400 0x01 0x00 0x00 0x92a240c 0x01 0x00 0x00 0x92a3214 0x02 0x00 0x00 0x92a3220 0x03 0x00 0x00 0x92a3308 0x01 0x00 0x00 0x92a3318 0x01 0x00 0x00 0x92b2100 0x01 0x00 0x00 0x92b6040 0x06 0x00 0x00 0x92b60b0 0x01 0x00 0x00 0x92be030 0x02 0x00 0x00 0x92c1000 0x01 0x00 0x00 0x92c2028 0x01 0x00 0x00 0x92c2044 0x03 0x00 0x00 0x92c2070 0x01 0x00 0x00 0x92c8030 0x01 0x00 0x00 0x92c8048 0x08 0x00 0x00 0x9320344 0x08 0x00 0x00 0x9320370 0x06 0x00 0x00 0x9320480 0x01 0x00 0x00 0x9322400 0x01 0x00 0x00 0x932240c 0x01 0x00 0x00 0x9323214 0x02 0x00 0x00 0x9323220 0x03 0x00 0x00 0x9323308 0x01 0x00 0x00 0x9323318 0x01 0x00 0x00 0x9332100 0x01 0x00 0x00 0x9336040 0x06 0x00 0x00 0x93360b0 0x01 0x00 0x00 0x933e030 0x02 0x00 0x00 0x9341000 0x01 0x00 0x00 0x9342028 0x01 0x00 0x00 0x9342044 0x03 0x00 0x00 0x9342070 0x01 0x00 0x00 0x9348030 0x01 0x00 0x00 0x9348048 0x08 0x00 0x00 0x93a0344 0x08 0x00 0x00 0x93a0370 0x06 0x00 0x00 0x93a0480 0x01 0x00 0x00 0x93a2400 0x01 0x00 0x00 0x93a240c 0x01 0x00 0x00 0x93a3214 0x02 0x00 0x00 0x93a3220 0x03 0x00 0x00 0x93a3308 0x01 0x00 0x00 0x93a3318 0x01 0x00 0x00 0x93b2100 0x01 0x00 0x00 0x93b6040 0x06 0x00 0x00 0x93b60b0 0x01 0x00 0x00 0x93be030 0x02 0x00 0x00 0x93c1000 0x01 0x00 0x00 0x93c2028 0x01 0x00 0x00 0x93c2044 0x03 0x00 0x00 0x93c2070 0x01 0x00 0x00 0x93c8030 0x01 0x00 0x00 0x93c8048 0x08 0x00 0x00 0x9270080 0x01 0x00 0x00 0x9270400 0x01 0x00 0x00 0x9270410 0x06 0x00 0x00 0x9270430 0x01 0x00 0x00 0x9270440 0x01 0x00 0x00 0x9270448 0x01 0x00 0x00 0x92704a0 0x01 0x00 0x00 0x92704b0 0x01 0x00 0x00 0x92704b8 0x02 0x00 0x00 0x92704d0 0x01 0x00 0x00 0x9271400 0x01 0x00 0x00 0x92753b0 0x01 0x00 0x00 0x9275c1c 0x01 0x00 0x00 0x9275c2c 0x01 0x00 0x00 0x9275c38 0x01 0x00 0x00 0x9276418 0x02 0x00 0x00 0x92f0080 0x01 0x00 0x00 0x92f0400 0x01 0x00 0x00 0x92f0410 0x06 0x00 0x00 0x92f0430 0x01 0x00 0x00 0x92f0440 0x01 0x00 0x00 0x92f0448 0x01 0x00 0x00 0x92f04a0 0x01 0x00 0x00 0x92f04b0 0x01 0x00 0x00 0x92f04b8 0x02 0x00 0x00 0x92f04d0 0x01 0x00 0x00 0x92f1400 0x01 0x00 0x00 0x92f53b0 0x01 0x00 0x00 0x92f5c1c 0x01 0x00 0x00 0x92f5c2c 0x01 0x00 0x00 0x92f5c38 0x01 0x00 0x00 0x92f6418 0x02 0x00 0x00 0x9370080 0x01 0x00 0x00 0x9370400 0x01 0x00 0x00 0x9370410 0x06 0x00 0x00 0x9370430 0x01 0x00 0x00 0x9370440 0x01 0x00 0x00 0x9370448 0x01 0x00 0x00 0x93704a0 0x01 0x00 0x00 0x93704b0 0x01 0x00 0x00 0x93704b8 0x02 0x00 0x00 0x93704d0 0x01 0x00 0x00 0x9371400 0x01 0x00 0x00 0x93753b0 0x01 0x00 0x00 0x9375c1c 0x01 0x00 0x00 0x9375c2c 0x01 0x00 0x00 0x9375c38 0x01 0x00 0x00 0x9376418 0x02 0x00 0x00 0x93f0080 0x01 0x00 0x00 0x93f0400 0x01 0x00 0x00 0x93f0410 0x06 0x00 0x00 0x93f0430 0x01 0x00 0x00 0x93f0440 0x01 0x00 0x00 0x93f0448 0x01 0x00 0x00 0x93f04a0 0x01 0x00 0x00 0x93f04b0 0x01 0x00 0x00 0x93f04b8 0x02 0x00 0x00 0x93f04d0 0x01 0x00 0x00 0x93f1400 0x01 0x00 0x00 0x93f53b0 0x01 0x00 0x00 0x93f5c1c 0x01 0x00 0x00 0x93f5c2c 0x01 0x00 0x00 0x93f5c38 0x01 0x00 0x00 0x93f6418 0x02 0x00 0x00 0x9260080 0x01 0x00 0x00 0x9260400 0x01 0x00 0x00 0x9260410 0x03 0x00 0x00 0x9260420 0x02 0x00 0x00 0x9260430 0x01 0x00 0x00 0x9260440 0x01 0x00 0x00 0x9260448 0x01 0x00 0x00 0x92604a0 0x01 0x00 0x00 0x92604b0 0x01 0x00 0x00 0x92604b8 0x02 0x00 0x00 0x92604d0 0x02 0x00 0x00 0x9261400 0x01 0x00 0x00 0x9263410 0x01 0x00 0x00 0x92653b0 0x01 0x00 0x00 0x9265804 0x01 0x00 0x00 0x9265b1c 0x01 0x00 0x00 0x9265b2c 0x01 0x00 0x00 0x9265b38 0x01 0x00 0x00 0x9269100 0x01 0x00 0x00 0x9269110 0x01 0x00 0x00 0x9269120 0x01 0x00 0x00 0x92e0080 0x01 0x00 0x00 0x92e0400 0x01 0x00 0x00 0x92e0410 0x03 0x00 0x00 0x92e0420 0x02 0x00 0x00 0x92e0430 0x01 0x00 0x00 0x92e0440 0x01 0x00 0x00 0x92e0448 0x01 0x00 0x00 0x92e04a0 0x01 0x00 0x00 0x92e04b0 0x01 0x00 0x00 0x92e04b8 0x02 0x00 0x00 0x92e04d0 0x02 0x00 0x00 0x92e1400 0x01 0x00 0x00 0x92e3410 0x01 0x00 0x00 0x92e53b0 0x01 0x00 0x00 0x92e5804 0x01 0x00 0x00 0x92e5b1c 0x01 0x00 0x00 0x92e5b2c 0x01 0x00 0x00 0x92e5b38 0x01 0x00 0x00 0x92e9100 0x01 0x00 0x00 0x92e9110 0x01 0x00 0x00 0x92e9120 0x01 0x00 0x00 0x9360080 0x01 0x00 0x00 0x9360400 0x01 0x00 0x00 0x9360410 0x03 0x00 0x00 0x9360420 0x02 0x00 0x00 0x9360430 0x01 0x00 0x00 0x9360440 0x01 0x00 0x00 0x9360448 0x01 0x00 0x00 0x93604a0 0x01 0x00 0x00 0x93604b0 0x01 0x00 0x00 0x93604b8 0x02 0x00 0x00 0x93604d0 0x02 0x00 0x00 0x9361400 0x01 0x00 0x00 0x9363410 0x01 0x00 0x00 0x93653b0 0x01 0x00 0x00 0x9365804 0x01 0x00 0x00 0x9365b1c 0x01 0x00 0x00 0x9365b2c 0x01 0x00 0x00 0x9365b38 0x01 0x00 0x00 0x9369100 0x01 0x00 0x00 0x9369110 0x01 0x00 0x00 0x9369120 0x01 0x00 0x00 0x93e0080 0x01 0x00 0x00 0x93e0400 0x01 0x00 0x00 0x93e0410 0x03 0x00 0x00 0x93e0420 0x02 0x00 0x00 0x93e0430 0x01 0x00 0x00 0x93e0440 0x01 0x00 0x00 0x93e0448 0x01 0x00 0x00 0x93e04a0 0x01 0x00 0x00 0x93e04b0 0x01 0x00 0x00 0x93e04b8 0x02 0x00 0x00 0x93e04d0 0x02 0x00 0x00 0x93e1400 0x01 0x00 0x00 0x93e3410 0x01 0x00 0x00 0x93e53b0 0x01 0x00 0x00 0x93e5804 0x01 0x00 0x00 0x93e5b1c 0x01 0x00 0x00 0x93e5b2c 0x01 0x00 0x00 0x93e5b38 0x01 0x00 0x00 0x93e9100 0x01 0x00 0x00 0x93e9110 0x01 0x00 0x00 0x93e9120 0x01 0x00 0x00 0x96b0868 0x01 0x00 0x00 0x96b0870 0x01 0x00 0x00 0x96b1004 0x01 0x00 0x00 0x96b100c 0x01 0x00 0x00 0x96b1014 0x01 0x00 0x00 0x96b1204 0x01 0x00 0x00 0x96b120c 0x01 0x00 0x00 0x96b1214 0x01 0x00 0x00 0x96b1504 0x01 0x00 0x00 0x96b150c 0x01 0x00 0x00 0x96b1514 0x01 0x00 0x00 0x96b1604 0x01 0x00 0x00 0x96b8100 0x01 0x00 0x00 0x96b813c 0x01 0x00 0x00 0x96b8500 0x01 0x00 0x00 0x96b853c 0x01 0x00 0x00 0x96b8a04 0x01 0x00 0x00 0x96b8a18 0x01 0x00 0x00 0x96b8ea8 0x01 0x00 0x00 0x96b9044 0x01 0x00 0x00 0x96b904c 0x01 0x00 0x00 0x96b9054 0x01 0x00 0x00 0x96b905c 0x01 0x00 0x00 0x96b910c 0x02 0x00 0x00 0x96b9204 0x01 0x00 0x00 0x96b920c 0x01 0x00 0x00 0x96b9238 0x01 0x00 0x00 0x96b9240 0x01 0x00 0x00 0x96b926c 0x01 0x00 0x00 0x96b9394 0x01 0x00 0x00 0x96b939c 0x01 0x00 0x00 0x96b9704 0x01 0x00 0x00 0x96b970c 0x01 0x00 0x00 0x96f0868 0x01 0x00 0x00 0x96f0870 0x01 0x00 0x00 0x96f1004 0x01 0x00 0x00 0x96f100c 0x01 0x00 0x00 0x96f1014 0x01 0x00 0x00 0x96f1204 0x01 0x00 0x00 0x96f120c 0x01 0x00 0x00 0x96f1214 0x01 0x00 0x00 0x96f1504 0x01 0x00 0x00 0x96f150c 0x01 0x00 0x00 0x96f1514 0x01 0x00 0x00 0x96f1604 0x01 0x00 0x00 0x96f8100 0x01 0x00 0x00 0x96f813c 0x01 0x00 0x00 0x96f8500 0x01 0x00 0x00 0x96f853c 0x01 0x00 0x00 0x96f8a04 0x01 0x00 0x00 0x96f8a18 0x01 0x00 0x00 0x96f8ea8 0x01 0x00 0x00 0x96f9044 0x01 0x00 0x00 0x96f904c 0x01 0x00 0x00 0x96f9054 0x01 0x00 0x00 0x96f905c 0x01 0x00 0x00 0x96f910c 0x02 0x00 0x00 0x96f9204 0x01 0x00 0x00 0x96f920c 0x01 0x00 0x00 0x96f9238 0x01 0x00 0x00 0x96f9240 0x01 0x00 0x00 0x96f926c 0x01 0x00 0x00 0x96f9394 0x01 0x00 0x00 0x96f939c 0x01 0x00 0x00 0x96f9704 0x01 0x00 0x00 0x96f970c 0x01 0x00 0x00 0x9730868 0x01 0x00 0x00 0x9730870 0x01 0x00 0x00 0x9731004 0x01 0x00 0x00 0x973100c 0x01 0x00 0x00 0x9731014 0x01 0x00 0x00 0x9731204 0x01 0x00 0x00 0x973120c 0x01 0x00 0x00 0x9731214 0x01 0x00 0x00 0x9731504 0x01 0x00 0x00 0x973150c 0x01 0x00 0x00 0x9731514 0x01 0x00 0x00 0x9731604 0x01 0x00 0x00 0x9738100 0x01 0x00 0x00 0x973813c 0x01 0x00 0x00 0x9738500 0x01 0x00 0x00 0x973853c 0x01 0x00 0x00 0x9738a04 0x01 0x00 0x00 0x9738a18 0x01 0x00 0x00 0x9738ea8 0x01 0x00 0x00 0x9739044 0x01 0x00 0x00 0x973904c 0x01 0x00 0x00 0x9739054 0x01 0x00 0x00 0x973905c 0x01 0x00 0x00 0x973910c 0x02 0x00 0x00 0x9739204 0x01 0x00 0x00 0x973920c 0x01 0x00 0x00 0x9739238 0x01 0x00 0x00 0x9739240 0x01 0x00 0x00 0x973926c 0x01 0x00 0x00 0x9739394 0x01 0x00 0x00 0x973939c 0x01 0x00 0x00 0x9739704 0x01 0x00 0x00 0x973970c 0x01 0x00 0x00 0x9770868 0x01 0x00 0x00 0x9770870 0x01 0x00 0x00 0x9771004 0x01 0x00 0x00 0x977100c 0x01 0x00 0x00 0x9771014 0x01 0x00 0x00 0x9771204 0x01 0x00 0x00 0x977120c 0x01 0x00 0x00 0x9771214 0x01 0x00 0x00 0x9771504 0x01 0x00 0x00 0x977150c 0x01 0x00 0x00 0x9771514 0x01 0x00 0x00 0x9771604 0x01 0x00 0x00 0x9778100 0x01 0x00 0x00 0x977813c 0x01 0x00 0x00 0x9778500 0x01 0x00 0x00 0x977853c 0x01 0x00 0x00 0x9778a04 0x01 0x00 0x00 0x9778a18 0x01 0x00 0x00 0x9778ea8 0x01 0x00 0x00 0x9779044 0x01 0x00 0x00 0x977904c 0x01 0x00 0x00 0x9779054 0x01 0x00 0x00 0x977905c 0x01 0x00 0x00 0x977910c 0x02 0x00 0x00 0x9779204 0x01 0x00 0x00 0x977920c 0x01 0x00 0x00 0x9779238 0x01 0x00 0x00 0x9779240 0x01 0x00 0x00 0x977926c 0x01 0x00 0x00 0x9779394 0x01 0x00 0x00 0x977939c 0x01 0x00 0x00 0x9779704 0x01 0x00 0x00 0x977970c 0x01 0x00 0x00 0x910d100 0x03 0x00 0x00 0x914d100 0x03 0x00 0x00 0x918d100 0x04 0x00 0x00 0x91a5100 0x01 0x00 0x00 0x91ad100 0x01 0x00>; | |
| qcom,curr-link-list = <0x06>; | |
| }; | |
| link_list3 { | |
| qcom,data-sink = "sram"; | |
| qcom,link-list = <0x00 0x9050078 0x01 0x00 0x00 0x9050110 0x08 0x00 0x00 0x9080058 0x02 0x00 0x00 0x90800c8 0x01 0x00 0x00 0x90800d4 0x01 0x00 0x00 0x90800e0 0x01 0x00 0x00 0x90800ec 0x01 0x00 0x00 0x90800f8 0x01 0x00 0x00 0x908401c 0x01 0x00 0x00 0x908403c 0x01 0x00 0x00 0x908404c 0x02 0x00 0x00 0x90840d4 0x01 0x00 0x00 0x9084204 0x01 0x00 0x00 0x908420c 0x01 0x00 0x00 0x9084250 0x02 0x00 0x00 0x9084260 0x03 0x00 0x00 0x9084280 0x01 0x00 0x00 0x90ba280 0x01 0x00 0x00 0x90ba288 0x07 0x00 0x00 0x9258610 0x04 0x00 0x00 0x92d8610 0x04 0x00 0x00 0x9358610 0x04 0x00 0x00 0x93d8610 0x04 0x00 0x00 0x9220344 0x08 0x00 0x00 0x9220370 0x06 0x00 0x00 0x9220480 0x01 0x00 0x00 0x9222400 0x01 0x00 0x00 0x922240c 0x01 0x00 0x00 0x9223214 0x02 0x00 0x00 0x9223220 0x03 0x00 0x00 0x9223308 0x01 0x00 0x00 0x9223318 0x01 0x00 0x00 0x9232100 0x01 0x00 0x00 0x9236040 0x06 0x00 0x00 0x92360b0 0x01 0x00 0x00 0x923e030 0x02 0x00 0x00 0x9241000 0x01 0x00 0x00 0x9242028 0x01 0x00 0x00 0x9242044 0x03 0x00 0x00 0x9242070 0x01 0x00 0x00 0x9248030 0x01 0x00 0x00 0x9248048 0x08 0x00 0x00 0x92a0344 0x08 0x00 0x00 0x92a0370 0x06 0x00 0x00 0x92a0480 0x01 0x00 0x00 0x92a2400 0x01 0x00 0x00 0x92a240c 0x01 0x00 0x00 0x92a3214 0x02 0x00 0x00 0x92a3220 0x03 0x00 0x00 0x92a3308 0x01 0x00 0x00 0x92a3318 0x01 0x00 0x00 0x92b2100 0x01 0x00 0x00 0x92b6040 0x06 0x00 0x00 0x92b60b0 0x01 0x00 0x00 0x92be030 0x02 0x00 0x00 0x92c1000 0x01 0x00 0x00 0x92c2028 0x01 0x00 0x00 0x92c2044 0x03 0x00 0x00 0x92c2070 0x01 0x00 0x00 0x92c8030 0x01 0x00 0x00 0x92c8048 0x08 0x00 0x00 0x9320344 0x08 0x00 0x00 0x9320370 0x06 0x00 0x00 0x9320480 0x01 0x00 0x00 0x9322400 0x01 0x00 0x00 0x932240c 0x01 0x00 0x00 0x9323214 0x02 0x00 0x00 0x9323220 0x03 0x00 0x00 0x9323308 0x01 0x00 0x00 0x9323318 0x01 0x00 0x00 0x9332100 0x01 0x00 0x00 0x9336040 0x06 0x00 0x00 0x93360b0 0x01 0x00 0x00 0x933e030 0x02 0x00 0x00 0x9341000 0x01 0x00 0x00 0x9342028 0x01 0x00 0x00 0x9342044 0x03 0x00 0x00 0x9342070 0x01 0x00 0x00 0x9348030 0x01 0x00 0x00 0x9348048 0x08 0x00 0x00 0x93a0344 0x08 0x00 0x00 0x93a0370 0x06 0x00 0x00 0x93a0480 0x01 0x00 0x00 0x93a2400 0x01 0x00 0x00 0x93a240c 0x01 0x00 0x00 0x93a3214 0x02 0x00 0x00 0x93a3220 0x03 0x00 0x00 0x93a3308 0x01 0x00 0x00 0x93a3318 0x01 0x00 0x00 0x93b2100 0x01 0x00 0x00 0x93b6040 0x06 0x00 0x00 0x93b60b0 0x01 0x00 0x00 0x93be030 0x02 0x00 0x00 0x93c1000 0x01 0x00 0x00 0x93c2028 0x01 0x00 0x00 0x93c2044 0x03 0x00 0x00 0x93c2070 0x01 0x00 0x00 0x93c8030 0x01 0x00 0x00 0x93c8048 0x08 0x00 0x00 0x9270080 0x01 0x00 0x00 0x9270400 0x01 0x00 0x00 0x9270410 0x06 0x00 0x00 0x9270430 0x01 0x00 0x00 0x9270440 0x01 0x00 0x00 0x9270448 0x01 0x00 0x00 0x92704a0 0x01 0x00 0x00 0x92704b0 0x01 0x00 0x00 0x92704b8 0x02 0x00 0x00 0x92704d0 0x01 0x00 0x00 0x9271400 0x01 0x00 0x00 0x92753b0 0x01 0x00 0x00 0x9275c1c 0x01 0x00 0x00 0x9275c2c 0x01 0x00 0x00 0x9275c38 0x01 0x00 0x00 0x9276418 0x02 0x00 0x00 0x92f0080 0x01 0x00 0x00 0x92f0400 0x01 0x00 0x00 0x92f0410 0x06 0x00 0x00 0x92f0430 0x01 0x00 0x00 0x92f0440 0x01 0x00 0x00 0x92f0448 0x01 0x00 0x00 0x92f04a0 0x01 0x00 0x00 0x92f04b0 0x01 0x00 0x00 0x92f04b8 0x02 0x00 0x00 0x92f04d0 0x01 0x00 0x00 0x92f1400 0x01 0x00 0x00 0x92f53b0 0x01 0x00 0x00 0x92f5c1c 0x01 0x00 0x00 0x92f5c2c 0x01 0x00 0x00 0x92f5c38 0x01 0x00 0x00 0x92f6418 0x02 0x00 0x00 0x9370080 0x01 0x00 0x00 0x9370400 0x01 0x00 0x00 0x9370410 0x06 0x00 0x00 0x9370430 0x01 0x00 0x00 0x9370440 0x01 0x00 0x00 0x9370448 0x01 0x00 0x00 0x93704a0 0x01 0x00 0x00 0x93704b0 0x01 0x00 0x00 0x93704b8 0x02 0x00 0x00 0x93704d0 0x01 0x00 0x00 0x9371400 0x01 0x00 0x00 0x93753b0 0x01 0x00 0x00 0x9375c1c 0x01 0x00 0x00 0x9375c2c 0x01 0x00 0x00 0x9375c38 0x01 0x00 0x00 0x9376418 0x02 0x00 0x00 0x93f0080 0x01 0x00 0x00 0x93f0400 0x01 0x00 0x00 0x93f0410 0x06 0x00 0x00 0x93f0430 0x01 0x00 0x00 0x93f0440 0x01 0x00 0x00 0x93f0448 0x01 0x00 0x00 0x93f04a0 0x01 0x00 0x00 0x93f04b0 0x01 0x00 0x00 0x93f04b8 0x02 0x00 0x00 0x93f04d0 0x01 0x00 0x00 0x93f1400 0x01 0x00 0x00 0x93f53b0 0x01 0x00 0x00 0x93f5c1c 0x01 0x00 0x00 0x93f5c2c 0x01 0x00 0x00 0x93f5c38 0x01 0x00 0x00 0x93f6418 0x02 0x00 0x00 0x9260080 0x01 0x00 0x00 0x9260400 0x01 0x00 0x00 0x9260410 0x03 0x00 0x00 0x9260420 0x02 0x00 0x00 0x9260430 0x01 0x00 0x00 0x9260440 0x01 0x00 0x00 0x9260448 0x01 0x00 0x00 0x92604a0 0x01 0x00 0x00 0x92604b0 0x01 0x00 0x00 0x92604b8 0x02 0x00 0x00 0x92604d0 0x02 0x00 0x00 0x9261400 0x01 0x00 0x00 0x9263410 0x01 0x00 0x00 0x92653b0 0x01 0x00 0x00 0x9265804 0x01 0x00 0x00 0x9265b1c 0x01 0x00 0x00 0x9265b2c 0x01 0x00 0x00 0x9265b38 0x01 0x00 0x00 0x9269100 0x01 0x00 0x00 0x9269110 0x01 0x00 0x00 0x9269120 0x01 0x00 0x00 0x92e0080 0x01 0x00 0x00 0x92e0400 0x01 0x00 0x00 0x92e0410 0x03 0x00 0x00 0x92e0420 0x02 0x00 0x00 0x92e0430 0x01 0x00 0x00 0x92e0440 0x01 0x00 0x00 0x92e0448 0x01 0x00 0x00 0x92e04a0 0x01 0x00 0x00 0x92e04b0 0x01 0x00 0x00 0x92e04b8 0x02 0x00 0x00 0x92e04d0 0x02 0x00 0x00 0x92e1400 0x01 0x00 0x00 0x92e3410 0x01 0x00 0x00 0x92e53b0 0x01 0x00 0x00 0x92e5804 0x01 0x00 0x00 0x92e5b1c 0x01 0x00 0x00 0x92e5b2c 0x01 0x00 0x00 0x92e5b38 0x01 0x00 0x00 0x92e9100 0x01 0x00 0x00 0x92e9110 0x01 0x00 0x00 0x92e9120 0x01 0x00 0x00 0x9360080 0x01 0x00 0x00 0x9360400 0x01 0x00 0x00 0x9360410 0x03 0x00 0x00 0x9360420 0x02 0x00 0x00 0x9360430 0x01 0x00 0x00 0x9360440 0x01 0x00 0x00 0x9360448 0x01 0x00 0x00 0x93604a0 0x01 0x00 0x00 0x93604b0 0x01 0x00 0x00 0x93604b8 0x02 0x00 0x00 0x93604d0 0x02 0x00 0x00 0x9361400 0x01 0x00 0x00 0x9363410 0x01 0x00 0x00 0x93653b0 0x01 0x00 0x00 0x9365804 0x01 0x00 0x00 0x9365b1c 0x01 0x00 0x00 0x9365b2c 0x01 0x00 0x00 0x9365b38 0x01 0x00 0x00 0x9369100 0x01 0x00 0x00 0x9369110 0x01 0x00 0x00 0x9369120 0x01 0x00 0x00 0x93e0080 0x01 0x00 0x00 0x93e0400 0x01 0x00 0x00 0x93e0410 0x03 0x00 0x00 0x93e0420 0x02 0x00 0x00 0x93e0430 0x01 0x00 0x00 0x93e0440 0x01 0x00 0x00 0x93e0448 0x01 0x00 0x00 0x93e04a0 0x01 0x00 0x00 0x93e04b0 0x01 0x00 0x00 0x93e04b8 0x02 0x00 0x00 0x93e04d0 0x02 0x00 0x00 0x93e1400 0x01 0x00 0x00 0x93e3410 0x01 0x00 0x00 0x93e53b0 0x01 0x00 0x00 0x93e5804 0x01 0x00 0x00 0x93e5b1c 0x01 0x00 0x00 0x93e5b2c 0x01 0x00 0x00 0x93e5b38 0x01 0x00 0x00 0x93e9100 0x01 0x00 0x00 0x93e9110 0x01 0x00 0x00 0x93e9120 0x01 0x00 0x00 0x96b0868 0x01 0x00 0x00 0x96b0870 0x01 0x00 0x00 0x96b1004 0x01 0x00 0x00 0x96b100c 0x01 0x00 0x00 0x96b1014 0x01 0x00 0x00 0x96b1204 0x01 0x00 0x00 0x96b120c 0x01 0x00 0x00 0x96b1214 0x01 0x00 0x00 0x96b1504 0x01 0x00 0x00 0x96b150c 0x01 0x00 0x00 0x96b1514 0x01 0x00 0x00 0x96b1604 0x01 0x00 0x00 0x96b8100 0x01 0x00 0x00 0x96b813c 0x01 0x00 0x00 0x96b8500 0x01 0x00 0x00 0x96b853c 0x01 0x00 0x00 0x96b8a04 0x01 0x00 0x00 0x96b8a18 0x01 0x00 0x00 0x96b8ea8 0x01 0x00 0x00 0x96b9044 0x01 0x00 0x00 0x96b904c 0x01 0x00 0x00 0x96b9054 0x01 0x00 0x00 0x96b905c 0x01 0x00 0x00 0x96b910c 0x02 0x00 0x00 0x96b9204 0x01 0x00 0x00 0x96b920c 0x01 0x00 0x00 0x96b9238 0x01 0x00 0x00 0x96b9240 0x01 0x00 0x00 0x96b926c 0x01 0x00 0x00 0x96b9394 0x01 0x00 0x00 0x96b939c 0x01 0x00 0x00 0x96b9704 0x01 0x00 0x00 0x96b970c 0x01 0x00 0x00 0x96f0868 0x01 0x00 0x00 0x96f0870 0x01 0x00 0x00 0x96f1004 0x01 0x00 0x00 0x96f100c 0x01 0x00 0x00 0x96f1014 0x01 0x00 0x00 0x96f1204 0x01 0x00 0x00 0x96f120c 0x01 0x00 0x00 0x96f1214 0x01 0x00 0x00 0x96f1504 0x01 0x00 0x00 0x96f150c 0x01 0x00 0x00 0x96f1514 0x01 0x00 0x00 0x96f1604 0x01 0x00 0x00 0x96f8100 0x01 0x00 0x00 0x96f813c 0x01 0x00 0x00 0x96f8500 0x01 0x00 0x00 0x96f853c 0x01 0x00 0x00 0x96f8a04 0x01 0x00 0x00 0x96f8a18 0x01 0x00 0x00 0x96f8ea8 0x01 0x00 0x00 0x96f9044 0x01 0x00 0x00 0x96f904c 0x01 0x00 0x00 0x96f9054 0x01 0x00 0x00 0x96f905c 0x01 0x00 0x00 0x96f910c 0x02 0x00 0x00 0x96f9204 0x01 0x00 0x00 0x96f920c 0x01 0x00 0x00 0x96f9238 0x01 0x00 0x00 0x96f9240 0x01 0x00 0x00 0x96f926c 0x01 0x00 0x00 0x96f9394 0x01 0x00 0x00 0x96f939c 0x01 0x00 0x00 0x96f9704 0x01 0x00 0x00 0x96f970c 0x01 0x00 0x00 0x9730868 0x01 0x00 0x00 0x9730870 0x01 0x00 0x00 0x9731004 0x01 0x00 0x00 0x973100c 0x01 0x00 0x00 0x9731014 0x01 0x00 0x00 0x9731204 0x01 0x00 0x00 0x973120c 0x01 0x00 0x00 0x9731214 0x01 0x00 0x00 0x9731504 0x01 0x00 0x00 0x973150c 0x01 0x00 0x00 0x9731514 0x01 0x00 0x00 0x9731604 0x01 0x00 0x00 0x9738100 0x01 0x00 0x00 0x973813c 0x01 0x00 0x00 0x9738500 0x01 0x00 0x00 0x973853c 0x01 0x00 0x00 0x9738a04 0x01 0x00 0x00 0x9738a18 0x01 0x00 0x00 0x9738ea8 0x01 0x00 0x00 0x9739044 0x01 0x00 0x00 0x973904c 0x01 0x00 0x00 0x9739054 0x01 0x00 0x00 0x973905c 0x01 0x00 0x00 0x973910c 0x02 0x00 0x00 0x9739204 0x01 0x00 0x00 0x973920c 0x01 0x00 0x00 0x9739238 0x01 0x00 0x00 0x9739240 0x01 0x00 0x00 0x973926c 0x01 0x00 0x00 0x9739394 0x01 0x00 0x00 0x973939c 0x01 0x00 0x00 0x9739704 0x01 0x00 0x00 0x973970c 0x01 0x00 0x00 0x9770868 0x01 0x00 0x00 0x9770870 0x01 0x00 0x00 0x9771004 0x01 0x00 0x00 0x977100c 0x01 0x00 0x00 0x9771014 0x01 0x00 0x00 0x9771204 0x01 0x00 0x00 0x977120c 0x01 0x00 0x00 0x9771214 0x01 0x00 0x00 0x9771504 0x01 0x00 0x00 0x977150c 0x01 0x00 0x00 0x9771514 0x01 0x00 0x00 0x9771604 0x01 0x00 0x00 0x9778100 0x01 0x00 0x00 0x977813c 0x01 0x00 0x00 0x9778500 0x01 0x00 0x00 0x977853c 0x01 0x00 0x00 0x9778a04 0x01 0x00 0x00 0x9778a18 0x01 0x00 0x00 0x9778ea8 0x01 0x00 0x00 0x9779044 0x01 0x00 0x00 0x977904c 0x01 0x00 0x00 0x9779054 0x01 0x00 0x00 0x977905c 0x01 0x00 0x00 0x977910c 0x02 0x00 0x00 0x9779204 0x01 0x00 0x00 0x977920c 0x01 0x00 0x00 0x9779238 0x01 0x00 0x00 0x9779240 0x01 0x00 0x00 0x977926c 0x01 0x00 0x00 0x9779394 0x01 0x00 0x00 0x977939c 0x01 0x00 0x00 0x9779704 0x01 0x00 0x00 0x977970c 0x01 0x00 0x00 0x910d100 0x03 0x00 0x00 0x914d100 0x03 0x00 0x00 0x918d100 0x04 0x00 0x00 0x91a5100 0x01 0x00 0x00 0x91ad100 0x01 0x00>; | |
| qcom,curr-link-list = <0x07>; | |
| }; | |
| }; | |
| qcom,qbt_handler { | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x696>; | |
| compatible = "qcom,qbt-handler"; | |
| qcom,finger-detect-gpio = <0x695 0x01 0x00>; | |
| }; | |
| qcom,qsee_irq_bridge { | |
| compatible = "qcom,qsee-ipc-irq-bridge"; | |
| qcom,qsee-ipc-irq-spss { | |
| qcom,dev-name = "qsee_ipc_irq_spss"; | |
| interrupts = <0x01 0x00 0x04>; | |
| interrupt-parent = <0x85>; | |
| label = "spss"; | |
| }; | |
| }; | |
| qcom,cam-jpeg { | |
| num-jpeg-enc = <0x01>; | |
| num-jpeg-dma = <0x01>; | |
| compat-hw-name = "qcom,jpegenc\0qcom,jpegdma"; | |
| compatible = "qcom,cam-jpeg"; | |
| status = "ok"; | |
| }; | |
| qcom,qupv3_1_geni_se@ac0000 { | |
| iommus = <0x47 0x43 0x00>; | |
| qcom,bus-mas-id = <0x98>; | |
| qcom,bus-slv-id = <0x200>; | |
| compatible = "qcom,qupv3-geni-se"; | |
| qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>; | |
| reg = <0xac0000 0x2000>; | |
| phandle = <0x2a3>; | |
| qcom,iommu-dma = "fastmap"; | |
| }; | |
| qcom,gdsc@ad0a004 { | |
| clock-names = "ahb_clk"; | |
| qcom,msm-bus,name = "ife_0_gdsc_ahb"; | |
| parent-supply = <0x69>; | |
| qcom,retain-regs; | |
| clocks = <0x16 0x0b>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| regulator-name = "ife_0_gdsc"; | |
| vdd_parent-supply = <0x69>; | |
| compatible = "qcom,gdsc"; | |
| reg = <0xad0a004 0x04>; | |
| phandle = <0x26d>; | |
| qcom,msm-bus,vectors-KBps = <0x01 0x24d 0x00 0x00 0x01 0x24d 0x00 0x01>; | |
| }; | |
| qcom,devfreq-l3 { | |
| reg-names = "en-base\0ftbl-base\0perf-base"; | |
| compatible = "qcom,devfreq-fw"; | |
| reg = <0x18590000 0x04 0x18590100 0xa0 0x18590320 0x04>; | |
| qcom,cpu4-cpu-l3-lat { | |
| compatible = "qcom,devfreq-fw-voter"; | |
| phandle = <0x5a>; | |
| }; | |
| qcom,cpu7-cpu-l3-lat { | |
| compatible = "qcom,devfreq-fw-voter"; | |
| phandle = <0x5b>; | |
| }; | |
| qcom,cdsp-cdsp-l3-lat { | |
| compatible = "qcom,devfreq-fw-voter"; | |
| phandle = <0x8e>; | |
| }; | |
| qcom,cpu0-cpu-l3-lat { | |
| compatible = "qcom,devfreq-fw-voter"; | |
| phandle = <0x57>; | |
| }; | |
| }; | |
| syscon@3d91540 { | |
| compatible = "syscon"; | |
| reg = <0x3d91540 0x04>; | |
| phandle = <0x72>; | |
| }; | |
| qcom,npu-npu-llcc-bwmon@60300 { | |
| qcom,msm_bus = <0x9a 0x2756>; | |
| qcom,bwmon_clks = "npu_bwmon_ahb\0npu_bwmon_axi"; | |
| clock-names = "npu_bwmon_ahb\0npu_bwmon_axi"; | |
| reg-names = "base\0global_base"; | |
| interrupts = <0x00 0x1dc 0x04>; | |
| clocks = <0x16 0x2a 0x16 0x29>; | |
| qcom,msm_bus_name = "npu_bwmon_cdsp"; | |
| compatible = "qcom,bimc-bwmon4"; | |
| qcom,hw-timer-hz = <0x124f800>; | |
| qcom,mport = <0x00>; | |
| qcom,count-unit = <0x10000>; | |
| reg = <0x60400 0x300 0x60300 0x200>; | |
| phandle = <0x35f>; | |
| qcom,target-dev = <0x50>; | |
| }; | |
| ssusb@a600000 { | |
| iommus = <0x47 0x00 0x00>; | |
| #address-cells = <0x01>; | |
| clock-names = "core_clk\0iface_clk\0bus_aggr_clk\0utmi_clk\0sleep_clk\0xo"; | |
| reg-names = "core_base"; | |
| qcom,msm-bus,name = "usb0"; | |
| resets = <0x16 0x22>; | |
| clocks = <0x16 0xb6 0x16 0x0f 0x16 0x08 0x16 0xb8 0x16 0xbb 0x16 0xc7>; | |
| qcom,use-pdc-interrupts; | |
| qcom,msm-bus,num-paths = <0x03>; | |
| extcon = <0x637 0x39e>; | |
| #size-cells = <0x01>; | |
| qcom,msm-bus,num-cases = <0x04>; | |
| dpdm-supply = <0x183>; | |
| interrupts-extended = <0x76 0x0e 0x01 0x01 0x00 0x82 0x04 0x76 0x11 0x04 0x76 0x0f 0x01>; | |
| qcom,core-clk-rate-hs = <0x3f940ab>; | |
| qcom,num-gsi-evt-buffs = <0x03>; | |
| compatible = "qcom,dwc-usb3-msm"; | |
| ranges; | |
| interrupt-names = "dp_hs_phy_irq\0pwr_event_irq\0ss_phy_irq\0dm_hs_phy_irq"; | |
| qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; | |
| qcom,core-clk-rate = <0xbebc200>; | |
| reg = <0xa600000 0x100000>; | |
| phandle = <0x4da>; | |
| qcom,msm-bus,vectors-KBps = <0x3d 0x200 0x00 0x00 0x3d 0x2a4 0x00 0x00 0x01 0x247 0x00 0x00 0x3d 0x200 0xf4240 0x2625a0 0x3d 0x2a4 0x00 0x960 0x01 0x247 0x00 0x9c40 0x3d 0x200 0x3a980 0xaae60 0x3d 0x2a4 0x00 0x960 0x01 0x247 0x00 0x9c40 0x3d 0x200 0x01 0x01 0x3d 0x2a4 0x01 0x01 0x01 0x247 0x01 0x01>; | |
| qcom,dwc-usb3-msm-tx-fifo-size = <0x6c30>; | |
| reset-names = "core_reset"; | |
| USB3_GDSC-supply = <0x182>; | |
| qcom,gsi-reg-offset = <0xfc 0x110 0x120 0x130 0x144 0x1a4>; | |
| qcom,iommu-dma = "atomic"; | |
| dwc3@a600000 { | |
| linux,sysdev_is_parent; | |
| snps,hird-threshold = [10]; | |
| tx-fifo-resize; | |
| usb-core-id = <0x00>; | |
| snps,usb3-u1u2-disable; | |
| interrupts = <0x00 0x85 0x04>; | |
| compatible = "snps,dwc3"; | |
| snps,disable-clk-gating; | |
| snps,has-lpm-erratum; | |
| reg = <0xa600000 0xd93c>; | |
| usb-phy = <0x183 0x184>; | |
| dr_mode = "drd"; | |
| maximum-speed = "super-speed-plus"; | |
| }; | |
| qcom,usbbam@a704000 { | |
| qcom,disable-clk-gating; | |
| qcom,usb-bam-num-pipes = <0x04>; | |
| interrupts = <0x00 0x84 0x04>; | |
| qcom,usb-bam-max-mbps-highspeed = <0x190>; | |
| compatible = "qcom,usb-bam-msm"; | |
| qcom,usb-bam-max-mbps-superspeed = <0xe10>; | |
| qcom,usb-bam-fifo-baseaddr = <0x146bb000>; | |
| qcom,reset-bam-on-connect; | |
| reg = <0xa704000 0x17000>; | |
| qcom,usb-bam-override-threshold = <0x4001>; | |
| qcom,pipe0 { | |
| qcom,descriptor-fifo-offset = <0x1800>; | |
| qcom,data-fifo-offset = <0x00>; | |
| qcom,usb-bam-mem-type = <0x02>; | |
| qcom,src-bam-pipe-index = <0x00>; | |
| qcom,peer-bam-physical-address = <0x6064000>; | |
| qcom,peer-bam = <0x00>; | |
| qcom,dir = <0x01>; | |
| label = "ssusb-qdss-in-0"; | |
| qcom,dst-bam-pipe-index = <0x00>; | |
| qcom,data-fifo-size = <0x1800>; | |
| qcom,pipe-num = <0x00>; | |
| qcom,descriptor-fifo-size = <0x800>; | |
| }; | |
| }; | |
| }; | |
| cti@6e03000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti-ddr_dl_0_cti_2"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6e03000 0x1000>; | |
| phandle = <0x50e>; | |
| }; | |
| etm@7140000 { | |
| arm,primecell-periphid = <0xbb95d>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x49 0x00>; | |
| cpu = <0x0e>; | |
| qcom,tupwr-disable; | |
| coresight-name = "coresight-etm1"; | |
| compatible = "arm,primecell"; | |
| reg = <0x7140000 0x1000>; | |
| phandle = <0x548>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x23c>; | |
| phandle = <0x245>; | |
| }; | |
| }; | |
| }; | |
| cti@6016000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti6"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6016000 0x1000>; | |
| phandle = <0x51e>; | |
| }; | |
| qcom,glink { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| compatible = "qcom,glink"; | |
| ranges; | |
| npu { | |
| transport = "smem"; | |
| interrupts = <0x07 0x00 0x01>; | |
| qcom,glink-label = "npu"; | |
| interrupt-parent = <0x8a>; | |
| label = "npu"; | |
| qcom,remote-pid = <0x0a>; | |
| phandle = <0x8f>; | |
| mboxes = <0x3f 0x07 0x00>; | |
| mbox-names = "npu_smem"; | |
| qcom,npu_qrtr { | |
| qcom,net-id = <0x01>; | |
| qcom,intents = <0x800 0x05 0x2000 0x03 0x4400 0x02>; | |
| qcom,glink-channels = "IPCRTR"; | |
| }; | |
| qcom,npu_glink_ssr { | |
| qcom,notify-edges = <0x8b>; | |
| qcom,glink-channels = "glink_ssr"; | |
| }; | |
| }; | |
| adsp { | |
| transport = "smem"; | |
| interrupts = <0x03 0x00 0x01>; | |
| qcom,glink-label = "lpass"; | |
| interrupt-parent = <0x8a>; | |
| label = "adsp"; | |
| qcom,remote-pid = <0x02>; | |
| phandle = <0x8d>; | |
| mboxes = <0x8a 0x03 0x00>; | |
| mbox-names = "adsp_smem"; | |
| qcom,adsp_glink_ssr { | |
| qcom,notify-edges = <0x8c 0x8b>; | |
| qcom,glink-channels = "glink_ssr"; | |
| }; | |
| qcom,msm_fastrpc_rpmsg { | |
| qcom,intents = <0x64 0x40>; | |
| compatible = "qcom,msm-fastrpc-rpmsg"; | |
| qcom,glink-channels = "fastrpcglink-apps-dsp"; | |
| }; | |
| qcom,apr_tal_rpmsg { | |
| qcom,intents = <0x200 0x14>; | |
| qcom,glink-channels = "apr_audio_svc"; | |
| }; | |
| qcom,adsp_qrtr { | |
| qcom,net-id = <0x02>; | |
| qcom,intents = <0x800 0x05 0x2000 0x03 0x4400 0x02>; | |
| qcom,glink-channels = "IPCRTR"; | |
| }; | |
| }; | |
| spss { | |
| reg-names = "qcom,spss-addr\0qcom,spss-size"; | |
| transport = "spss"; | |
| interrupts = <0x00 0x00 0x04>; | |
| qcom,glink-label = "spss"; | |
| interrupt-parent = <0x85>; | |
| label = "spss"; | |
| qcom,remote-pid = <0x08>; | |
| reg = <0x1885008 0x08 0x1885010 0x04>; | |
| phandle = <0x39d>; | |
| mboxes = <0x90 0x00>; | |
| mbox-names = "spss_spss"; | |
| }; | |
| cdsp { | |
| transport = "smem"; | |
| interrupts = <0x06 0x00 0x01>; | |
| qcom,glink-label = "cdsp"; | |
| interrupt-parent = <0x8a>; | |
| label = "cdsp"; | |
| qcom,remote-pid = <0x05>; | |
| phandle = <0x8b>; | |
| mboxes = <0x8a 0x06 0x00>; | |
| mbox-names = "dsps_smem"; | |
| qcom,cdsp_qrtr { | |
| qcom,net-id = <0x01>; | |
| qcom,intents = <0x800 0x05 0x2000 0x03 0x4400 0x02>; | |
| qcom,glink-channels = "IPCRTR"; | |
| }; | |
| qcom,cdsp_glink_ssr { | |
| qcom,notify-edges = <0x8d 0x8c 0x8f>; | |
| qcom,glink-channels = "glink_ssr"; | |
| }; | |
| qcom,msm_fastrpc_rpmsg { | |
| qcom,intents = <0x64 0x40>; | |
| compatible = "qcom,msm-fastrpc-rpmsg"; | |
| qcom,glink-channels = "fastrpcglink-apps-dsp"; | |
| }; | |
| qcom,msm_cdsprm_rpmsg { | |
| qcom,intents = <0x20 0x0c>; | |
| compatible = "qcom,msm-cdsprm-rpmsg"; | |
| qcom,glink-channels = "cdsprmglink-apps-dsp"; | |
| qcom,msm_cdsp_rm { | |
| qcom,compute-priority-mode = <0x02>; | |
| qcom,qos-maxhold-ms = <0x14>; | |
| compatible = "qcom,msm-cdsp-rm"; | |
| qcom,compute-cx-limit-en; | |
| phandle = <0x3c>; | |
| #cooling-cells = <0x02>; | |
| qcom,qos-latency-us = <0x2c>; | |
| }; | |
| qcom,msm_hvx_rm { | |
| compatible = "qcom,msm-hvx-rm"; | |
| phandle = <0x39c>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| qcom,cdsp-cdsp-l3-gov { | |
| compatible = "qcom,cdsp-l3"; | |
| qcom,target-dev = <0x8e>; | |
| }; | |
| }; | |
| }; | |
| dsps { | |
| transport = "smem"; | |
| interrupts = <0x04 0x00 0x01>; | |
| qcom,glink-label = "dsps"; | |
| interrupt-parent = <0x8a>; | |
| label = "slpi"; | |
| qcom,remote-pid = <0x03>; | |
| phandle = <0x8c>; | |
| mboxes = <0x8a 0x04 0x00>; | |
| mbox-names = "dsps_smem"; | |
| qcom,slpi_qrtr { | |
| qcom,net-id = <0x02>; | |
| qcom,low-latency; | |
| qcom,intents = <0x800 0x05 0x2000 0x03 0x4400 0x02>; | |
| qcom,glink-channels = "IPCRTR"; | |
| }; | |
| qcom,msm_fastrpc_rpmsg { | |
| qcom,intents = <0x64 0x40>; | |
| compatible = "qcom,msm-fastrpc-rpmsg"; | |
| qcom,glink-channels = "fastrpcglink-apps-dsp"; | |
| }; | |
| qcom,slpi_glink_ssr { | |
| qcom,notify-edges = <0x8d 0x8b>; | |
| qcom,glink-channels = "glink_ssr"; | |
| }; | |
| }; | |
| }; | |
| jtagmm@7240000 { | |
| clock-names = "core_clk"; | |
| reg-names = "etm-base"; | |
| clocks = <0x49 0x00>; | |
| compatible = "qcom,jtagv8-mm"; | |
| qcom,coresight-jtagmm-cpu = <0x0f>; | |
| reg = <0x7240000 0x1000>; | |
| phandle = <0x354>; | |
| }; | |
| qcom,smem { | |
| memory-region = <0x82>; | |
| compatible = "qcom,smem"; | |
| phandle = <0x395>; | |
| hwlocks = <0x83 0x03>; | |
| }; | |
| qcom,msm-dai-q6-afe-loopback-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x6001>; | |
| phandle = <0x32b>; | |
| }; | |
| qcom,cvpss@abb0000 { | |
| memory-region = <0x9b>; | |
| qcom,pas-id = <0x1a>; | |
| compatible = "qcom,pil-tz-generic"; | |
| status = "ok"; | |
| reg = <0xabb0000 0x2000>; | |
| qcom,firmware-name = "cvpss"; | |
| }; | |
| va_npl_clk { | |
| qcom,codec-ext-clk-src = <0x0a>; | |
| #clock-cells = <0x01>; | |
| compatible = "qcom,audio-ref-clk"; | |
| phandle = <0x65a>; | |
| qcom,codec-lpass-clk-id = <0x310>; | |
| qcom,codec-lpass-ext-clk-freq = <0x124f800>; | |
| }; | |
| qcom,msm-rtb { | |
| compatible = "qcom,msm-rtb"; | |
| qcom,rtb-size = <0x100000>; | |
| }; | |
| qcom,msm-hdmi-dba-codec-rx { | |
| compatible = "qcom,msm-hdmi-dba-codec-rx"; | |
| phandle = <0x5e4>; | |
| qcom,dba-bridge-chip = "adv7533"; | |
| }; | |
| cti@6013000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti3"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6013000 0x1000>; | |
| phandle = <0x51b>; | |
| }; | |
| tpdm@6844000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-tpdm-lpass"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6844000 0x1000>; | |
| phandle = <0x1e9>; | |
| qcom,msr-fix-req; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x1ce>; | |
| phandle = <0x1cd>; | |
| }; | |
| }; | |
| }; | |
| qcom,dsi-display-secondary { | |
| pinctrl-names = "panel_active\0panel_suspend"; | |
| avdd-supply = <0x63c>; | |
| qcom,panel-te-source = <0x01>; | |
| pinctrl-0 = <0x411 0x415>; | |
| clock-names = "mux_byte_clk0\0mux_pixel_clk0\0cphy_byte_clk0\0cphy_pixel_clk0\0mux_byte_clk1\0mux_pixel_clk1\0cphy_byte_clk1\0cphy_pixel_clk1"; | |
| clocks = <0x55b 0x06 0x55b 0x09 0x55b 0x12 0x55b 0x15 0x55c 0x20 0x55c 0x23 0x55c 0x2c 0x55c 0x2f>; | |
| label = "secondary"; | |
| vdd-supply = <0x80>; | |
| qcom,dsi-phy = <0x559 0x55a>; | |
| compatible = "qcom,dsi-display"; | |
| vddio-supply = <0x7e>; | |
| pinctrl-1 = <0x412 0x416>; | |
| phandle = <0x645>; | |
| qcom,dsi-ctrl = <0x557 0x558>; | |
| qcom,mdp = <0x24c>; | |
| qcom,platform-te-gpio = <0x66 0x43 0x00>; | |
| }; | |
| qcom,rpm-stats@c3f0004 { | |
| reg-names = "phys_addr_base\0offset_addr"; | |
| qcom,num-records = <0x03>; | |
| compatible = "qcom,rpm-stats"; | |
| reg = <0xc300000 0x1000 0xc3f0004 0x04>; | |
| }; | |
| cti@6c2b000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti-dlct_cti1"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6c2b000 0x1000>; | |
| phandle = <0x517>; | |
| }; | |
| qcrypto@1de0000 { | |
| iommus = <0x47 0x584 0x11 0x47 0x594 0x11>; | |
| qcom,ce-hw-shared; | |
| qcom,ce-device = <0x00>; | |
| reg-names = "crypto-base\0crypto-bam-base"; | |
| qcom,use-sw-aes-xts-algo; | |
| qcom,clk-mgmt-sus-res; | |
| qcom,msm-bus,name = "qcrypto-noc"; | |
| qcom,bam-ee = <0x00>; | |
| interrupts = <0x00 0x110 0x04>; | |
| qcom,use-sw-aead-algo; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| compatible = "qcom,qcrypto"; | |
| qcom,no-clock-support; | |
| qcom,bam-pipe-pair = <0x02>; | |
| qcom,use-sw-ahash-algo; | |
| qcom,use-sw-aes-ccm-algo; | |
| reg = <0x1de0000 0x20000 0x1dc4000 0x24000>; | |
| phandle = <0x3a1>; | |
| qcom,msm-bus,vectors-KBps = <0x7d 0x200 0x00 0x00 0x7d 0x200 0x60180 0x60180>; | |
| qcom,smmu-s1-enable; | |
| qcom,use-sw-hmac-algo; | |
| qcom,use-sw-aes-cbc-ecb-ctr-algo; | |
| qcom,ce-hw-instance = <0x00>; | |
| qcom,iommu-dma = "atomic"; | |
| }; | |
| qcom,msm-pcm-voice { | |
| qcom,destroy-cvd; | |
| compatible = "qcom,msm-pcm-voice"; | |
| phandle = <0x2e4>; | |
| }; | |
| qcom,npudsp-npu-ddr-bw { | |
| qcom,src-dst-ports = <0x9a 0x200>; | |
| governor = "performance"; | |
| compatible = "qcom,devbw-ddr"; | |
| phandle = <0x53>; | |
| operating-points-v2 = <0x51>; | |
| }; | |
| npu_etm0 { | |
| qcom,inst-id = <0x0e>; | |
| coresight-name = "coresight-npu-etm0"; | |
| compatible = "qcom,coresight-remote-etm"; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x237>; | |
| phandle = <0x21e>; | |
| }; | |
| }; | |
| }; | |
| qcom,msm-dai-tdm-pri-tx { | |
| qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
| qcom,msm-cpudai-tdm-data-out = <0x00>; | |
| qcom,msm-cpudai-tdm-data-delay = <0x01>; | |
| qcom,msm-cpudai-tdm-group-port-id = <0x9001>; | |
| qcom,msm-cpudai-tdm-group-num-ports = <0x01>; | |
| qcom,msm-cpudai-tdm-invert-sync = <0x01>; | |
| compatible = "qcom,msm-dai-tdm"; | |
| qcom,msm-cpudai-tdm-group-id = <0x9101>; | |
| phandle = <0x5e7>; | |
| qcom,msm-cpudai-tdm-sync-src = <0x01>; | |
| qcom,msm-cpudai-tdm-clk-internal = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-mode = <0x01>; | |
| qcom,msm-dai-q6-tdm-pri-tx-0 { | |
| qcom,msm-cpudai-tdm-dev-id = <0x9001>; | |
| qcom,msm-cpudai-tdm-data-align = <0x00>; | |
| compatible = "qcom,msm-dai-q6-tdm"; | |
| phandle = <0x30a>; | |
| }; | |
| }; | |
| spi@884000 { | |
| pinctrl-names = "default\0sleep"; | |
| #address-cells = <0x01>; | |
| pinctrl-0 = <0x2d4>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| reg-names = "se_phys"; | |
| interrupts = <0x00 0x247 0x04>; | |
| clocks = <0x16 0x7a 0x16 0x88 0x16 0x89>; | |
| #size-cells = <0x00>; | |
| qcom,wrapper-core = <0x2bf>; | |
| spi-max-frequency = <0x2faf080>; | |
| dma-names = "tx\0rx"; | |
| compatible = "qcom,spi-geni"; | |
| pinctrl-1 = <0x2d5>; | |
| status = "disabled"; | |
| reg = <0x884000 0x4000>; | |
| phandle = <0x5c7>; | |
| dmas = <0x2c2 0x00 0x01 0x01 0x40 0x00 0x2c2 0x01 0x01 0x01 0x40 0x00>; | |
| }; | |
| qcom,cpu4-llcc-ddr-lat { | |
| qcom,src-dst-ports = <0x81 0x200>; | |
| governor = "performance"; | |
| compatible = "qcom,devbw-ddr"; | |
| phandle = <0x5d>; | |
| qcom,active-only; | |
| operating-points-v2 = <0x4d>; | |
| }; | |
| sdhci@8804000 { | |
| pinctrl-names = "active\0sleep"; | |
| qcom,large-address-bus; | |
| qcom,vdd-voltage-level = <0x2d0370 0x2d2a80>; | |
| qcom,restore-after-cx-collapse; | |
| pinctrl-0 = <0x3fa 0x400 0x406 0x3f9>; | |
| clock-names = "iface_clk\0core_clk"; | |
| qcom,bus-width = <0x04>; | |
| reg-names = "hc_mem"; | |
| qcom,msm-bus,name = "sdhc2"; | |
| pwr-gpios = <0x66 0x74 0x00>; | |
| qcom,pm-qos-irq-latency = <0x2c 0x2c>; | |
| qcom,pm-qos-legacy-latency-us = <0x2c 0x2c 0x2c 0x2c>; | |
| interrupts = <0x00 0xcc 0x04 0x00 0xde 0x04>; | |
| qcom,clk-rates = <0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100 0xc02a560>; | |
| clocks = <0x16 0x8a 0x16 0x8b>; | |
| qcom,vdd-always-on; | |
| qcom,msm-bus,num-paths = <0x02>; | |
| qcom,msm-bus,num-cases = <0x08>; | |
| qcom,vdd-io-current-level = <0xc8 0x55f0>; | |
| qcom,bus-bw-vectors-bps = <0x00 0x61a80 0x1312d00 0x17d7840 0x2faf080 0x60152b0 0xbebc200 0xffffffff>; | |
| qcom,pm-qos-cpu-groups = <0x3f 0xc0>; | |
| qcom,pm-qos-irq-type = "affine_irq"; | |
| vdd-supply = <0x38a>; | |
| compatible = "qcom,sdhci-msm-v5"; | |
| qcom,devfreq,freq-table = <0x2faf080 0xc02a560>; | |
| vdd-io-supply = <0x388>; | |
| pinctrl-1 = <0x3fb 0x401 0x407 0x3f9>; | |
| qcom,vdd-current-level = <0xc8 0xc3500>; | |
| status = "ok"; | |
| qcom,dll-hsr-list = <0x7642c 0xa800 0x10 0x2c010800 0x80040868>; | |
| interrupt-names = "hc_irq\0pwr_irq"; | |
| reg = <0x8804000 0x1000>; | |
| phandle = <0x379>; | |
| qcom,msm-bus,vectors-KBps = <0x51 0x200 0x00 0x00 0x01 0x260 0x00 0x00 0x51 0x200 0x416 0x640 0x01 0x260 0x640 0x640 0x51 0x200 0xcc3e 0x13880 0x01 0x260 0x13880 0x13880 0x51 0x200 0xff50 0x186a0 0x01 0x260 0x186a0 0x186a0 0x51 0x200 0x1fe9e 0x30d40 0x01 0x260 0x208c8 0x208c8 0x51 0x200 0x3fd3e 0x30d40 0x01 0x260 0x249f0 0x249f0 0x51 0x200 0x3fd3e 0x61a80 0x01 0x260 0x493e0 0x493e0 0x51 0x200 0x146cc2 0x3e8000 0x01 0x260 0x146cc2 0x3e8000>; | |
| cd-gpios = <0x66 0x4d 0x00>; | |
| qcom,bus-speed-mode = "SDR12\0SDR25\0SDR50\0DDR50\0SDR104"; | |
| qcom,vdd-io-voltage-level = <0x1b9680 0x2d2a80>; | |
| }; | |
| cti@6010000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti0"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6010000 0x1000>; | |
| phandle = <0x1a1>; | |
| }; | |
| qcom,msm-dai-q6-spdif-sec-tx { | |
| compatible = "qcom,msm-dai-q6-spdif"; | |
| qcom,msm-dai-q6-dev-id = <0x5003>; | |
| phandle = <0x5f5>; | |
| }; | |
| qcom,msm_notifier@0 { | |
| compatible = "qcom,msm-notifier"; | |
| phandle = <0x6e8>; | |
| panel = <0x63f 0x640 0x641>; | |
| }; | |
| smcinvoke@87900000 { | |
| reg-names = "secapp-region"; | |
| compatible = "qcom,smcinvoke"; | |
| reg = <0x87900000 0x2200000>; | |
| phandle = <0x3a5>; | |
| }; | |
| qcom,mdm0 { | |
| qcom,mdm-link-info = "0306_02.01.00"; | |
| qcom,sysmon-id = <0x14>; | |
| pinctrl-names = "mdm_active\0mdm_suspend"; | |
| qcom,vddmin-drive-strength = <0x08>; | |
| #address-cells = <0x00>; | |
| qcom,vddmin-modes = "normal"; | |
| qcom,pil-force-shutdown; | |
| qcom,ssctl-instance-id = <0x10>; | |
| pinctrl-0 = <0x62 0x63>; | |
| qcom,ramdump-delay-ms = <0xbb8>; | |
| cell-index = <0x00>; | |
| interrupt-map = <0x00 0x66 0x01 0x03 0x01 0x66 0x03 0x03>; | |
| qcom,ap2mdm-errfatal-gpio = <0x66 0x39 0x00>; | |
| interrupt-parent = <0x61>; | |
| qcom,mdm2ap-status-gpio = <0x66 0x03 0x00>; | |
| interrupt-map-mask = <0xffffffff>; | |
| qcom,ap2mdm-status-gpio = <0x66 0x38 0x00>; | |
| qcom,esoc-skip-restart-for-mdm-crash; | |
| compatible = "qcom,ext-sdx55m"; | |
| #interrupt-cells = <0x01>; | |
| pinctrl-1 = <0x64 0x65>; | |
| qcom,ramdump-timeout-ms = <0x1d4c0>; | |
| status = "disabled"; | |
| interrupt-names = "err_fatal_irq\0status_irq\0mdm2ap_vddmin_irq"; | |
| qcom,sfr-query; | |
| phandle = <0x61>; | |
| qcom,support-shutdown; | |
| qcom,mdm2ap-errfatal-gpio = <0x66 0x01 0x00>; | |
| }; | |
| i3c-master@980000 { | |
| pinctrl-names = "default\0sleep\0disable"; | |
| #address-cells = <0x03>; | |
| pinctrl-2 = <0x273>; | |
| pinctrl-0 = <0x271>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| qcom,ibi-ctrl-id = <0x00>; | |
| clocks = <0x16 0x58 0x16 0x84 0x16 0x85>; | |
| #size-cells = <0x00>; | |
| qcom,wrapper-core = <0x274>; | |
| interrupts-extended = <0x01 0x00 0x259 0x04 0x76 0x1f 0x04 0x76 0x1e 0x04>; | |
| compatible = "qcom,geni-i3c"; | |
| pinctrl-1 = <0x272>; | |
| status = "disabled"; | |
| reg = <0x980000 0x4000 0xec30000 0x10000>; | |
| phandle = <0x59c>; | |
| }; | |
| qcom,cnss-qca6390@b0000000 { | |
| qcom,vdd-wlan-aon-config = <0xe7ef0 0xe7ef0 0x00 0x00 0x01>; | |
| pinctrl-names = "wlan_en_active\0wlan_en_sleep"; | |
| mhi,timeout = <0x2710>; | |
| cnss-daemon-support; | |
| pinctrl-0 = <0xa5>; | |
| reg-names = "smmu_iova_ipa\0tcs_cmd"; | |
| qcom,converged-dt; | |
| mhi,m2-no-db-access; | |
| vdd-wlan-dig-supply = <0xa8>; | |
| qcom,msm-bus,name = "msm-cnss"; | |
| vdd-wlan-aon-supply = <0xa7>; | |
| qcom,wlan-rc-num = <0x00>; | |
| mhi,buffer-len = <0x8000>; | |
| vdd-wlan-rfa1-supply = <0xaa>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x07>; | |
| qcom,bt-en-gpio = <0x66 0x15 0x00>; | |
| vdd-wlan-rfa2-supply = <0xab>; | |
| qcom,cmd_db_name = "smpf2"; | |
| qcom,vdd-wlan-rfa1-config = <0x1cfde0 0x1cfde0 0x00 0x00 0x01>; | |
| qcom,vdd-wlan-io-config = <0x1b7740 0x1b7740 0x00 0x00 0x01>; | |
| vdd-wlan-io-supply = <0xa9>; | |
| qcom,vdd-wlan-rfa2-config = <0x149970 0x149970 0x00 0x00 0x01>; | |
| compatible = "qcom,cnss-qca6390"; | |
| qcom,set-wlaon-pwr-ctrl; | |
| pinctrl-1 = <0xa6>; | |
| reg = <0xb0000000 0x10000 0xb2e5510 0x5c0>; | |
| wlan-en-gpio = <0x66 0x14 0x00>; | |
| qcom,wlan-ramdump-dynamic = <0x420000>; | |
| phandle = <0x3a6>; | |
| qcom,msm-bus,vectors-KBps = <0x2d 0x200 0x00 0x00 0x2d 0x200 0x8ca 0x186a00 0x2d 0x200 0x1d4c 0x186a00 0x2d 0x200 0x7530 0x1b8a00 0x2d 0x200 0x186a0 0x1b8a00 0x2d 0x200 0x2ab98 0x5eec00 0x2d 0x200 0x1d4c 0x216600>; | |
| qcom,smmu-s1-enable; | |
| wlan-ant-switch-supply = <0xac>; | |
| qcom,vdd-wlan-dig-config = <0xe7ef0 0xe86c0 0x00 0x00 0x01>; | |
| cnss-enable-self-recovery; | |
| mhi,max-channels = <0x1e>; | |
| qcom,wlan-ant-switch-config = <0x1b7740 0x1b7740 0x00 0x00 0x00>; | |
| mhi_channels { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| mhi_chan@5 { | |
| mhi,event-ring = <0x01>; | |
| label = "DIAG"; | |
| mhi,data-type = <0x00>; | |
| mhi,num-elements = <0x20>; | |
| reg = <0x05>; | |
| mhi,ee = <0x14>; | |
| mhi,chan-dir = <0x02>; | |
| mhi,doorbell-mode = <0x02>; | |
| }; | |
| mhi_chan@1 { | |
| mhi,event-ring = <0x01>; | |
| label = "LOOPBACK"; | |
| mhi,data-type = <0x00>; | |
| mhi,num-elements = <0x20>; | |
| reg = <0x01>; | |
| mhi,ee = <0x14>; | |
| mhi,chan-dir = <0x02>; | |
| mhi,doorbell-mode = <0x02>; | |
| }; | |
| mhi_chan@21 { | |
| mhi,auto-start; | |
| mhi,event-ring = <0x01>; | |
| label = "IPCR"; | |
| mhi,data-type = <0x00>; | |
| mhi,num-elements = <0x20>; | |
| reg = <0x15>; | |
| mhi,ee = <0x14>; | |
| mhi,chan-dir = <0x02>; | |
| mhi,doorbell-mode = <0x02>; | |
| mhi,auto-queue; | |
| }; | |
| mhi_chan@4 { | |
| mhi,event-ring = <0x01>; | |
| label = "DIAG"; | |
| mhi,data-type = <0x00>; | |
| mhi,num-elements = <0x20>; | |
| reg = <0x04>; | |
| mhi,ee = <0x14>; | |
| mhi,chan-dir = <0x01>; | |
| mhi,doorbell-mode = <0x02>; | |
| }; | |
| mhi_chan@0 { | |
| mhi,event-ring = <0x01>; | |
| label = "LOOPBACK"; | |
| mhi,data-type = <0x00>; | |
| mhi,num-elements = <0x20>; | |
| reg = <0x00>; | |
| mhi,ee = <0x14>; | |
| mhi,chan-dir = <0x01>; | |
| mhi,doorbell-mode = <0x02>; | |
| }; | |
| mhi_chan@20 { | |
| mhi,auto-start; | |
| mhi,event-ring = <0x01>; | |
| label = "IPCR"; | |
| mhi,data-type = <0x01>; | |
| mhi,num-elements = <0x20>; | |
| reg = <0x14>; | |
| mhi,ee = <0x14>; | |
| mhi,chan-dir = <0x01>; | |
| mhi,doorbell-mode = <0x02>; | |
| }; | |
| }; | |
| mhi_events { | |
| mhi_event@2 { | |
| mhi,brstmode = <0x02>; | |
| mhi,intmod = <0x01>; | |
| mhi,data-type = <0x03>; | |
| mhi,priority = <0x02>; | |
| mhi,num-elements = <0x20>; | |
| mhi,msi = <0x00>; | |
| }; | |
| mhi_event@0 { | |
| mhi,brstmode = <0x02>; | |
| mhi,intmod = <0x00>; | |
| mhi,data-type = <0x01>; | |
| mhi,priority = <0x01>; | |
| mhi,num-elements = <0x20>; | |
| mhi,msi = <0x01>; | |
| }; | |
| mhi_event@1 { | |
| mhi,brstmode = <0x02>; | |
| mhi,intmod = <0x00>; | |
| mhi,priority = <0x01>; | |
| mhi,num-elements = <0x100>; | |
| mhi,msi = <0x02>; | |
| }; | |
| }; | |
| mhi_devices { | |
| mhi_qrtr { | |
| mhi,early-notify; | |
| mhi,chan = "IPCR"; | |
| qcom,net-id = <0x00>; | |
| qcom,low-latency; | |
| }; | |
| }; | |
| }; | |
| funnel@7800000 { | |
| arm,primecell-periphid = <0xbb908>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "funnel-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-funnel-apss"; | |
| compatible = "arm,primecell"; | |
| reg = <0x7800000 0x1000>; | |
| phandle = <0x54f>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x243>; | |
| phandle = <0x239>; | |
| }; | |
| }; | |
| port@7 { | |
| reg = <0x06>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x24a>; | |
| phandle = <0x241>; | |
| }; | |
| }; | |
| port@5 { | |
| reg = <0x04>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x248>; | |
| phandle = <0x23f>; | |
| }; | |
| }; | |
| port@3 { | |
| reg = <0x02>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x246>; | |
| phandle = <0x23d>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x00>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x244>; | |
| phandle = <0x23b>; | |
| }; | |
| }; | |
| port@8 { | |
| reg = <0x07>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x24b>; | |
| phandle = <0x242>; | |
| }; | |
| }; | |
| port@6 { | |
| reg = <0x05>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x249>; | |
| phandle = <0x240>; | |
| }; | |
| }; | |
| port@4 { | |
| reg = <0x03>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x247>; | |
| phandle = <0x23e>; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x01>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x245>; | |
| phandle = <0x23c>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,msm-pcm-afe { | |
| compatible = "qcom,msm-pcm-afe"; | |
| phandle = <0x2e8>; | |
| }; | |
| etm@7740000 { | |
| arm,primecell-periphid = <0xbb95d>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x49 0x00>; | |
| cpu = <0x14>; | |
| qcom,tupwr-disable; | |
| coresight-name = "coresight-etm7"; | |
| compatible = "arm,primecell"; | |
| reg = <0x7740000 0x1000>; | |
| phandle = <0x54e>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x242>; | |
| phandle = <0x24b>; | |
| }; | |
| }; | |
| }; | |
| qcom,gmu@3d6a000 { | |
| vddcx-supply = <0x17c>; | |
| clock-names = "gmu_clk\0cxo_clk\0axi_clk\0memnoc_clk\0gpu_cc_ahb"; | |
| reg-names = "kgsl_gmu_reg\0kgsl_gmu_pdc_cfg\0kgsl_gmu_pdc_seq"; | |
| qcom,msm-bus,name = "cnoc"; | |
| interrupts = <0x00 0x130 0x04 0x00 0x131 0x04>; | |
| clocks = <0x6e 0x03 0x6e 0x09 0x16 0x16 0x16 0x26 0x6e 0x00>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| label = "kgsl-gmu"; | |
| vdd-supply = <0x1af>; | |
| compatible = "qcom,gpu-gmu"; | |
| interrupt-names = "kgsl_hfi_irq\0kgsl_gmu_irq"; | |
| reg = <0x3d6a000 0x30000 0xb290000 0x10000 0xb490000 0x10000>; | |
| regulator-names = "vddcx\0vdd"; | |
| phandle = <0x60b>; | |
| qcom,msm-bus,vectors-KBps = <0x1a 0x2734 0x00 0x00 0x1a 0x2734 0x00 0x64>; | |
| mboxes = <0x02 0x00>; | |
| mbox-names = "aop"; | |
| gmu_kernel { | |
| iommus = <0x181 0x05 0x400>; | |
| compatible = "qcom,smmu-gmu-kernel-cb"; | |
| phandle = <0x60d>; | |
| qcom,iommu-dma = "disabled"; | |
| }; | |
| gmu_user { | |
| iommus = <0x181 0x04 0x400>; | |
| compatible = "qcom,smmu-gmu-user-cb"; | |
| phandle = <0x60c>; | |
| qcom,iommu-dma = "disabled"; | |
| }; | |
| }; | |
| spi@98c000 { | |
| pinctrl-names = "default\0sleep"; | |
| #address-cells = <0x01>; | |
| pinctrl-0 = <0x297>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| reg-names = "se_phys"; | |
| interrupts = <0x00 0x25c 0x04>; | |
| clocks = <0x16 0x5e 0x16 0x84 0x16 0x85>; | |
| #size-cells = <0x00>; | |
| qcom,wrapper-core = <0x274>; | |
| spi-max-frequency = <0x2faf080>; | |
| dma-names = "tx\0rx"; | |
| compatible = "qcom,spi-geni"; | |
| pinctrl-1 = <0x298>; | |
| status = "disabled"; | |
| reg = <0x98c000 0x4000>; | |
| phandle = <0x5ab>; | |
| dmas = <0x280 0x00 0x03 0x01 0x40 0x00 0x280 0x01 0x03 0x01 0x40 0x00>; | |
| }; | |
| qcom,chd_silver { | |
| qcom,config-arr = <0x18000060 0x18010060 0x18020060 0x18030060>; | |
| label = "silver"; | |
| qcom,threshold-arr = <0x18000058 0x18010058 0x18020058 0x18030058>; | |
| compatible = "qcom,core-hang-detect"; | |
| }; | |
| qcom,ipa-mpm { | |
| qcom,mhi-chdb-base = <0x64300300>; | |
| qcom,iova-mapping = <0x10000000 0xfffffff>; | |
| qcom,mhi-erdb-base = "d0\a"; | |
| compatible = "qcom,ipa-mpm"; | |
| }; | |
| i2c@890000 { | |
| pinctrl-names = "default\0sleep"; | |
| #address-cells = <0x01>; | |
| pinctrl-0 = <0x2ce>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| interrupts = <0x00 0x24a 0x04>; | |
| clocks = <0x16 0x80 0x16 0x88 0x16 0x89>; | |
| #size-cells = <0x00>; | |
| qcom,wrapper-core = <0x2bf>; | |
| dma-names = "tx\0rx"; | |
| compatible = "qcom,i2c-geni"; | |
| pinctrl-1 = <0x2cf>; | |
| status = "disabled"; | |
| reg = <0x890000 0x4000>; | |
| phandle = <0x5c4>; | |
| dmas = <0x2c2 0x00 0x04 0x03 0x40 0x00 0x2c2 0x01 0x04 0x03 0x40 0x00>; | |
| }; | |
| qcom,msm-dai-tdm-tert-tx { | |
| qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
| qcom,msm-cpudai-tdm-data-out = <0x00>; | |
| qcom,msm-cpudai-tdm-data-delay = <0x01>; | |
| qcom,msm-cpudai-tdm-group-port-id = <0x9021>; | |
| qcom,msm-cpudai-tdm-group-num-ports = <0x01>; | |
| qcom,msm-cpudai-tdm-invert-sync = <0x01>; | |
| compatible = "qcom,msm-dai-tdm"; | |
| qcom,msm-cpudai-tdm-group-id = <0x9121>; | |
| phandle = <0x5eb>; | |
| qcom,msm-cpudai-tdm-sync-src = <0x01>; | |
| qcom,msm-cpudai-tdm-clk-internal = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-mode = <0x01>; | |
| qcom,msm-dai-q6-tdm-tert-tx-0 { | |
| qcom,msm-cpudai-tdm-dev-id = <0x9021>; | |
| qcom,msm-cpudai-tdm-data-align = <0x00>; | |
| compatible = "qcom,msm-dai-q6-tdm"; | |
| phandle = <0x30e>; | |
| }; | |
| }; | |
| qcom,gdsc@ad07004 { | |
| clock-names = "ahb_clk"; | |
| qcom,msm-bus,name = "bps_gdsc_ahb"; | |
| parent-supply = <0x69>; | |
| qcom,support-hw-trigger; | |
| qcom,retain-regs; | |
| clocks = <0x16 0x0b>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| regulator-name = "bps_gdsc"; | |
| vdd_parent-supply = <0x69>; | |
| compatible = "qcom,gdsc"; | |
| reg = <0xad07004 0x04>; | |
| phandle = <0x270>; | |
| qcom,msm-bus,vectors-KBps = <0x01 0x24d 0x00 0x00 0x01 0x24d 0x00 0x01>; | |
| }; | |
| qcom,csid-lite0@acd9200 { | |
| camss-supply = <0x253>; | |
| clock-control-debugfs = "true"; | |
| clock-names = "ife_csid_clk_src\0ife_csid_clk\0cphy_rx_clk_src\0ife_cphy_rx_clk\0ife_clk_src\0ife_lite_ahb\0ife_clk"; | |
| reg-names = "csid-lite"; | |
| reg-cam-base = <0xd9200>; | |
| cell-index = <0x02>; | |
| interrupts = <0x00 0x1d4 0x01>; | |
| clocks = <0x6d 0x41 0x6d 0x40 0x6d 0x0e 0x6d 0x3f 0x6d 0x3e 0x6d 0x3b 0x6d 0x3d>; | |
| clock-cntl-level = "lowsvs\0svs\0svs_l1\0turbo"; | |
| compatible = "qcom,csid-lite480"; | |
| src-clock-name = "ife_csid_clk_src"; | |
| status = "ok"; | |
| interrupt-names = "csid-lite"; | |
| reg = <0xacd9200 0x1000>; | |
| regulator-names = "camss"; | |
| phandle = <0x592>; | |
| clock-rates = <0x17d78400 0x00 0x00 0x00 0x17d78400 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x1c9c3800 0x00 0x00>; | |
| }; | |
| qcom,msm-dai-tdm-pri-rx { | |
| qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
| qcom,msm-cpudai-tdm-data-out = <0x00>; | |
| qcom,msm-cpudai-tdm-data-delay = <0x01>; | |
| qcom,msm-cpudai-tdm-group-port-id = <0x9000>; | |
| qcom,msm-cpudai-tdm-group-num-ports = <0x01>; | |
| qcom,msm-cpudai-tdm-invert-sync = <0x01>; | |
| compatible = "qcom,msm-dai-tdm"; | |
| qcom,msm-cpudai-tdm-group-id = <0x9100>; | |
| phandle = <0x5e6>; | |
| qcom,msm-cpudai-tdm-sync-src = <0x01>; | |
| qcom,msm-cpudai-tdm-clk-internal = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-mode = <0x01>; | |
| qcom,msm-dai-q6-tdm-pri-rx-0 { | |
| qcom,msm-cpudai-tdm-dev-id = <0x9000>; | |
| qcom,msm-cpudai-tdm-data-align = <0x00>; | |
| compatible = "qcom,msm-dai-q6-tdm"; | |
| phandle = <0x309>; | |
| }; | |
| }; | |
| tpdm@6e10000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-tpdm-ddr-ch02"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6e10000 0x1000>; | |
| phandle = <0x1eb>; | |
| qcom,msr-fix-req; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x22d>; | |
| phandle = <0x22a>; | |
| }; | |
| }; | |
| }; | |
| qcom,msm-dai-q6-spdif-sec-rx { | |
| compatible = "qcom,msm-dai-q6-spdif"; | |
| qcom,msm-dai-q6-dev-id = <0x5002>; | |
| phandle = <0x5f4>; | |
| }; | |
| qcom,wil6210 { | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0xae>; | |
| clock-names = "rf_clk"; | |
| qcom,msm-bus,name = "wil6210"; | |
| clocks = <0x15 0x08>; | |
| qcom,use-ap-power-save; | |
| qcom,keep-radio-on-during-sleep; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x03>; | |
| vdd-ldo-supply = <0xaf>; | |
| compatible = "qcom,wil6210"; | |
| vddio-supply = <0xaa>; | |
| qcom,use-ext-supply; | |
| status = "ok"; | |
| qcom,pcie-parent = <0xad>; | |
| qcom,use-ext-clocks; | |
| phandle = <0x3a7>; | |
| qcom,msm-bus,vectors-KBps = <0x64 0x200 0x00 0x00 0x64 0x200 0x927c0 0xc3500 0x64 0x200 0x13d620 0x13d620>; | |
| }; | |
| qcom,gpi-dma@900000 { | |
| iommus = <0x47 0x5b6 0x00>; | |
| qcom,gpi-ee-offset = <0x1000>; | |
| qcom,gpii-mask = <0x7ff>; | |
| qcom,smmu-cfg = <0x01>; | |
| reg-names = "gpi-top"; | |
| interrupts = <0x00 0xf4 0x04 0x00 0xf5 0x04 0x00 0xf6 0x04 0x00 0xf7 0x04 0x00 0xf8 0x04 0x00 0xf9 0x04 0x00 0xfa 0x04 0x00 0xfb 0x04 0x00 0xfc 0x04 0x00 0xfd 0x04 0x00 0xfe 0x04 0x00 0xff 0x04 0x00 0x100 0x04>; | |
| qcom,ev-factor = <0x02>; | |
| compatible = "qcom,gpi-dma"; | |
| status = "ok"; | |
| qcom,iommu-dma-addr-pool = <0x100000 0x100000>; | |
| qcom,max-num-gpii = <0x0f>; | |
| reg = <0x900000 0x70000>; | |
| phandle = <0x280>; | |
| #dma-cells = <0x05>; | |
| }; | |
| funnel@6e22000 { | |
| arm,primecell-periphid = <0xbb908>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "funnel-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-funnel-ddr-ch13"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6e22000 0x1000>; | |
| phandle = <0x507>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x22b>; | |
| phandle = <0x227>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x00>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x22c>; | |
| phandle = <0x22e>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| i2c@888000 { | |
| pinctrl-names = "default\0sleep"; | |
| #address-cells = <0x01>; | |
| pinctrl-0 = <0x2ca>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| interrupts = <0x00 0x248 0x04>; | |
| clocks = <0x16 0x7c 0x16 0x88 0x16 0x89>; | |
| #size-cells = <0x00>; | |
| qcom,wrapper-core = <0x2bf>; | |
| dma-names = "tx\0rx"; | |
| compatible = "qcom,i2c-geni"; | |
| pinctrl-1 = <0x2cb>; | |
| status = "disabled"; | |
| reg = <0x888000 0x4000>; | |
| phandle = <0x5c2>; | |
| dmas = <0x2c2 0x00 0x02 0x03 0x40 0x00 0x2c2 0x01 0x02 0x03 0x40 0x00>; | |
| }; | |
| qcom,gdsc@18d004 { | |
| qcom,retain-regs; | |
| regulator-name = "pcie_1_gdsc"; | |
| compatible = "qcom,gdsc"; | |
| reg = <0x18d004 0x04>; | |
| phandle = <0x172>; | |
| }; | |
| cti@7320000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| cpu = <0x10>; | |
| coresight-name = "coresight-cti-cpu3"; | |
| compatible = "arm,primecell"; | |
| reg = <0x7320000 0x1000>; | |
| phandle = <0x52b>; | |
| }; | |
| qcom,spmi-debug@6b0f000 { | |
| #address-cells = <0x02>; | |
| clock-names = "core_clk"; | |
| reg-names = "core\0fuse"; | |
| clocks = <0x49 0x00>; | |
| #size-cells = <0x00>; | |
| qcom,fuse-disable-bit = <0x18>; | |
| compatible = "qcom,spmi-pmic-arb-debug"; | |
| status = "ok"; | |
| reg = <0x6b0f000 0x60 0x7820a8 0x04>; | |
| phandle = <0x377>; | |
| qcom,pmxprairie-debug@8 { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| qcom,can-sleep; | |
| compatible = "qcom,spmi-pmic"; | |
| reg = <0x08 0x00>; | |
| }; | |
| qcom,pm8009-debug@b { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| qcom,can-sleep; | |
| compatible = "qcom,spmi-pmic"; | |
| reg = <0x0b 0x00>; | |
| }; | |
| qcom,pmk8002-debug@6 { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| qcom,can-sleep; | |
| compatible = "qcom,spmi-pmic"; | |
| reg = <0x06 0x00>; | |
| }; | |
| qcom,pm8150-debug@1 { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| qcom,can-sleep; | |
| compatible = "qcom,spmi-pmic"; | |
| reg = <0x01 0x00>; | |
| }; | |
| qcom,pm8150b-debug@2 { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| qcom,can-sleep; | |
| compatible = "qcom,spmi-pmic"; | |
| reg = <0x02 0x00>; | |
| }; | |
| qcom,pm8150l-debug@5 { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| qcom,can-sleep; | |
| compatible = "qcom,spmi-pmic"; | |
| reg = <0x05 0x00>; | |
| }; | |
| qcom,pmxprairie-debug@9 { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| qcom,can-sleep; | |
| compatible = "qcom,spmi-pmic"; | |
| reg = <0x09 0x00>; | |
| }; | |
| qcom,pmk8002-debug@7 { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| qcom,can-sleep; | |
| compatible = "qcom,spmi-pmic"; | |
| reg = <0x07 0x00>; | |
| }; | |
| qcom,pm8009-debug@a { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| qcom,can-sleep; | |
| compatible = "qcom,spmi-pmic"; | |
| reg = <0x0a 0x00>; | |
| }; | |
| qcom,pm8150b-debug@3 { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| qcom,can-sleep; | |
| compatible = "qcom,spmi-pmic"; | |
| reg = <0x03 0x00>; | |
| }; | |
| qcom,pm8150-debug@0 { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| qcom,can-sleep; | |
| compatible = "qcom,spmi-pmic"; | |
| reg = <0x00 0x00>; | |
| }; | |
| qcom,pm8150l-debug@4 { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| qcom,can-sleep; | |
| compatible = "qcom,spmi-pmic"; | |
| reg = <0x04 0x00>; | |
| }; | |
| }; | |
| qmi-tmd-devices { | |
| compatible = "qcom,qmi-cooling-devices"; | |
| modem { | |
| qcom,instance-id = <0x64>; | |
| modem_mmw2 { | |
| phandle = <0x5ff>; | |
| qcom,qmi-dev-name = "mmw2"; | |
| #cooling-cells = <0x02>; | |
| }; | |
| modem_pa_fr1 { | |
| phandle = <0x5f6>; | |
| qcom,qmi-dev-name = "pa_fr1"; | |
| #cooling-cells = <0x02>; | |
| }; | |
| modem_mmw_skin2 { | |
| phandle = <0x5fb>; | |
| qcom,qmi-dev-name = "mmw_skin2"; | |
| #cooling-cells = <0x02>; | |
| }; | |
| modem_mmw0 { | |
| phandle = <0x5fd>; | |
| qcom,qmi-dev-name = "mmw0"; | |
| #cooling-cells = <0x02>; | |
| }; | |
| modem_mmw_skin0 { | |
| phandle = <0x5f9>; | |
| qcom,qmi-dev-name = "mmw_skin0"; | |
| #cooling-cells = <0x02>; | |
| }; | |
| modem_tj { | |
| phandle = <0x3e>; | |
| qcom,qmi-dev-name = "modem"; | |
| #cooling-cells = <0x02>; | |
| }; | |
| modem_pa { | |
| phandle = <0x3d>; | |
| qcom,qmi-dev-name = "pa"; | |
| #cooling-cells = <0x02>; | |
| }; | |
| modem_mmw3 { | |
| phandle = <0x600>; | |
| qcom,qmi-dev-name = "mmw3"; | |
| #cooling-cells = <0x02>; | |
| }; | |
| modem_mmw_skin3 { | |
| phandle = <0x5fc>; | |
| qcom,qmi-dev-name = "mmw_skin3"; | |
| #cooling-cells = <0x02>; | |
| }; | |
| modem_mmw1 { | |
| phandle = <0x5fe>; | |
| qcom,qmi-dev-name = "mmw1"; | |
| #cooling-cells = <0x02>; | |
| }; | |
| modem_skin { | |
| phandle = <0x5f8>; | |
| qcom,qmi-dev-name = "modem_skin"; | |
| #cooling-cells = <0x02>; | |
| }; | |
| modem_mmw_skin1 { | |
| phandle = <0x5fa>; | |
| qcom,qmi-dev-name = "mmw_skin1"; | |
| #cooling-cells = <0x02>; | |
| }; | |
| modem_charge_state { | |
| phandle = <0x602>; | |
| qcom,qmi-dev-name = "charge_state"; | |
| #cooling-cells = <0x02>; | |
| }; | |
| modem_current { | |
| phandle = <0x5f7>; | |
| qcom,qmi-dev-name = "modem_current"; | |
| #cooling-cells = <0x02>; | |
| }; | |
| modem_bcl { | |
| phandle = <0x601>; | |
| qcom,qmi-dev-name = "vbatt_low"; | |
| #cooling-cells = <0x02>; | |
| }; | |
| }; | |
| }; | |
| qcom,smp2p_interrupt_qvrexternal_5_out { | |
| qcom,smem-state-names = "qvrexternal-smp2p-out"; | |
| compatible = "qcom,smp2p-interrupt-qvrexternal-5-out"; | |
| qcom,smem-states = <0x336 0x00>; | |
| }; | |
| tx_npl_clk { | |
| qcom,codec-ext-clk-src = <0x08>; | |
| #clock-cells = <0x01>; | |
| compatible = "qcom,audio-ref-clk"; | |
| phandle = <0x654>; | |
| qcom,codec-lpass-clk-id = <0x30d>; | |
| qcom,codec-lpass-ext-clk-freq = <0x124f800>; | |
| }; | |
| replicator@6046000 { | |
| arm,primecell-periphid = <0xbb909>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "replicator-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-replicator-qdss"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6046000 0x1000>; | |
| phandle = <0x4dd>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x18b>; | |
| phandle = <0x1a3>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x00>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x18c>; | |
| phandle = <0x18e>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,gdsc@3d9106c { | |
| hw-ctrl-addr = <0x72>; | |
| qcom,no-status-check-on-disable; | |
| qcom,gds-timeout = <0x1f4>; | |
| parent-supply = <0x67>; | |
| qcom,retain-regs; | |
| qcom,clk-dis-wait-val = <0x08>; | |
| regulator-name = "gpu_cx_gdsc"; | |
| vdd_parent-supply = <0x67>; | |
| compatible = "qcom,gdsc"; | |
| reg = <0x3d9106c 0x04>; | |
| phandle = <0x17c>; | |
| }; | |
| tpdm@6830000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-tpdm-venus"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6830000 0x1000>; | |
| phandle = <0x1e3>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x217>; | |
| phandle = <0x216>; | |
| }; | |
| }; | |
| }; | |
| qcom,smp2p-dsps { | |
| qcom,local-pid = <0x00>; | |
| interrupts = <0x04 0x02 0x01>; | |
| interrupt-parent = <0x8a>; | |
| qcom,remote-pid = <0x03>; | |
| compatible = "qcom,smp2p"; | |
| mboxes = <0x8a 0x04 0x02>; | |
| qcom,smem = <0x1e1 0x1ae>; | |
| slave-kernel { | |
| qcom,entry-name = "slave-kernel"; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0xa3>; | |
| interrupt-controller; | |
| }; | |
| qcom,sleepstate-in { | |
| qcom,entry-name = "sleepstate_see"; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x9f>; | |
| interrupt-controller; | |
| }; | |
| sleepstate-out { | |
| qcom,entry-name = "sleepstate"; | |
| #qcom,smem-state-cells = <0x01>; | |
| phandle = <0x9e>; | |
| }; | |
| master-kernel { | |
| qcom,entry-name = "master-kernel"; | |
| #qcom,smem-state-cells = <0x01>; | |
| phandle = <0xa4>; | |
| }; | |
| }; | |
| qcom,msm-compress-dsp { | |
| compatible = "qcom,msm-compress-dsp"; | |
| phandle = <0x2e6>; | |
| }; | |
| turing_etm0 { | |
| qcom,inst-id = <0x0d>; | |
| coresight-name = "coresight-turing-etm0"; | |
| compatible = "qcom,coresight-remote-etm"; | |
| phandle = <0x545>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x234>; | |
| phandle = <0x222>; | |
| }; | |
| }; | |
| }; | |
| tsens@c223000 { | |
| reg-names = "tsens_srot_physical\0tsens_tm_physical"; | |
| interrupts = <0x00 0x1fb 0x04 0x00 0x1fd 0x04>; | |
| #thermal-sensor-cells = <0x01>; | |
| compatible = "qcom,tsens24xx"; | |
| interrupt-names = "tsens-upper-lower\0tsens-critical"; | |
| reg = <0xc223000 0x04 0xc265000 0x1ff>; | |
| phandle = <0x1a>; | |
| tsens-reinit-wa; | |
| }; | |
| qcom,cam-req-mgr { | |
| compatible = "qcom,cam-req-mgr"; | |
| status = "ok"; | |
| }; | |
| spi@994000 { | |
| pinctrl-names = "default\0sleep"; | |
| #address-cells = <0x01>; | |
| pinctrl-0 = <0x29b>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| reg-names = "se_phys"; | |
| interrupts = <0x00 0x25e 0x04>; | |
| clocks = <0x16 0x62 0x16 0x84 0x16 0x85>; | |
| #size-cells = <0x00>; | |
| qcom,wrapper-core = <0x274>; | |
| spi-max-frequency = <0x2faf080>; | |
| dma-names = "tx\0rx"; | |
| compatible = "qcom,spi-geni"; | |
| pinctrl-1 = <0x29c>; | |
| status = "disabled"; | |
| reg = <0x994000 0x4000>; | |
| phandle = <0x5ad>; | |
| dmas = <0x280 0x00 0x05 0x01 0x40 0x00 0x280 0x01 0x05 0x01 0x40 0x00>; | |
| }; | |
| qcom,gdsc@17d06c { | |
| qcom,no-status-check-on-disable; | |
| qcom,gds-timeout = <0x1f4>; | |
| regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc"; | |
| compatible = "qcom,gdsc"; | |
| reg = <0x17d06c 0x04>; | |
| phandle = <0x180>; | |
| }; | |
| qcom,pcie1_msi@17a10040 { | |
| interrupts = <0x00 0x320 0x01 0x00 0x321 0x01 0x00 0x322 0x01 0x00 0x323 0x01 0x00 0x324 0x01 0x00 0x325 0x01 0x00 0x326 0x01 0x00 0x327 0x01 0x00 0x328 0x01 0x00 0x329 0x01 0x00 0x32a 0x01 0x00 0x32b 0x01 0x00 0x32c 0x01 0x00 0x32d 0x01 0x00 0x32e 0x01 0x00 0x32f 0x01 0x00 0x330 0x01 0x00 0x331 0x01 0x00 0x332 0x01 0x00 0x333 0x01 0x00 0x334 0x01 0x00 0x335 0x01 0x00 0x336 0x01 0x00 0x337 0x01 0x00 0x338 0x01 0x00 0x339 0x01 0x00 0x33a 0x01 0x00 0x33b 0x01 0x00 0x33c 0x01 0x00 0x33d 0x01 0x00 0x33e 0x01 0x00 0x33f 0x01>; | |
| interrupt-parent = <0x01>; | |
| msi-controller; | |
| compatible = "qcom,pci-msi"; | |
| reg = <0x17a10040 0x00>; | |
| phandle = <0x16e>; | |
| }; | |
| qcom,msm-dai-tdm-tert-rx { | |
| qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
| qcom,msm-cpudai-tdm-data-out = <0x00>; | |
| qcom,msm-cpudai-tdm-data-delay = <0x01>; | |
| qcom,msm-cpudai-tdm-group-port-id = <0x9020>; | |
| qcom,msm-cpudai-tdm-group-num-ports = <0x01>; | |
| qcom,msm-cpudai-tdm-invert-sync = <0x01>; | |
| compatible = "qcom,msm-dai-tdm"; | |
| qcom,msm-cpudai-tdm-group-id = <0x9120>; | |
| phandle = <0x5ea>; | |
| qcom,msm-cpudai-tdm-sync-src = <0x01>; | |
| qcom,msm-cpudai-tdm-clk-internal = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-mode = <0x01>; | |
| qcom,msm-dai-q6-tdm-tert-rx-0 { | |
| qcom,msm-cpudai-tdm-dev-id = <0x9020>; | |
| qcom,msm-cpudai-tdm-data-align = <0x00>; | |
| compatible = "qcom,msm-dai-q6-tdm"; | |
| phandle = <0x30d>; | |
| }; | |
| }; | |
| qmi-ts-sensors { | |
| #thermal-sensor-cells = <0x01>; | |
| compatible = "qcom,qmi-sensors"; | |
| phandle = <0x46>; | |
| modem { | |
| qcom,qmi-sensor-names = "pa\0pa_1\0qfe_wtr0\0modem_tsens\0qfe_mmw0\0qfe_mmw1\0qfe_mmw2\0qfe_mmw3\0xo_therm\0qfe_mmw_streamer0\0qfe_mmw0_mod\0qfe_mmw1_mod\0qfe_mmw2_mod\0qfe_mmw3_mod\0qfe_ret_pa0\0qfe_wtr_pa0\0qfe_wtr_pa1\0qfe_wtr_pa2\0qfe_wtr_pa3\0sys_therm1\0sys_therm2\0modem_tsens1"; | |
| qcom,instance-id = <0x64>; | |
| }; | |
| }; | |
| qcom,msm-pcm-hostless { | |
| compatible = "qcom,msm-pcm-hostless"; | |
| phandle = <0x2e7>; | |
| }; | |
| cti@6b01000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti-swao_cti1"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6b01000 0x1000>; | |
| phandle = <0x53f>; | |
| }; | |
| restart@c264000 { | |
| reg-names = "pshold-base\0tcsr-boot-misc-detect"; | |
| compatible = "qcom,pshold"; | |
| reg = <0xc264000 0x04 0x1fd3000 0x04>; | |
| }; | |
| tpdm@69810000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-tpdm-turing-llm"; | |
| compatible = "arm,primecell"; | |
| status = "disabled"; | |
| reg = <0x6981000 0x1000>; | |
| phandle = <0x1f3>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x224>; | |
| phandle = <0x221>; | |
| }; | |
| }; | |
| }; | |
| spi@a84000 { | |
| pinctrl-names = "default\0sleep"; | |
| #address-cells = <0x01>; | |
| pinctrl-0 = <0x2b2>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| reg-names = "se_phys"; | |
| interrupts = <0x00 0x162 0x04>; | |
| clocks = <0x16 0x6c 0x16 0x86 0x16 0x87>; | |
| #size-cells = <0x00>; | |
| qcom,wrapper-core = <0x2a3>; | |
| spi-max-frequency = <0x2faf080>; | |
| dma-names = "tx\0rx"; | |
| compatible = "qcom,spi-geni"; | |
| pinctrl-1 = <0x2b3>; | |
| status = "disabled"; | |
| reg = <0xa84000 0x4000>; | |
| phandle = <0x5b8>; | |
| dmas = <0x2a4 0x00 0x01 0x01 0x40 0x00 0x2a4 0x01 0x01 0x01 0x40 0x00>; | |
| }; | |
| qcom,npu-npu-llcc-bw { | |
| qcom,src-dst-ports = <0x9a 0x302>; | |
| governor = "performance"; | |
| compatible = "qcom,devbw"; | |
| phandle = <0x50>; | |
| operating-points-v2 = <0x4f>; | |
| }; | |
| etm@7040000 { | |
| arm,primecell-periphid = <0xbb95d>; | |
| clock-names = "apb_pclk"; | |
| clocks = <0x49 0x00>; | |
| cpu = <0x0d>; | |
| qcom,tupwr-disable; | |
| coresight-name = "coresight-etm0"; | |
| compatible = "arm,primecell"; | |
| reg = <0x7040000 0x1000>; | |
| phandle = <0x547>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x23b>; | |
| phandle = <0x244>; | |
| }; | |
| }; | |
| }; | |
| tpdm@6870000 { | |
| arm,primecell-periphid = <0x3b968>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x49 0x00>; | |
| qcom,hw-enable-check; | |
| coresight-name = "coresight-tpdm-dcc"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6870000 0x1000>; | |
| phandle = <0x4ed>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x1c8>; | |
| phandle = <0x1c4>; | |
| }; | |
| }; | |
| }; | |
| pinctrl@f000000 { | |
| wakeup-parent = <0x76>; | |
| irqdomain-map-pass-thru = <0x00 0xff>; | |
| gpio-controller; | |
| interrupts = <0x00 0xd0 0x04>; | |
| compatible = "qcom,kona-pinctrl"; | |
| irqdomain-map-mask = <0xff 0x00>; | |
| #interrupt-cells = <0x02>; | |
| reg = <0xf000000 0x1000000>; | |
| phandle = <0x66>; | |
| #gpio-cells = <0x02>; | |
| irqdomain-map = <0x00 0x00 0x76 0x4f 0x00 0x01 0x00 0x76 0x54 0x00 0x02 0x00 0x76 0x50 0x00 0x03 0x00 0x76 0x52 0x00 0x04 0x00 0x76 0x6b 0x00 0x07 0x00 0x76 0x2b 0x00 0x0b 0x00 0x76 0x2a 0x00 0x0e 0x00 0x76 0x2c 0x00 0x0f 0x00 0x76 0x34 0x00 0x13 0x00 0x76 0x43 0x00 0x17 0x00 0x76 0x44 0x00 0x18 0x00 0x76 0x69 0x00 0x1b 0x00 0x76 0x5c 0x00 0x1c 0x00 0x76 0x6a 0x00 0x1f 0x00 0x76 0x45 0x00 0x23 0x00 0x76 0x46 0x00 0x27 0x00 0x76 0x49 0x00 0x28 0x00 0x76 0x6c 0x00 0x2b 0x00 0x76 0x47 0x00 0x2d 0x00 0x76 0x48 0x00 0x2f 0x00 0x76 0x53 0x00 0x33 0x00 0x76 0x4a 0x00 0x37 0x00 0x76 0x4d 0x00 0x3b 0x00 0x76 0x4e 0x00 0x3f 0x00 0x76 0x4b 0x00 0x40 0x00 0x76 0x51 0x00 0x41 0x00 0x76 0x57 0x00 0x42 0x00 0x76 0x58 0x00 0x43 0x00 0x76 0x59 0x00 0x44 0x00 0x76 0x36 0x00 0x46 0x00 0x76 0x55 0x00 0x4d 0x00 0x76 0x2e 0x00 0x50 0x00 0x76 0x5a 0x00 0x51 0x00 0x76 0x5b 0x00 0x53 0x00 0x76 0x61 0x00 0x54 0x00 0x76 0x62 0x00 0x56 0x00 0x76 0x63 0x00 0x58 0x00 0x76 0x65 0x00 0x59 0x00 0x76 0x66 0x00 0x5c 0x00 0x76 0x67 0x00 0x5d 0x00 0x76 0x68 0x00 0x64 0x00 0x76 0x35 0x00 0x67 0x00 0x76 0x2f 0x00 0x68 0x00 0x76 0x30 0x00 0x6c 0x00 0x76 0x31 0x00 0x6d 0x00 0x76 0x5e 0x00 0x6e 0x00 0x76 0x5f 0x00 0x6f 0x00 0x76 0x60 0x00 0x70 0x00 0x76 0x37 0x00 0x71 0x00 0x76 0x38 0x00 0x76 0x00 0x76 0x32 0x00 0x79 0x00 0x76 0x33 0x00 0x7a 0x00 0x76 0x39 0x00 0x7b 0x00 0x76 0x3a 0x00 0x7c 0x00 0x76 0x2d 0x00 0x7e 0x00 0x76 0x3b 0x00 0x80 0x00 0x76 0x4c 0x00 0x81 0x00 0x76 0x56 0x00 0x84 0x00 0x76 0x5d 0x00 0x85 0x00 0x76 0x41 0x00 0x86 0x00 0x76 0x42 0x00 0x88 0x00 0x76 0x3e 0x00 0x89 0x00 0x76 0x3f 0x00 0x8a 0x00 0x76 0x40 0x00 0x8e 0x00 0x76 0x3c 0x00 0x8f 0x00 0x76 0x3d 0x00 0x93 0x00 0x76 0x6d 0x00 0x96 0x00 0x76 0x6e 0x00 0x9d 0x00 0x76 0x6f 0x00 0x9e 0x00 0x76 0x70 0x00 0xa0 0x00 0x76 0x71 0x00 0xa2 0x00 0x76 0x72 0x00 0xa4 0x00 0x76 0x73 0x00 0xa6 0x00 0x76 0x74 0x00 0xa7 0x00 0x76 0x75 0x00 0xaf 0x00 0x76 0x76 0x00 0xb1 0x00 0x76 0x77 0x00 0xb3 0x00 0x76 0x78 0x00>; | |
| interrupt-controller; | |
| cam_sensor_6dof_vana_suspend { | |
| phandle = <0x488>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio84"; | |
| }; | |
| config { | |
| pins = "gpio84"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| wcd938x_reset_sleep { | |
| phandle = <0x468>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio32"; | |
| }; | |
| config { | |
| pins = "gpio32"; | |
| drive-strength = <0x10>; | |
| bias-disable; | |
| output-low; | |
| }; | |
| }; | |
| pmx_ts_int_suspend { | |
| ts_int_suspend { | |
| phandle = <0x3f6>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio39"; | |
| }; | |
| config { | |
| pins = "gpio39"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| }; | |
| tert_mi2s_sd1 { | |
| tert_mi2s_sd1_active { | |
| phandle = <0x462>; | |
| mux { | |
| function = "mi2s2_data1"; | |
| pins = "gpio137"; | |
| }; | |
| config { | |
| pins = "gpio137"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| }; | |
| }; | |
| tert_mi2s_sd1_sleep { | |
| phandle = <0x461>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio137"; | |
| }; | |
| config { | |
| pins = "gpio137"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| tert_tdm_din { | |
| tert_tdm_din_active { | |
| phandle = <0x444>; | |
| mux { | |
| function = "mi2s2_data0"; | |
| pins = "gpio134"; | |
| }; | |
| config { | |
| pins = "gpio134"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| }; | |
| }; | |
| tert_tdm_din_sleep { | |
| phandle = <0x443>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio134"; | |
| }; | |
| config { | |
| pins = "gpio134"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_rgb_vdig_suspend { | |
| phandle = <0x496>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio115"; | |
| }; | |
| config { | |
| pins = "gpio115"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| tert_aux_pcm { | |
| tert_aux_pcm_clk_active { | |
| phandle = <0x428>; | |
| mux { | |
| function = "mi2s2_sck"; | |
| pins = "gpio133"; | |
| }; | |
| config { | |
| pins = "gpio133"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| tert_aux_pcm_clk_sleep { | |
| phandle = <0x427>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio133"; | |
| }; | |
| config { | |
| pins = "gpio133"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| tert_aux_pcm_ws_sleep { | |
| phandle = <0x429>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio135"; | |
| }; | |
| config { | |
| pins = "gpio135"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| tert_aux_pcm_ws_active { | |
| phandle = <0x42a>; | |
| mux { | |
| function = "mi2s2_ws"; | |
| pins = "gpio135"; | |
| }; | |
| config { | |
| pins = "gpio135"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| cci3_active { | |
| phandle = <0x259>; | |
| mux { | |
| function = "cci_i2c"; | |
| pins = "gpio107\0gpio108"; | |
| }; | |
| config { | |
| pins = "gpio107\0gpio108"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| cam_sensor_active_3 { | |
| phandle = <0x47d>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio109"; | |
| }; | |
| config { | |
| pins = "gpio109"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| sdc2_cmd_on { | |
| phandle = <0x400>; | |
| config { | |
| pins = "sdc2_cmd"; | |
| drive-strength = <0x10>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| sec_tdm_dout { | |
| sec_tdm_dout_active { | |
| phandle = <0x43e>; | |
| mux { | |
| function = "mi2s1_data1"; | |
| pins = "gpio144"; | |
| }; | |
| config { | |
| pins = "gpio144"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| }; | |
| }; | |
| sec_tdm_dout_sleep { | |
| phandle = <0x43d>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio144"; | |
| }; | |
| config { | |
| pins = "gpio144"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_suspend_6dofleft { | |
| phandle = <0x49c>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio130"; | |
| }; | |
| config { | |
| pins = "gpio130"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| output-low; | |
| }; | |
| }; | |
| qupv3_se15_spi_pins { | |
| phandle = <0x4d1>; | |
| qupv3_se15_spi_active { | |
| phandle = <0x2d4>; | |
| mux { | |
| function = "qup15"; | |
| pins = "gpio44\0gpio45\0gpio46\0gpio47"; | |
| }; | |
| config { | |
| pins = "gpio44\0gpio45\0gpio46\0gpio47"; | |
| drive-strength = <0x06>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se15_spi_sleep { | |
| phandle = <0x2d5>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio44\0gpio45\0gpio46\0gpio47"; | |
| }; | |
| config { | |
| pins = "gpio44\0gpio45\0gpio46\0gpio47"; | |
| drive-strength = <0x06>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| qupv3_se6_spi_pins { | |
| phandle = <0x4bb>; | |
| qupv3_se6_spi_sleep { | |
| phandle = <0x29e>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio16\0gpio17\0gpio18\0gpio19"; | |
| }; | |
| config { | |
| pins = "gpio16\0gpio17\0gpio18\0gpio19"; | |
| drive-strength = <0x06>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se6_spi_active { | |
| phandle = <0x29d>; | |
| mux { | |
| function = "qup6"; | |
| pins = "gpio16\0gpio17\0gpio18\0gpio19"; | |
| }; | |
| config { | |
| pins = "gpio16\0gpio17\0gpio18\0gpio19"; | |
| drive-strength = <0x06>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_suspend_5 { | |
| phandle = <0x482>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio131"; | |
| }; | |
| config { | |
| pins = "gpio131"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| output-low; | |
| }; | |
| }; | |
| sec_mi2s_mclk { | |
| sec_mi2s_mclk_sleep { | |
| phandle = <0x451>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio137"; | |
| }; | |
| config { | |
| pins = "gpio137"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| sec_mi2s_mclk_active { | |
| phandle = <0x452>; | |
| mux { | |
| function = "sec_mi2s"; | |
| pins = "gpio137"; | |
| }; | |
| config { | |
| pins = "gpio137"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| qupv3_se11_i2c_pins { | |
| phandle = <0x4c0>; | |
| qupv3_se11_i2c_active { | |
| phandle = <0x2ab>; | |
| mux { | |
| function = "qup11"; | |
| pins = "gpio60\0gpio61"; | |
| }; | |
| config { | |
| pins = "gpio60\0gpio61"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se11_i2c_sleep { | |
| phandle = <0x2ac>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio60\0gpio61"; | |
| }; | |
| config { | |
| pins = "gpio60\0gpio61"; | |
| drive-strength = <0x02>; | |
| bias-no-pull; | |
| }; | |
| }; | |
| }; | |
| sdc2_cmd_ds_50MHz { | |
| phandle = <0x403>; | |
| config { | |
| pins = "sdc2_cmd"; | |
| drive-strength = <0x10>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| qupv3_se2_i2c_pins { | |
| phandle = <0x4af>; | |
| qupv3_se2_i2c_sleep { | |
| phandle = <0x286>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio115\0gpio116"; | |
| }; | |
| config { | |
| pins = "gpio115\0gpio116"; | |
| drive-strength = <0x02>; | |
| bias-no-pull; | |
| }; | |
| }; | |
| qupv3_se2_i2c_active { | |
| phandle = <0x285>; | |
| mux { | |
| function = "qup2"; | |
| pins = "gpio115\0gpio116"; | |
| }; | |
| config { | |
| pins = "gpio115\0gpio116"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| sdc2_data_on { | |
| phandle = <0x406>; | |
| config { | |
| pins = "sdc2_data"; | |
| drive-strength = <0x10>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| wil6210_refclk_en_pin { | |
| phandle = <0xae>; | |
| mux { | |
| function = "gpio"; | |
| }; | |
| config { | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| sde_led_driver_en2_gpio { | |
| phandle = <0x486>; | |
| mux { | |
| function = "gpio"; | |
| }; | |
| config { | |
| drive-strength = <0x10>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| cs35l41_reset_default { | |
| phandle = <0x687>; | |
| config { | |
| pins = "gpio131"; | |
| drive-strength = <0x10>; | |
| output-high; | |
| bias-pull-up; | |
| }; | |
| }; | |
| cam_sensor_mclk6_suspend { | |
| phandle = <0x476>; | |
| mux { | |
| function = "cam_mclk"; | |
| pins = "gpio100"; | |
| }; | |
| config { | |
| pins = "gpio100"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| tsif1_sync_active { | |
| phandle = <0xb3>; | |
| tsif2_sync { | |
| function = "tsif1_sync"; | |
| pins = "gpio76"; | |
| drive_strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| cam_sensor_suspend_rgbleft { | |
| phandle = <0x4a2>; | |
| mux { | |
| }; | |
| config { | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| output-low; | |
| }; | |
| }; | |
| tert_mi2s_ws { | |
| tert_mi2s_ws_sleep { | |
| phandle = <0x45d>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio135"; | |
| }; | |
| config { | |
| pins = "gpio135"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| tert_mi2s_ws_active { | |
| phandle = <0x45e>; | |
| mux { | |
| function = "mi2s2_ws"; | |
| pins = "gpio135"; | |
| }; | |
| config { | |
| pins = "gpio135"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| pri_tdm_dout { | |
| pri_tdm_dout_active { | |
| phandle = <0x436>; | |
| mux { | |
| function = "mi2s0_data1"; | |
| pins = "gpio140"; | |
| }; | |
| config { | |
| pins = "gpio140"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| }; | |
| }; | |
| pri_tdm_dout_sleep { | |
| phandle = <0x435>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio140"; | |
| }; | |
| config { | |
| pins = "gpio140"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_rgb_vio_active { | |
| phandle = <0x493>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio116"; | |
| }; | |
| config { | |
| pins = "gpio116"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| bt_en_sleep { | |
| phandle = <0x4a3>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio21"; | |
| }; | |
| config { | |
| pins = "gpio21"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| output-low; | |
| }; | |
| }; | |
| ufs_dev_reset_assert { | |
| phandle = <0x78>; | |
| config { | |
| pins = "ufs_reset"; | |
| drive-strength = <0x08>; | |
| bias-pull-down; | |
| output-low; | |
| }; | |
| }; | |
| qupv3_se1_i3c_pins { | |
| phandle = <0x4a5>; | |
| qupv3_se1_i3c_sleep { | |
| phandle = <0x276>; | |
| mux { | |
| function = "ibi_i3c"; | |
| pins = "gpio4\0gpio5"; | |
| }; | |
| config { | |
| pins = "gpio4\0gpio5"; | |
| drive-strength = <0x10>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| qupv3_se1_i3c_disable { | |
| phandle = <0x277>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio4\0gpio5"; | |
| }; | |
| config { | |
| pins = "gpio4\0gpio5"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| qupv3_se1_i3c_active { | |
| phandle = <0x275>; | |
| mux { | |
| function = "ibi_i3c"; | |
| pins = "gpio4\0gpio5"; | |
| }; | |
| config { | |
| pins = "gpio4\0gpio5"; | |
| drive-strength = <0x10>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_suspend_3 { | |
| phandle = <0x47e>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio109"; | |
| }; | |
| config { | |
| pins = "gpio109"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| output-low; | |
| }; | |
| }; | |
| sec_mi2s_sd1 { | |
| sec_mi2s_sd1_active { | |
| phandle = <0x45a>; | |
| mux { | |
| function = "mi2s1_data1"; | |
| pins = "gpio144"; | |
| }; | |
| config { | |
| pins = "gpio144"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| }; | |
| }; | |
| sec_mi2s_sd1_sleep { | |
| phandle = <0x459>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio144"; | |
| }; | |
| config { | |
| pins = "gpio144"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| qupv3_se16_i2c_pins { | |
| phandle = <0x4cc>; | |
| qupv3_se16_i2c_active { | |
| phandle = <0x2ca>; | |
| mux { | |
| function = "qup16"; | |
| pins = "gpio48\0gpio49"; | |
| }; | |
| config { | |
| pins = "gpio48\0gpio49"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se16_i2c_sleep { | |
| phandle = <0x2cb>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio48\0gpio49"; | |
| }; | |
| config { | |
| pins = "gpio48\0gpio49"; | |
| drive-strength = <0x02>; | |
| bias-no-pull; | |
| }; | |
| }; | |
| }; | |
| pri_tdm_sync { | |
| pri_tdm_sync_active { | |
| phandle = <0x432>; | |
| mux { | |
| function = "mi2s0_ws"; | |
| pins = "gpio141"; | |
| }; | |
| config { | |
| pins = "gpio141"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| pri_tdm_sync_sleep { | |
| phandle = <0x431>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio141"; | |
| }; | |
| config { | |
| pins = "gpio141"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| qupv3_se11_spi_pins { | |
| phandle = <0x4c7>; | |
| qupv3_se11_spi_sleep { | |
| phandle = <0x2b7>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio60\0gpio61\0gpio62\0gpio63"; | |
| }; | |
| config { | |
| pins = "gpio60\0gpio61\0gpio62\0gpio63"; | |
| drive-strength = <0x06>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se11_spi_active { | |
| phandle = <0x2b6>; | |
| mux { | |
| function = "qup11"; | |
| pins = "gpio60\0gpio61\0gpio62\0gpio63"; | |
| }; | |
| config { | |
| pins = "gpio60\0gpio61\0gpio62\0gpio63"; | |
| drive-strength = <0x06>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| qupv3_se7_i2c_pins { | |
| phandle = <0x4b4>; | |
| qupv3_se7_i2c_sleep { | |
| phandle = <0x290>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio20\0gpio21"; | |
| }; | |
| config { | |
| pins = "gpio20\0gpio21"; | |
| drive-strength = <0x02>; | |
| bias-no-pull; | |
| }; | |
| }; | |
| qupv3_se7_i2c_active { | |
| phandle = <0x28f>; | |
| mux { | |
| function = "qup7"; | |
| pins = "gpio20\0gpio21"; | |
| }; | |
| config { | |
| pins = "gpio20\0gpio21"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| qupv3_se2_spi_pins { | |
| phandle = <0x4b7>; | |
| qupv3_se2_spi_sleep { | |
| phandle = <0x296>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio115\0gpio116\0gpio117\0gpio118"; | |
| }; | |
| config { | |
| pins = "gpio115\0gpio116\0gpio117\0gpio118"; | |
| drive-strength = <0x06>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se2_spi_active { | |
| phandle = <0x295>; | |
| mux { | |
| function = "qup2"; | |
| pins = "gpio115\0gpio116\0gpio117\0gpio118"; | |
| }; | |
| config { | |
| pins = "gpio115\0gpio116\0gpio117\0gpio118"; | |
| drive-strength = <0x06>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_et_vana_active { | |
| phandle = <0x48d>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio114"; | |
| }; | |
| config { | |
| pins = "gpio114"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| sdc2_cmd_ds_200MHz { | |
| phandle = <0x405>; | |
| config { | |
| pins = "sdc2_cmd"; | |
| drive-strength = <0x10>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| cam_sensor_et_vio_active { | |
| phandle = <0x48f>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio145"; | |
| }; | |
| config { | |
| pins = "gpio145"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| cam_sensor_suspend_etright { | |
| phandle = <0x49a>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio92"; | |
| }; | |
| config { | |
| pins = "gpio92"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| output-low; | |
| }; | |
| }; | |
| sdc2_clk_ds_50MHz { | |
| phandle = <0x3fd>; | |
| config { | |
| pins = "sdc2_clk"; | |
| drive-strength = <0x10>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se2_2uart_pins { | |
| phandle = <0x3f0>; | |
| qupv3_se2_2uart_active { | |
| phandle = <0x278>; | |
| mux { | |
| function = "qup2"; | |
| pins = "gpio117\0gpio118"; | |
| }; | |
| config { | |
| pins = "gpio117\0gpio118"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se2_2uart_sleep { | |
| phandle = <0x279>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio117\0gpio118"; | |
| }; | |
| config { | |
| pins = "gpio117\0gpio118"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| }; | |
| sdc2_data_ds_200MHz { | |
| phandle = <0x40b>; | |
| config { | |
| pins = "sdc2_data"; | |
| drive-strength = <0x10>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| pri_mi2s_sd1 { | |
| pri_mi2s_sd1_sleep { | |
| phandle = <0x44f>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio140"; | |
| }; | |
| config { | |
| pins = "gpio140"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| pri_mi2s_sd1_active { | |
| phandle = <0x450>; | |
| mux { | |
| function = "mi2s0_data1"; | |
| pins = "gpio140"; | |
| }; | |
| config { | |
| pins = "gpio140"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| sde_led_driver_en1_gpio { | |
| phandle = <0x485>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio144"; | |
| }; | |
| config { | |
| pins = "gpio144"; | |
| drive-strength = <0x10>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| cam_sensor_active_rear_aux { | |
| phandle = <0x479>; | |
| mux { | |
| function = "gpio"; | |
| }; | |
| config { | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| pcie2 { | |
| pcie2_perst_default { | |
| phandle = <0x176>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio85"; | |
| }; | |
| config { | |
| pins = "gpio85"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| pcie2_wake_default { | |
| phandle = <0x177>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio87"; | |
| }; | |
| config { | |
| pins = "gpio87"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| pcie2_clkreq_default { | |
| phandle = <0x175>; | |
| mux { | |
| function = "pci_e2"; | |
| pins = "gpio86"; | |
| }; | |
| config { | |
| pins = "gpio86"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| }; | |
| qupv3_se16_spi_pins { | |
| phandle = <0x4d2>; | |
| qupv3_se16_spi_sleep { | |
| phandle = <0x2d7>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio48\0gpio49\0gpio50\0gpio51"; | |
| }; | |
| config { | |
| pins = "gpio48\0gpio49\0gpio50\0gpio51"; | |
| drive-strength = <0x06>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se16_spi_active { | |
| phandle = <0x2d6>; | |
| mux { | |
| function = "qup16"; | |
| pins = "gpio48\0gpio49\0gpio50\0gpio51"; | |
| }; | |
| config { | |
| pins = "gpio48\0gpio49\0gpio50\0gpio51"; | |
| drive-strength = <0x06>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| sdc2_clk_off { | |
| phandle = <0x3fb>; | |
| config { | |
| pins = "sdc2_clk"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se7_spi_pins { | |
| phandle = <0x4bc>; | |
| qupv3_se7_spi_sleep { | |
| phandle = <0x2a0>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio20\0gpio21\0gpio22\0gpio23"; | |
| }; | |
| config { | |
| pins = "gpio20\0gpio21\0gpio22\0gpio23"; | |
| drive-strength = <0x06>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se7_spi_active { | |
| phandle = <0x29f>; | |
| mux { | |
| function = "qup7"; | |
| pins = "gpio20\0gpio21\0gpio22\0gpio23"; | |
| }; | |
| config { | |
| pins = "gpio20\0gpio21\0gpio22\0gpio23"; | |
| drive-strength = <0x06>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| pri_aux_pcm_dout { | |
| pri_aux_pcm_dout_sleep { | |
| phandle = <0x41d>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio140"; | |
| }; | |
| config { | |
| pins = "gpio140"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| pri_aux_pcm_dout_active { | |
| phandle = <0x41e>; | |
| mux { | |
| function = "mi2s0_data1"; | |
| pins = "gpio140"; | |
| }; | |
| config { | |
| pins = "gpio140"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_mclk1_suspend { | |
| phandle = <0x46c>; | |
| mux { | |
| function = "cam_mclk"; | |
| pins = "gpio95"; | |
| }; | |
| config { | |
| pins = "gpio95"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| cam_sensor_active_rgbright { | |
| phandle = <0x49f>; | |
| mux { | |
| }; | |
| config { | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se6_4uart_pins { | |
| phandle = <0x3f1>; | |
| qupv3_se6_default_tx { | |
| phandle = <0x27c>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio18"; | |
| }; | |
| config { | |
| pins = "gpio18"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| qupv3_se6_default_cts { | |
| phandle = <0x27a>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio16"; | |
| }; | |
| config { | |
| pins = "gpio16"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se6_rts { | |
| phandle = <0x27e>; | |
| mux { | |
| function = "qup6"; | |
| pins = "gpio17"; | |
| }; | |
| config { | |
| pins = "gpio17"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| qupv3_se6_tx { | |
| phandle = <0x27f>; | |
| mux { | |
| function = "qup6"; | |
| pins = "gpio18"; | |
| }; | |
| config { | |
| pins = "gpio18"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| qupv3_se6_default_rtsrx { | |
| phandle = <0x27b>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio17\0gpio19"; | |
| }; | |
| config { | |
| pins = "gpio17\0gpio19"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| qupv3_se6_ctsrx { | |
| phandle = <0x27d>; | |
| mux { | |
| function = "qup6"; | |
| pins = "gpio16\0gpio19"; | |
| }; | |
| config { | |
| pins = "gpio16\0gpio19"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_suspend_rst2 { | |
| phandle = <0x47c>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio78"; | |
| }; | |
| config { | |
| pins = "gpio78"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| output-low; | |
| }; | |
| }; | |
| qupv3_se12_i2c_pins { | |
| phandle = <0x4c1>; | |
| qupv3_se12_i2c_sleep { | |
| phandle = <0x2ae>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio32\0gpio33"; | |
| }; | |
| config { | |
| pins = "gpio32\0gpio33"; | |
| drive-strength = <0x02>; | |
| bias-no-pull; | |
| }; | |
| }; | |
| qupv3_se12_i2c_active { | |
| phandle = <0x2ad>; | |
| mux { | |
| function = "qup12"; | |
| pins = "gpio32\0gpio33"; | |
| }; | |
| config { | |
| pins = "gpio32\0gpio33"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| display_panel_avdd_default { | |
| phandle = <0x63b>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio61"; | |
| }; | |
| config { | |
| pins = "gpio61"; | |
| drive-strength = <0x08>; | |
| bias-disable = <0x00>; | |
| output-high; | |
| }; | |
| }; | |
| sdc2_cmd_off { | |
| phandle = <0x401>; | |
| config { | |
| pins = "sdc2_cmd"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| qupv3_se3_i2c_pins { | |
| phandle = <0x4b0>; | |
| qupv3_se3_i2c_active { | |
| phandle = <0x287>; | |
| mux { | |
| function = "qup3"; | |
| pins = "gpio119\0gpio120"; | |
| }; | |
| config { | |
| pins = "gpio119\0gpio120"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se3_i2c_sleep { | |
| phandle = <0x288>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio119\0gpio120"; | |
| }; | |
| config { | |
| pins = "gpio119\0gpio120"; | |
| drive-strength = <0x02>; | |
| bias-no-pull; | |
| }; | |
| }; | |
| }; | |
| ap2mdm { | |
| ap2mdm_sleep { | |
| phandle = <0x64>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio56\0gpio57"; | |
| }; | |
| config { | |
| pins = "gpio56\0gpio57"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| }; | |
| }; | |
| ap2mdm_active { | |
| phandle = <0x62>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio56\0gpio57"; | |
| }; | |
| config { | |
| pins = "gpio56\0gpio57"; | |
| drive-strength = <0x10>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| nfc { | |
| nfc_int_suspend { | |
| phandle = <0x4aa>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio111"; | |
| }; | |
| config { | |
| pins = "gpio111"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| nfc_enable_active { | |
| phandle = <0x4ab>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio6\0gpio110"; | |
| }; | |
| config { | |
| pins = "gpio6\0gpio110"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| nfc_int_active { | |
| phandle = <0x4a9>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio111"; | |
| }; | |
| config { | |
| pins = "gpio111"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| nfc_enable_suspend { | |
| phandle = <0x4ac>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio6\0gpio110"; | |
| }; | |
| config { | |
| pins = "gpio6\0gpio110"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| nfc_clk_req_active { | |
| phandle = <0x4ad>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio7"; | |
| }; | |
| config { | |
| pins = "gpio7"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| nfc_clk_req_suspend { | |
| phandle = <0x4ae>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio7"; | |
| }; | |
| config { | |
| pins = "gpio7"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| cs35l41_4_irq_default { | |
| phandle = <0x68a>; | |
| config { | |
| pins = "gpio68"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| pri_aux_pcm_sync { | |
| pri_aux_pcm_sync_active { | |
| phandle = <0x41a>; | |
| mux { | |
| function = "mi2s0_ws"; | |
| pins = "gpio141"; | |
| }; | |
| config { | |
| pins = "gpio141"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| pri_aux_pcm_sync_sleep { | |
| phandle = <0x419>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio141"; | |
| }; | |
| config { | |
| pins = "gpio141"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| tsif1_signals_active { | |
| phandle = <0xb2>; | |
| tsif2_clk { | |
| function = "tsif1_clk"; | |
| pins = "gpio73"; | |
| }; | |
| signals_cfg { | |
| pins = "gpio73\0gpio74\0gpio75"; | |
| drive_strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| tsif2_en { | |
| function = "tsif1_en"; | |
| pins = "gpio74"; | |
| }; | |
| tsif2_data { | |
| function = "tsif1_data"; | |
| pins = "gpio75"; | |
| }; | |
| }; | |
| pri_tdm_clk { | |
| pri_tdm_clk_active { | |
| phandle = <0x430>; | |
| mux { | |
| function = "mi2s0_sck"; | |
| pins = "gpio138"; | |
| }; | |
| config { | |
| pins = "gpio138"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| pri_tdm_clk_sleep { | |
| phandle = <0x42f>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio138"; | |
| }; | |
| config { | |
| pins = "gpio138"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| cs35l41_2_irq_default { | |
| phandle = <0x688>; | |
| config { | |
| pins = "gpio113"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| sdc2_cmd_ds_100MHz { | |
| phandle = <0x404>; | |
| config { | |
| pins = "sdc2_cmd"; | |
| drive-strength = <0x10>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| sec_aux_pcm_din { | |
| sec_aux_pcm_din_active { | |
| phandle = <0x424>; | |
| mux { | |
| function = "mi2s1_data0"; | |
| pins = "gpio143"; | |
| }; | |
| config { | |
| pins = "gpio143"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| }; | |
| }; | |
| sec_aux_pcm_din_sleep { | |
| phandle = <0x423>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio143"; | |
| }; | |
| config { | |
| pins = "gpio143"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| pcie0 { | |
| pcie0_perst_default { | |
| phandle = <0x168>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio79"; | |
| }; | |
| config { | |
| pins = "gpio79"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| pcie0_clkreq_default { | |
| phandle = <0x167>; | |
| mux { | |
| function = "pci_e0"; | |
| pins = "gpio80"; | |
| }; | |
| config { | |
| pins = "gpio80"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| pcie0_clkreq_sleep { | |
| phandle = <0x16a>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio80"; | |
| }; | |
| config { | |
| pins = "gpio80"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| pcie0_wake_default { | |
| phandle = <0x169>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio81"; | |
| }; | |
| config { | |
| pins = "gpio81"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| }; | |
| sdc2_data_ds_100MHz { | |
| phandle = <0x40a>; | |
| config { | |
| pins = "sdc2_data"; | |
| drive-strength = <0x10>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| cam_sensor_suspend_rear { | |
| phandle = <0x478>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio93"; | |
| }; | |
| config { | |
| pins = "gpio93"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| output-low; | |
| }; | |
| }; | |
| cam_sensor_rgb_vana_active { | |
| phandle = <0x491>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio117"; | |
| }; | |
| config { | |
| pins = "gpio117"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| cam_sensor_active_6 { | |
| phandle = <0x483>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio114"; | |
| }; | |
| config { | |
| pins = "gpio114"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| pmx_ts_reset_suspend { | |
| ts_reset_suspend { | |
| phandle = <0x3f7>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio38"; | |
| }; | |
| config { | |
| pins = "gpio38"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| }; | |
| qupv3_se17_i2c_pins { | |
| phandle = <0x4cd>; | |
| qupv3_se17_i2c_sleep { | |
| phandle = <0x2cd>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio52\0gpio53"; | |
| }; | |
| config { | |
| pins = "gpio52\0gpio53"; | |
| drive-strength = <0x02>; | |
| bias-no-pull; | |
| }; | |
| }; | |
| qupv3_se17_i2c_active { | |
| phandle = <0x2cc>; | |
| mux { | |
| function = "qup17"; | |
| pins = "gpio52\0gpio53"; | |
| }; | |
| config { | |
| pins = "gpio52\0gpio53"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| qupv3_se12_spi_pins { | |
| phandle = <0x4c8>; | |
| qupv3_se12_spi_active { | |
| phandle = <0x2b8>; | |
| mux { | |
| function = "qup12"; | |
| pins = "gpio32\0gpio33\0gpio34\0gpio35"; | |
| }; | |
| config { | |
| pins = "gpio32\0gpio33\0gpio34\0gpio35"; | |
| drive-strength = <0x06>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se12_spi_sleep { | |
| phandle = <0x2b9>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio32\0gpio33\0gpio34\0gpio35"; | |
| }; | |
| config { | |
| pins = "gpio32\0gpio33\0gpio34\0gpio35"; | |
| drive-strength = <0x06>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| qupv3_se8_i2c_pins { | |
| phandle = <0x4bd>; | |
| qupv3_se8_i2c_active { | |
| phandle = <0x2a5>; | |
| mux { | |
| function = "qup8"; | |
| pins = "gpio24"; | |
| }; | |
| config { | |
| pins = "gpio24"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se8_i2c_sleep { | |
| phandle = <0x2a6>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio24"; | |
| }; | |
| config { | |
| pins = "gpio24"; | |
| drive-strength = <0x02>; | |
| bias-no-pull; | |
| }; | |
| }; | |
| }; | |
| sdc2_clk_on { | |
| phandle = <0x3fa>; | |
| config { | |
| pins = "sdc2_clk"; | |
| drive-strength = <0x10>; | |
| bias-disable; | |
| }; | |
| }; | |
| cam_sensor_et_vana_suspend { | |
| phandle = <0x48e>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio114"; | |
| }; | |
| config { | |
| pins = "gpio114"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| cci1_suspend { | |
| phandle = <0x257>; | |
| mux { | |
| function = "cci_i2c"; | |
| pins = "gpio103\0gpio104"; | |
| }; | |
| config { | |
| pins = "gpio103\0gpio104"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| qupv3_se3_spi_pins { | |
| phandle = <0x4b8>; | |
| qupv3_se3_spi_sleep { | |
| phandle = <0x298>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio119\0gpio120\0gpio121\0gpio122"; | |
| }; | |
| config { | |
| pins = "gpio119\0gpio120\0gpio121\0gpio122"; | |
| drive-strength = <0x06>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se3_spi_active { | |
| phandle = <0x297>; | |
| mux { | |
| function = "qup3"; | |
| pins = "gpio119\0gpio120\0gpio121\0gpio122"; | |
| }; | |
| config { | |
| pins = "gpio119\0gpio120\0gpio121\0gpio122"; | |
| drive-strength = <0x06>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| qupv3_se18_2uart_pins { | |
| phandle = <0x3f4>; | |
| qupv3_se18_tx { | |
| phandle = <0x2c1>; | |
| mux { | |
| function = "qup18"; | |
| pins = "gpio58"; | |
| }; | |
| config { | |
| pins = "gpio58"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| qupv3_se18_rx { | |
| phandle = <0x2c0>; | |
| mux { | |
| function = "qup18"; | |
| pins = "gpio59"; | |
| }; | |
| config { | |
| pins = "gpio59"; | |
| drive-strength = <0x02>; | |
| bias-no-pull; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_mclk3_suspend { | |
| phandle = <0x470>; | |
| mux { | |
| function = "cam_mclk"; | |
| pins = "gpio97"; | |
| }; | |
| config { | |
| pins = "gpio97"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| qupv3_se17_4uart_pins { | |
| phandle = <0x3f3>; | |
| qupv3_se17_ctsrx { | |
| phandle = <0x2bc>; | |
| mux { | |
| function = "qup17"; | |
| pins = "gpio52\0gpio55"; | |
| }; | |
| config { | |
| pins = "gpio52\0gpio55"; | |
| drive-strength = <0x02>; | |
| bias-no-pull; | |
| }; | |
| }; | |
| qupv3_se17_tx { | |
| phandle = <0x2be>; | |
| mux { | |
| function = "qup17"; | |
| pins = "gpio54"; | |
| }; | |
| config { | |
| pins = "gpio54"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| qupv3_se17_rts { | |
| phandle = <0x2bd>; | |
| mux { | |
| function = "qup17"; | |
| pins = "gpio53"; | |
| }; | |
| config { | |
| pins = "gpio53"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| }; | |
| pmx_ts_release { | |
| ts_release { | |
| phandle = <0x3f8>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio38\0gpio39"; | |
| }; | |
| config { | |
| pins = "gpio38\0gpio39"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_active_6dofright { | |
| phandle = <0x49d>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio131"; | |
| }; | |
| config { | |
| pins = "gpio131"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| pri_aux_pcm_clk { | |
| pri_aux_pcm_clk_sleep { | |
| phandle = <0x417>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio138"; | |
| }; | |
| config { | |
| pins = "gpio138"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| pri_aux_pcm_clk_active { | |
| phandle = <0x418>; | |
| mux { | |
| function = "mi2s0_sck"; | |
| pins = "gpio138"; | |
| }; | |
| config { | |
| pins = "gpio138"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| tert_mi2s_sck { | |
| tert_mi2s_sck_active { | |
| phandle = <0x45c>; | |
| mux { | |
| function = "mi2s2_sck"; | |
| pins = "gpio133"; | |
| }; | |
| config { | |
| pins = "gpio133"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| }; | |
| }; | |
| tert_mi2s_sck_sleep { | |
| phandle = <0x45b>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio133"; | |
| }; | |
| config { | |
| pins = "gpio133"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_et_vio_suspend { | |
| phandle = <0x490>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio145"; | |
| }; | |
| config { | |
| pins = "gpio145"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| cam_sensor_suspend_rear_aux { | |
| phandle = <0x47a>; | |
| mux { | |
| function = "gpio"; | |
| }; | |
| config { | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| output-low; | |
| }; | |
| }; | |
| pri_tdm_din { | |
| pri_tdm_din_sleep { | |
| phandle = <0x433>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio139"; | |
| }; | |
| config { | |
| pins = "gpio139"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| pri_tdm_din_active { | |
| phandle = <0x434>; | |
| mux { | |
| function = "mi2s0_data0"; | |
| pins = "gpio139"; | |
| }; | |
| config { | |
| pins = "gpio139"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_active_4 { | |
| phandle = <0x47f>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio130"; | |
| }; | |
| config { | |
| pins = "gpio130"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se17_spi_pins { | |
| phandle = <0x4d3>; | |
| qupv3_se17_spi_active { | |
| phandle = <0x2d8>; | |
| mux { | |
| function = "qup17"; | |
| pins = "gpio52\0gpio53\0gpio54\0gpio55"; | |
| }; | |
| config { | |
| pins = "gpio52\0gpio53\0gpio54\0gpio55"; | |
| drive-strength = <0x06>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se17_spi_sleep { | |
| phandle = <0x2d9>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio52\0gpio53\0gpio54\0gpio55"; | |
| }; | |
| config { | |
| pins = "gpio52\0gpio53\0gpio54\0gpio55"; | |
| drive-strength = <0x06>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| sdc2_cmd_ds_400KHz { | |
| phandle = <0x402>; | |
| config { | |
| pins = "sdc2_cmd"; | |
| drive-strength = <0x10>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| cam_sensor_suspend_rgbright { | |
| phandle = <0x4a0>; | |
| mux { | |
| }; | |
| config { | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| output-low; | |
| }; | |
| }; | |
| cam_sensor_6dof_vdig_suspend { | |
| phandle = <0x48a>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio82"; | |
| }; | |
| config { | |
| pins = "gpio82"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| qupv3_se8_spi_pins { | |
| phandle = <0x4c3>; | |
| qupv3_se8_spi_sleep { | |
| phandle = <0x4c4>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio24\0gpio26\0gpio27"; | |
| }; | |
| config { | |
| pins = "gpio24\0gpio26\0gpio27"; | |
| drive-strength = <0x06>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se8_spi_active { | |
| phandle = <0x2b1>; | |
| mux { | |
| function = "qup8"; | |
| pins = "gpio24\0gpio26\0gpio27"; | |
| }; | |
| config { | |
| pins = "gpio24\0gpio26\0gpio27"; | |
| drive-strength = <0x06>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_mclk0_active { | |
| phandle = <0x469>; | |
| mux { | |
| function = "cam_mclk"; | |
| pins = "gpio94"; | |
| }; | |
| config { | |
| pins = "gpio94"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| cam_sensor_rgb_vana_suspend { | |
| phandle = <0x492>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio117"; | |
| }; | |
| config { | |
| pins = "gpio117"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| cam_sensor_suspend_6 { | |
| phandle = <0x484>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio114"; | |
| }; | |
| config { | |
| pins = "gpio114"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| output-low; | |
| }; | |
| }; | |
| sdc2_data_ds_400KHz { | |
| phandle = <0x408>; | |
| config { | |
| pins = "sdc2_data"; | |
| drive-strength = <0x10>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| qupv3_se13_i2c_pins { | |
| phandle = <0x4c2>; | |
| qupv3_se13_i2c_sleep { | |
| phandle = <0x2b0>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio36\0gpio37"; | |
| }; | |
| config { | |
| pins = "gpio36\0gpio37"; | |
| drive-strength = <0x02>; | |
| bias-no-pull; | |
| }; | |
| }; | |
| qupv3_se13_i2c_active { | |
| phandle = <0x2af>; | |
| mux { | |
| function = "qup13"; | |
| pins = "gpio36\0gpio37"; | |
| }; | |
| config { | |
| pins = "gpio36\0gpio37"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_rgb_vdig_active { | |
| phandle = <0x495>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio115"; | |
| }; | |
| config { | |
| pins = "gpio115"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se4_i2c_pins { | |
| phandle = <0x4b1>; | |
| qupv3_se4_i2c_active { | |
| phandle = <0x289>; | |
| mux { | |
| function = "qup4"; | |
| pins = "gpio8\0gpio9"; | |
| }; | |
| config { | |
| pins = "gpio8\0gpio9"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se4_i2c_sleep { | |
| phandle = <0x28a>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio8\0gpio9"; | |
| }; | |
| config { | |
| pins = "gpio8\0gpio9"; | |
| drive-strength = <0x02>; | |
| bias-no-pull; | |
| }; | |
| }; | |
| }; | |
| tsif0_signals_active { | |
| phandle = <0xb0>; | |
| tsif1_data { | |
| function = "tsif0_data"; | |
| pins = "gpio71"; | |
| }; | |
| signals_cfg { | |
| pins = "gpio69\0gpio70\0gpio71"; | |
| drive_strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| tsif1_en { | |
| function = "tsif0_en"; | |
| pins = "gpio70"; | |
| }; | |
| tsif1_clk { | |
| function = "tsif0_clk"; | |
| pins = "gpio69"; | |
| }; | |
| }; | |
| cci3_suspend { | |
| phandle = <0x25b>; | |
| mux { | |
| function = "cci_i2c"; | |
| pins = "gpio107\0gpio108"; | |
| }; | |
| config { | |
| pins = "gpio107\0gpio108"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| pmx_sde_te { | |
| sde_te_suspend { | |
| phandle = <0x414>; | |
| mux { | |
| function = "mdp_vsync"; | |
| pins = "gpio66"; | |
| }; | |
| config { | |
| pins = "gpio66"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| sde_te1_active { | |
| phandle = <0x415>; | |
| mux { | |
| function = "mdp_vsync"; | |
| pins = "gpio67"; | |
| }; | |
| config { | |
| pins = "gpio67"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| sde_te1_suspend { | |
| phandle = <0x416>; | |
| mux { | |
| function = "mdp_vsync"; | |
| pins = "gpio67"; | |
| }; | |
| config { | |
| pins = "gpio67"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| sde_te_active { | |
| phandle = <0x413>; | |
| mux { | |
| function = "mdp_vsync"; | |
| pins = "gpio66"; | |
| }; | |
| config { | |
| pins = "gpio66"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_mclk5_suspend { | |
| phandle = <0x474>; | |
| mux { | |
| function = "cam_mclk"; | |
| pins = "gpio99"; | |
| }; | |
| config { | |
| pins = "gpio99"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| cam_sensor_mclk1_active { | |
| phandle = <0x46b>; | |
| mux { | |
| function = "cam_mclk"; | |
| pins = "gpio95"; | |
| }; | |
| config { | |
| pins = "gpio95"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| tert_mi2s_sd0 { | |
| tert_mi2s_sd0_active { | |
| phandle = <0x460>; | |
| mux { | |
| function = "mi2s2_data0"; | |
| pins = "gpio134"; | |
| }; | |
| config { | |
| pins = "gpio134"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| }; | |
| }; | |
| tert_mi2s_sd0_sleep { | |
| phandle = <0x45f>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio134"; | |
| }; | |
| config { | |
| pins = "gpio134"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| mcu_gpio { | |
| phandle = <0x4d8>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio11\0gpio14\0gpio25"; | |
| }; | |
| config { | |
| pins = "gpio11\0gpio14\0gpio25"; | |
| bias-disable; | |
| }; | |
| }; | |
| cnss_pins { | |
| cnss_wlan_en_sleep { | |
| phandle = <0xa6>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio20"; | |
| }; | |
| config { | |
| pins = "gpio20"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| output-low; | |
| }; | |
| }; | |
| cnss_wlan_en_active { | |
| phandle = <0xa5>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio20"; | |
| }; | |
| config { | |
| pins = "gpio20"; | |
| drive-strength = <0x10>; | |
| output-high; | |
| bias-pull-up; | |
| }; | |
| }; | |
| }; | |
| sec_tdm_din { | |
| sec_tdm_din_sleep { | |
| phandle = <0x43b>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio143"; | |
| }; | |
| config { | |
| pins = "gpio143"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| sec_tdm_din_active { | |
| phandle = <0x43c>; | |
| mux { | |
| function = "mi2s1_data0"; | |
| pins = "gpio143"; | |
| }; | |
| config { | |
| pins = "gpio143"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| sec_aux_pcm { | |
| sec_aux_pcm_clk_sleep { | |
| phandle = <0x41f>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio142"; | |
| }; | |
| config { | |
| pins = "gpio142"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| sec_aux_pcm_ws_sleep { | |
| phandle = <0x421>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio145"; | |
| }; | |
| config { | |
| pins = "gpio145"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| sec_aux_pcm_clk_active { | |
| phandle = <0x420>; | |
| mux { | |
| function = "mi2s1_sck"; | |
| pins = "gpio142"; | |
| }; | |
| config { | |
| pins = "gpio142"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| }; | |
| }; | |
| sec_aux_pcm_ws_active { | |
| phandle = <0x422>; | |
| mux { | |
| function = "mi2s1_ws"; | |
| pins = "gpio145"; | |
| }; | |
| config { | |
| pins = "gpio145"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| pri_aux_pcm_din { | |
| pri_aux_pcm_din_active { | |
| phandle = <0x41c>; | |
| mux { | |
| function = "mi2s0_data0"; | |
| pins = "gpio139"; | |
| }; | |
| config { | |
| pins = "gpio139"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| }; | |
| }; | |
| pri_aux_pcm_din_sleep { | |
| phandle = <0x41b>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio139"; | |
| }; | |
| config { | |
| pins = "gpio139"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| pogo_gpio { | |
| phandle = <0x4d7>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio24\0gpio129"; | |
| }; | |
| config { | |
| pins = "gpio24\0gpio129"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| sdc2_clk_ds_200MHz { | |
| phandle = <0x3ff>; | |
| config { | |
| pins = "sdc2_clk"; | |
| drive-strength = <0x10>; | |
| bias-disable; | |
| }; | |
| }; | |
| pri_mi2s_ws { | |
| pri_mi2s_ws_sleep { | |
| phandle = <0x44b>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio141"; | |
| }; | |
| config { | |
| pins = "gpio141"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| pri_mi2s_ws_active { | |
| phandle = <0x44c>; | |
| mux { | |
| function = "mi2s0_ws"; | |
| pins = "gpio141"; | |
| }; | |
| config { | |
| pins = "gpio141"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_mclk2_active { | |
| phandle = <0x46d>; | |
| mux { | |
| function = "cam_mclk"; | |
| pins = "gpio96"; | |
| }; | |
| config { | |
| pins = "gpio96"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| cam_sensor_active_etleft { | |
| phandle = <0x497>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio93"; | |
| }; | |
| config { | |
| pins = "gpio93"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| cam_sensor_suspend_4 { | |
| phandle = <0x480>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio130"; | |
| }; | |
| config { | |
| pins = "gpio130"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| output-low; | |
| }; | |
| }; | |
| qupv3_se18_i2c_pins { | |
| phandle = <0x4ce>; | |
| qupv3_se18_i2c_sleep { | |
| phandle = <0x2cf>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio56\0gpio57"; | |
| }; | |
| config { | |
| pins = "gpio56\0gpio57"; | |
| drive-strength = <0x02>; | |
| bias-no-pull; | |
| }; | |
| }; | |
| qupv3_se18_i2c_active { | |
| phandle = <0x2ce>; | |
| mux { | |
| function = "qup18"; | |
| pins = "gpio56\0gpio57"; | |
| }; | |
| config { | |
| pins = "gpio56\0gpio57"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| qupv3_se13_spi_pins { | |
| phandle = <0x4c9>; | |
| qupv3_se13_spi_active { | |
| phandle = <0x2ba>; | |
| mux { | |
| function = "qup13"; | |
| pins = "gpio36\0gpio37\0gpio38\0gpio39"; | |
| }; | |
| config { | |
| pins = "gpio36\0gpio37\0gpio38\0gpio39"; | |
| drive-strength = <0x06>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se13_spi_sleep { | |
| phandle = <0x2bb>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio36\0gpio37\0gpio38\0gpio39"; | |
| }; | |
| config { | |
| pins = "gpio36\0gpio37\0gpio38\0gpio39"; | |
| drive-strength = <0x06>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| qupv3_se9_i2c_pins { | |
| phandle = <0x4be>; | |
| qupv3_se9_i2c_active { | |
| phandle = <0x2a7>; | |
| mux { | |
| function = "qup9"; | |
| pins = "gpio125\0gpio126"; | |
| }; | |
| config { | |
| pins = "gpio125\0gpio126"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se9_i2c_sleep { | |
| phandle = <0x2a8>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio125\0gpio126"; | |
| }; | |
| config { | |
| pins = "gpio125\0gpio126"; | |
| drive-strength = <0x02>; | |
| bias-no-pull; | |
| }; | |
| }; | |
| }; | |
| qupv3_se4_spi_pins { | |
| phandle = <0x4b9>; | |
| qupv3_se4_spi_active { | |
| phandle = <0x299>; | |
| mux { | |
| function = "qup4"; | |
| pins = "gpio8\0gpio9\0gpio10"; | |
| }; | |
| config { | |
| pins = "gpio8\0gpio9\0gpio10"; | |
| drive-strength = <0x06>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se4_spi_sleep { | |
| phandle = <0x29a>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio8\0gpio9\0gpio10"; | |
| }; | |
| config { | |
| pins = "gpio8\0gpio9\0gpio10"; | |
| drive-strength = <0x06>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| sec_mi2s_sck { | |
| sec_mi2s_sck_sleep { | |
| phandle = <0x453>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio142"; | |
| }; | |
| config { | |
| pins = "gpio142"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| sec_mi2s_sck_active { | |
| phandle = <0x454>; | |
| mux { | |
| function = "mi2s1_sck"; | |
| pins = "gpio142"; | |
| }; | |
| config { | |
| pins = "gpio142"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| tsif0_sync_active { | |
| phandle = <0xb1>; | |
| tsif1_sync { | |
| function = "tsif0_sync"; | |
| pins = "gpio72"; | |
| drive_strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| pmx_ts_active { | |
| ts_active { | |
| phandle = <0x3f5>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio38\0gpio39"; | |
| }; | |
| config { | |
| pins = "gpio38\0gpio39"; | |
| drive-strength = <0x08>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_suspend_etleft { | |
| phandle = <0x498>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio93"; | |
| }; | |
| config { | |
| pins = "gpio93"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| output-low; | |
| }; | |
| }; | |
| cam_sensor_mclk3_active { | |
| phandle = <0x46f>; | |
| mux { | |
| function = "cam_mclk"; | |
| pins = "gpio97"; | |
| }; | |
| config { | |
| pins = "gpio97"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se0_i2c_pins { | |
| phandle = <0x4a6>; | |
| qupv3_se0_i2c_sleep { | |
| phandle = <0x282>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio28\0gpio29"; | |
| }; | |
| config { | |
| pins = "gpio28\0gpio29"; | |
| drive-strength = <0x02>; | |
| bias-no-pull; | |
| }; | |
| }; | |
| qupv3_se0_i2c_active { | |
| phandle = <0x281>; | |
| mux { | |
| function = "qup0"; | |
| pins = "gpio28\0gpio29"; | |
| }; | |
| config { | |
| pins = "gpio28\0gpio29"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_rgb_vio_suspend { | |
| phandle = <0x494>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio116"; | |
| }; | |
| config { | |
| pins = "gpio116"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| sde_dp_usbplug_cc_suspend { | |
| phandle = <0x40d>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio65"; | |
| }; | |
| config { | |
| pins = "gpio65"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| sec_mi2s_ws { | |
| sec_mi2s_ws_active { | |
| phandle = <0x456>; | |
| mux { | |
| function = "mi2s1_ws"; | |
| pins = "gpio145"; | |
| }; | |
| config { | |
| pins = "gpio145"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| }; | |
| }; | |
| sec_mi2s_ws_sleep { | |
| phandle = <0x455>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio145"; | |
| }; | |
| config { | |
| pins = "gpio145"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| pri_mi2s_sck { | |
| pri_mi2s_sck_sleep { | |
| phandle = <0x449>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio138"; | |
| }; | |
| config { | |
| pins = "gpio138"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| pri_mi2s_sck_active { | |
| phandle = <0x44a>; | |
| mux { | |
| function = "mi2s0_sck"; | |
| pins = "gpio138"; | |
| }; | |
| config { | |
| pins = "gpio138"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_mclk4_active { | |
| phandle = <0x471>; | |
| mux { | |
| function = "cam_mclk"; | |
| pins = "gpio98"; | |
| }; | |
| config { | |
| pins = "gpio98"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| cam_sensor_6dof_vana_active { | |
| phandle = <0x487>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio84"; | |
| }; | |
| config { | |
| pins = "gpio84"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se18_spi_pins { | |
| phandle = <0x4d4>; | |
| qupv3_se18_spi_active { | |
| phandle = <0x2da>; | |
| mux { | |
| function = "qup18"; | |
| pins = "gpio56\0gpio57\0gpio58\0gpio59"; | |
| }; | |
| config { | |
| pins = "gpio56\0gpio57\0gpio58\0gpio59"; | |
| drive-strength = <0x06>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se18_spi_sleep { | |
| phandle = <0x2db>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio56\0gpio57\0gpio58\0gpio59"; | |
| }; | |
| config { | |
| pins = "gpio56\0gpio57\0gpio58\0gpio59"; | |
| drive-strength = <0x06>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| qupv3_se9_spi_pins { | |
| phandle = <0x4c5>; | |
| qupv3_se9_spi_active { | |
| phandle = <0x2b2>; | |
| mux { | |
| function = "qup9"; | |
| pins = "gpio125\0gpio126\0gpio127\0gpio128"; | |
| }; | |
| config { | |
| pins = "gpio125\0gpio126\0gpio127\0gpio128"; | |
| drive-strength = <0x06>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se9_spi_sleep { | |
| phandle = <0x2b3>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio125\0gpio126\0gpio127\0gpio128"; | |
| }; | |
| config { | |
| pins = "gpio125\0gpio126\0gpio127\0gpio128"; | |
| drive-strength = <0x06>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_mclk0_suspend { | |
| phandle = <0x46a>; | |
| mux { | |
| function = "cam_mclk"; | |
| pins = "gpio94"; | |
| }; | |
| config { | |
| pins = "gpio94"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| ufs_dev_reset_deassert { | |
| phandle = <0x79>; | |
| config { | |
| pins = "ufs_reset"; | |
| drive-strength = <0x08>; | |
| output-high; | |
| bias-pull-down; | |
| }; | |
| }; | |
| sec_mi2s_sd0 { | |
| sec_mi2s_sd0_sleep { | |
| phandle = <0x457>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio143"; | |
| }; | |
| config { | |
| pins = "gpio143"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| sec_mi2s_sd0_active { | |
| phandle = <0x458>; | |
| mux { | |
| function = "mi2s1_data0"; | |
| pins = "gpio143"; | |
| }; | |
| config { | |
| pins = "gpio143"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| sec_tdm { | |
| sec_tdm_sck_active { | |
| phandle = <0x438>; | |
| mux { | |
| function = "mi2s1_sck"; | |
| pins = "gpio142"; | |
| }; | |
| config { | |
| pins = "gpio142"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| }; | |
| }; | |
| sec_tdm_sck_sleep { | |
| phandle = <0x437>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio142"; | |
| }; | |
| config { | |
| pins = "gpio142"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| sec_tdm_ws_active { | |
| phandle = <0x43a>; | |
| mux { | |
| function = "mi2s1_ws"; | |
| pins = "gpio145"; | |
| }; | |
| config { | |
| pins = "gpio145"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| }; | |
| }; | |
| sec_tdm_ws_sleep { | |
| phandle = <0x439>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio145"; | |
| }; | |
| config { | |
| pins = "gpio145"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| sdc2_data_ds_50MHz { | |
| phandle = <0x409>; | |
| config { | |
| pins = "sdc2_data"; | |
| drive-strength = <0x10>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| trigout_a { | |
| phandle = <0x233>; | |
| mux { | |
| function = "qdss_cti"; | |
| pins = "gpio2"; | |
| }; | |
| config { | |
| pins = "gpio2"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| cam_sensor_active_rst2 { | |
| phandle = <0x47b>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio78"; | |
| }; | |
| config { | |
| pins = "gpio78"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| cam_sensor_active_rgbleft { | |
| phandle = <0x4a1>; | |
| mux { | |
| }; | |
| config { | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| sec_aux_pcm_dout { | |
| sec_aux_pcm_dout_active { | |
| phandle = <0x426>; | |
| mux { | |
| function = "mi2s1_data1"; | |
| pins = "gpio144"; | |
| }; | |
| config { | |
| pins = "gpio144"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| }; | |
| }; | |
| sec_aux_pcm_dout_sleep { | |
| phandle = <0x425>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio144"; | |
| }; | |
| config { | |
| pins = "gpio144"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| qupv3_se14_i2c_pins { | |
| phandle = <0x4ca>; | |
| qupv3_se14_i2c_sleep { | |
| phandle = <0x2c4>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio40\0gpio41"; | |
| }; | |
| config { | |
| pins = "gpio40\0gpio41"; | |
| drive-strength = <0x02>; | |
| bias-no-pull; | |
| }; | |
| }; | |
| qupv3_se14_i2c_active { | |
| phandle = <0x2c3>; | |
| mux { | |
| function = "qup14"; | |
| pins = "gpio40\0gpio41"; | |
| }; | |
| config { | |
| pins = "gpio40\0gpio41"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| qupv3_se5_i2c_pins { | |
| phandle = <0x4b2>; | |
| qupv3_se5_i2c_sleep { | |
| phandle = <0x28c>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio12\0gpio13"; | |
| }; | |
| config { | |
| pins = "gpio12\0gpio13"; | |
| drive-strength = <0x02>; | |
| bias-no-pull; | |
| }; | |
| }; | |
| qupv3_se5_i2c_active { | |
| phandle = <0x28b>; | |
| mux { | |
| function = "qup5"; | |
| pins = "gpio12\0gpio13"; | |
| }; | |
| config { | |
| pins = "gpio12\0gpio13"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| qupv3_se0_spi_pins { | |
| phandle = <0x4b5>; | |
| qupv3_se0_spi_sleep { | |
| phandle = <0x292>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio28\0gpio29\0gpio30\0gpio31"; | |
| }; | |
| config { | |
| pins = "gpio28\0gpio29\0gpio30\0gpio31"; | |
| drive-strength = <0x06>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se0_spi_active { | |
| phandle = <0x291>; | |
| mux { | |
| function = "qup0"; | |
| pins = "gpio28\0gpio29\0gpio30\0gpio31"; | |
| }; | |
| config { | |
| pins = "gpio28\0gpio29\0gpio30\0gpio31"; | |
| drive-strength = <0x06>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| sdc2_clk_ds_100MHz { | |
| phandle = <0x3fe>; | |
| config { | |
| pins = "sdc2_clk"; | |
| drive-strength = <0x10>; | |
| bias-disable; | |
| }; | |
| }; | |
| cam_sensor_mclk5_active { | |
| phandle = <0x473>; | |
| mux { | |
| function = "cam_mclk"; | |
| pins = "gpio99"; | |
| }; | |
| config { | |
| pins = "gpio99"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| cam_sensor_suspend_6dofright { | |
| phandle = <0x49e>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio131"; | |
| }; | |
| config { | |
| pins = "gpio131"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| output-low; | |
| }; | |
| }; | |
| pmx_sde { | |
| phandle = <0x40e>; | |
| sde_dsi_suspend { | |
| phandle = <0x410>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio75\0gpio60"; | |
| }; | |
| config { | |
| pins = "gpio75\0gpio60"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| sde_dsi1_active { | |
| phandle = <0x411>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio128"; | |
| }; | |
| config { | |
| pins = "gpio128"; | |
| drive-strength = <0x08>; | |
| bias-disable = <0x00>; | |
| }; | |
| }; | |
| sde_dsi1_suspend { | |
| phandle = <0x412>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio128"; | |
| }; | |
| config { | |
| pins = "gpio128"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| sde_dsi_active { | |
| phandle = <0x40f>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio75\0gpio60"; | |
| }; | |
| config { | |
| pins = "gpio75\0gpio60"; | |
| drive-strength = <0x08>; | |
| bias-disable = <0x00>; | |
| }; | |
| }; | |
| }; | |
| lt9611_pins { | |
| phandle = <0x4a8>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio2\0gpio1"; | |
| }; | |
| config { | |
| pins = "gpio2\0gpio1"; | |
| drive-strength = <0x08>; | |
| bias-disable = <0x00>; | |
| }; | |
| }; | |
| spkr_2_sd_n { | |
| spkr_2_sd_n_active { | |
| phandle = <0x466>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio127"; | |
| }; | |
| config { | |
| pins = "gpio127"; | |
| drive-strength = <0x10>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| spkr_2_sd_n_sleep { | |
| phandle = <0x465>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio127"; | |
| }; | |
| config { | |
| pins = "gpio127"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| pri_mi2s_sd0 { | |
| pri_mi2s_sd0_active { | |
| phandle = <0x44e>; | |
| mux { | |
| function = "mi2s0_data0"; | |
| pins = "gpio139"; | |
| }; | |
| config { | |
| pins = "gpio139"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| pri_mi2s_sd0_sleep { | |
| phandle = <0x44d>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio139"; | |
| }; | |
| config { | |
| pins = "gpio139"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| tert_aux_pcm_dout { | |
| tert_aux_pcm_dout_sleep { | |
| phandle = <0x42d>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio137"; | |
| }; | |
| config { | |
| pins = "gpio137"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| tert_aux_pcm_dout_active { | |
| phandle = <0x42e>; | |
| mux { | |
| function = "mi2s2_data1"; | |
| pins = "gpio137"; | |
| }; | |
| config { | |
| pins = "gpio137"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| wcd938x_reset_active { | |
| phandle = <0x467>; | |
| mux { | |
| function = "func2"; | |
| pins = "gpio32"; | |
| }; | |
| config { | |
| pins = "gpio32"; | |
| drive-strength = <0x10>; | |
| output-high; | |
| }; | |
| }; | |
| cam_sensor_mclk6_active { | |
| phandle = <0x475>; | |
| mux { | |
| function = "cam_mclk"; | |
| pins = "gpio100"; | |
| }; | |
| config { | |
| pins = "gpio100"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| mdm2ap { | |
| mdm2ap_active { | |
| phandle = <0x63>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio1\0gpio3"; | |
| }; | |
| config { | |
| pins = "gpio1\0gpio3"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| }; | |
| }; | |
| mdm2ap_sleep { | |
| phandle = <0x65>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio1\0gpio3"; | |
| }; | |
| config { | |
| pins = "gpio1\0gpio3"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| pcie1 { | |
| pcie1_clkreq_default { | |
| phandle = <0x16f>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio83"; | |
| }; | |
| config { | |
| pins = "gpio83"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| pcie1_wake_default { | |
| phandle = <0x171>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio84"; | |
| }; | |
| config { | |
| pins = "gpio84"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| pcie1_perst_default { | |
| phandle = <0x170>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio82"; | |
| }; | |
| config { | |
| pins = "gpio82"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_active_rear { | |
| phandle = <0x477>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio93"; | |
| }; | |
| config { | |
| pins = "gpio93"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| cam_sensor_active_etright { | |
| phandle = <0x499>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio92"; | |
| }; | |
| config { | |
| pins = "gpio92"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se19_i2c_pins { | |
| phandle = <0x4cf>; | |
| qupv3_se19_i2c_sleep { | |
| phandle = <0x2d1>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio0\0gpio1"; | |
| }; | |
| config { | |
| pins = "gpio0\0gpio1"; | |
| drive-strength = <0x02>; | |
| bias-no-pull; | |
| }; | |
| }; | |
| qupv3_se19_i2c_active { | |
| phandle = <0x2d0>; | |
| mux { | |
| function = "qup19"; | |
| pins = "gpio0\0gpio1"; | |
| }; | |
| config { | |
| pins = "gpio0\0gpio1"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| qupv3_se14_spi_pins { | |
| phandle = <0x4d0>; | |
| qupv3_se14_spi_sleep { | |
| phandle = <0x2d3>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio40\0gpio41\0gpio42\0gpio43"; | |
| }; | |
| config { | |
| pins = "gpio40\0gpio41\0gpio42\0gpio43"; | |
| drive-strength = <0x06>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se14_spi_active { | |
| phandle = <0x2d2>; | |
| mux { | |
| function = "qup14"; | |
| pins = "gpio40\0gpio41\0gpio42\0gpio43"; | |
| }; | |
| config { | |
| pins = "gpio40\0gpio41\0gpio42\0gpio43"; | |
| drive-strength = <0x06>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| cs35l41_3_irq_default { | |
| phandle = <0x689>; | |
| config { | |
| pins = "gpio126"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| cci0_suspend { | |
| phandle = <0x256>; | |
| mux { | |
| function = "cci_i2c"; | |
| pins = "gpio101\0gpio102"; | |
| }; | |
| config { | |
| pins = "gpio101\0gpio102"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| cam_sensor_6dof_vdig_active { | |
| phandle = <0x489>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio82"; | |
| }; | |
| config { | |
| pins = "gpio82"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se5_spi_pins { | |
| phandle = <0x4ba>; | |
| qupv3_se5_spi_sleep { | |
| phandle = <0x29c>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio12\0gpio13\0gpio15"; | |
| }; | |
| config { | |
| pins = "gpio12\013\0gpio15"; | |
| drive-strength = <0x06>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se5_spi_active { | |
| phandle = <0x29b>; | |
| mux { | |
| function = "qup5"; | |
| pins = "gpio12\0gpio13\0gpio15"; | |
| }; | |
| config { | |
| pins = "gpio12\0gpio13\0gpio15"; | |
| drive-strength = <0x06>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_active_6dofleft { | |
| phandle = <0x49b>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio130"; | |
| }; | |
| config { | |
| pins = "gpio130"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| pri_mi2s_mclk { | |
| pri_mi2s_mclk_active { | |
| phandle = <0x448>; | |
| mux { | |
| function = "pri_mi2s"; | |
| pins = "gpio136"; | |
| }; | |
| config { | |
| pins = "gpio136"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| pri_mi2s_mclk_sleep { | |
| phandle = <0x447>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio136"; | |
| }; | |
| config { | |
| pins = "gpio136"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_mclk2_suspend { | |
| phandle = <0x46e>; | |
| mux { | |
| function = "cam_mclk"; | |
| pins = "gpio96"; | |
| }; | |
| config { | |
| pins = "gpio96"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| qupv3_se10_i2c_pins { | |
| phandle = <0x4bf>; | |
| qupv3_se10_i2c_sleep { | |
| phandle = <0x2aa>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio129\0gpio130"; | |
| }; | |
| config { | |
| pins = "gpio129\0gpio130"; | |
| drive-strength = <0x02>; | |
| bias-no-pull; | |
| }; | |
| }; | |
| qupv3_se10_i2c_active { | |
| phandle = <0x2a9>; | |
| mux { | |
| function = "qup10"; | |
| pins = "gpio129\0gpio130"; | |
| }; | |
| config { | |
| pins = "gpio129\0gpio130"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| cs35l41_1_irq_default { | |
| phandle = <0x686>; | |
| config { | |
| pins = "gpio67"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| cci0_active { | |
| phandle = <0x254>; | |
| mux { | |
| function = "cci_i2c"; | |
| pins = "gpio101\0gpio102"; | |
| }; | |
| config { | |
| pins = "gpio101\0gpio102"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| qupv3_se1_i2c_pins { | |
| phandle = <0x4a7>; | |
| qupv3_se1_i2c_active { | |
| phandle = <0x283>; | |
| mux { | |
| function = "qup1"; | |
| pins = "gpio4\0gpio5"; | |
| }; | |
| config { | |
| pins = "gpio4\0gpio5"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se1_i2c_sleep { | |
| phandle = <0x284>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio4\0gpio5"; | |
| }; | |
| config { | |
| pins = "gpio4\0gpio5"; | |
| drive-strength = <0x02>; | |
| bias-no-pull; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_6dof_vio_active { | |
| phandle = <0x48b>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio83"; | |
| }; | |
| config { | |
| pins = "gpio83"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| tert_tdm_dout { | |
| tert_tdm_dout_active { | |
| phandle = <0x446>; | |
| mux { | |
| function = "mi2s2_data1"; | |
| pins = "gpio137"; | |
| }; | |
| config { | |
| pins = "gpio137"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| }; | |
| }; | |
| tert_tdm_dout_sleep { | |
| phandle = <0x445>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio137"; | |
| }; | |
| config { | |
| pins = "gpio137"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| sdc2_clk_ds_400KHz { | |
| phandle = <0x3fc>; | |
| config { | |
| pins = "sdc2_clk"; | |
| drive-strength = <0x10>; | |
| bias-disable; | |
| }; | |
| }; | |
| storage_cd { | |
| phandle = <0x3f9>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio77"; | |
| }; | |
| config { | |
| pins = "gpio77"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| tert_aux_pcm_din { | |
| tert_aux_pcm_din_sleep { | |
| phandle = <0x42b>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio134"; | |
| }; | |
| config { | |
| pins = "gpio134"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| tert_aux_pcm_din_active { | |
| phandle = <0x42c>; | |
| mux { | |
| function = "mi2s2_data0"; | |
| pins = "gpio134"; | |
| }; | |
| config { | |
| pins = "gpio134"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| tert_tdm { | |
| tert_tdm_ws_active { | |
| phandle = <0x442>; | |
| mux { | |
| function = "mi2s2_ws"; | |
| pins = "gpio135"; | |
| }; | |
| config { | |
| pins = "gpio135"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| tert_tdm_clk_active { | |
| phandle = <0x440>; | |
| mux { | |
| function = "mi2s2_sck"; | |
| pins = "gpio133"; | |
| }; | |
| config { | |
| pins = "gpio133"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| tert_tdm_clk_sleep { | |
| phandle = <0x43f>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio133"; | |
| }; | |
| config { | |
| pins = "gpio133"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| tert_tdm_ws_sleep { | |
| phandle = <0x441>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio135"; | |
| }; | |
| config { | |
| pins = "gpio135"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| cci1_active { | |
| phandle = <0x255>; | |
| mux { | |
| function = "cci_i2c"; | |
| pins = "gpio103\0gpio104"; | |
| }; | |
| config { | |
| pins = "gpio103\0gpio104"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| qupv3_se19_spi_pins { | |
| phandle = <0x4d5>; | |
| qupv3_se19_spi_sleep { | |
| phandle = <0x2dd>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio0\0gpio1\0gpio2\0gpio3"; | |
| }; | |
| config { | |
| pins = "gpio0\0gpio1\0gpio2\0gpio3"; | |
| drive-strength = <0x06>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se19_spi_active { | |
| phandle = <0x2dc>; | |
| mux { | |
| function = "qup19"; | |
| pins = "gpio0\0gpio1\0gpio2\0gpio3"; | |
| }; | |
| config { | |
| pins = "gpio0\0gpio1\0gpio2\0gpio3"; | |
| drive-strength = <0x06>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| sdc2_data_off { | |
| phandle = <0x407>; | |
| config { | |
| pins = "sdc2_data"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| qupv3_se0_i3c_pins { | |
| phandle = <0x4a4>; | |
| qupv3_se0_i3c_sleep { | |
| phandle = <0x272>; | |
| mux { | |
| function = "ibi_i3c"; | |
| pins = "gpio28\0gpio29"; | |
| }; | |
| config { | |
| pins = "gpio28\0gpio29"; | |
| drive-strength = <0x10>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| qupv3_se0_i3c_disable { | |
| phandle = <0x273>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio28\0gpio29"; | |
| }; | |
| config { | |
| pins = "gpio28\0gpio29"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| qupv3_se0_i3c_active { | |
| phandle = <0x271>; | |
| mux { | |
| function = "ibi_i3c"; | |
| pins = "gpio28\0gpio29"; | |
| }; | |
| config { | |
| pins = "gpio28\0gpio29"; | |
| drive-strength = <0x10>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_active_5 { | |
| phandle = <0x481>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio131"; | |
| }; | |
| config { | |
| pins = "gpio131"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| spkr_1_sd_n { | |
| spkr_1_sd_n_active { | |
| phandle = <0x464>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio26"; | |
| }; | |
| config { | |
| pins = "gpio26"; | |
| drive-strength = <0x10>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| spkr_1_sd_n_sleep { | |
| phandle = <0x463>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio26"; | |
| }; | |
| config { | |
| pins = "gpio26"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| sde_dp_usbplug_cc_active { | |
| phandle = <0x40c>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio65"; | |
| }; | |
| config { | |
| pins = "gpio65"; | |
| drive-strength = <0x10>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se15_i2c_pins { | |
| phandle = <0x4cb>; | |
| qupv3_se15_i2c_sleep { | |
| phandle = <0x2c6>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio44\0gpio45"; | |
| }; | |
| config { | |
| pins = "gpio44\0gpio45"; | |
| drive-strength = <0x02>; | |
| bias-no-pull; | |
| }; | |
| }; | |
| qupv3_se15_i2c_active { | |
| phandle = <0x2c5>; | |
| mux { | |
| function = "qup15"; | |
| pins = "gpio44\0gpio45"; | |
| }; | |
| config { | |
| pins = "gpio44\0gpio45"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| qupv3_se12_2uart_pins { | |
| phandle = <0x3f2>; | |
| qupv3_se12_2uart_active { | |
| phandle = <0x2a1>; | |
| mux { | |
| function = "qup12"; | |
| pins = "gpio34\0gpio35"; | |
| }; | |
| config { | |
| pins = "gpio34\0gpio35"; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| qupv3_se12_2uart_sleep { | |
| phandle = <0x2a2>; | |
| mux { | |
| pins = "gpio34\0gpio35"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| config { | |
| pins = "gpio34\0gpio35"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| }; | |
| qupv3_se10_spi_pins { | |
| phandle = <0x4c6>; | |
| qupv3_se10_spi_active { | |
| phandle = <0x2b4>; | |
| mux { | |
| function = "qup10"; | |
| pins = "gpio129\0gpio130\0gpio131\0gpio132"; | |
| }; | |
| config { | |
| pins = "gpio129\0gpio130\0gpio131\0gpio132"; | |
| drive-strength = <0x06>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se10_spi_sleep { | |
| phandle = <0x2b5>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio129\0gpio130\0gpio131\0gpio132"; | |
| }; | |
| config { | |
| pins = "gpio129\0gpio130\0gpio131\0gpio132"; | |
| drive-strength = <0x06>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| qupv3_se6_i2c_pins { | |
| phandle = <0x4b3>; | |
| qupv3_se6_i2c_active { | |
| phandle = <0x28d>; | |
| mux { | |
| function = "qup6"; | |
| pins = "gpio16\0gpio17"; | |
| }; | |
| config { | |
| pins = "gpio16\0gpio17"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se6_i2c_sleep { | |
| phandle = <0x28e>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio16\0gpio17"; | |
| }; | |
| config { | |
| pins = "gpio16\0gpio17"; | |
| drive-strength = <0x02>; | |
| bias-no-pull; | |
| }; | |
| }; | |
| }; | |
| usb2_id_det_default { | |
| phandle = <0x4d6>; | |
| config { | |
| function = "gpio"; | |
| pins = "gpio91"; | |
| bias-pull-up; | |
| input-enable; | |
| }; | |
| }; | |
| qupv3_se1_spi_pins { | |
| phandle = <0x4b6>; | |
| qupv3_se1_spi_sleep { | |
| phandle = <0x294>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio4\0gpio5\0gpio6\0gpio7"; | |
| }; | |
| config { | |
| pins = "gpio4\0gpio5\0gpio6\0gpio7"; | |
| drive-strength = <0x06>; | |
| bias-disable; | |
| }; | |
| }; | |
| qupv3_se1_spi_active { | |
| phandle = <0x293>; | |
| mux { | |
| function = "qup1"; | |
| pins = "gpio4\0gpio5\0gpio6\0gpio7"; | |
| }; | |
| config { | |
| pins = "gpio4\0gpio5\0gpio6\0gpio7"; | |
| drive-strength = <0x06>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| cci2_suspend { | |
| phandle = <0x25a>; | |
| mux { | |
| function = "cci_i2c"; | |
| pins = "gpio105\0gpio106"; | |
| }; | |
| config { | |
| pins = "gpio105\0gpio106"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| cam_sensor_6dof_vio_suspend { | |
| phandle = <0x48c>; | |
| mux { | |
| function = "gpio"; | |
| pins = "gpio83"; | |
| }; | |
| config { | |
| pins = "gpio83"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| cci2_active { | |
| phandle = <0x258>; | |
| mux { | |
| function = "cci_i2c"; | |
| pins = "gpio105\0gpio106"; | |
| }; | |
| config { | |
| pins = "gpio105\0gpio106"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| cam_sensor_mclk4_suspend { | |
| phandle = <0x472>; | |
| mux { | |
| function = "cam_mclk"; | |
| pins = "gpio98"; | |
| }; | |
| config { | |
| pins = "gpio98"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| }; | |
| qcom,msm-ext-disp { | |
| compatible = "qcom,msm-ext-disp"; | |
| phandle = <0x642>; | |
| qcom,msm-ext-disp-audio-codec-rx { | |
| compatible = "qcom,msm-ext-disp-audio-codec-rx"; | |
| phandle = <0x667>; | |
| }; | |
| }; | |
| qcom,msm-pcm-low-latency { | |
| qcom,msm-pcm-dsp-id = <0x01>; | |
| qcom,latency-level = "regular"; | |
| compatible = "qcom,msm-pcm-dsp"; | |
| phandle = <0x2e1>; | |
| qcom,msm-pcm-low-latency; | |
| }; | |
| qcom,gdsc@abf0d18 { | |
| clock-names = "ahb_clk"; | |
| qcom,msm-bus,name = "mvs0_gdsc_ahb"; | |
| parent-supply = <0x69>; | |
| qcom,support-hw-trigger; | |
| qcom,retain-regs; | |
| clocks = <0x16 0xcd>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| regulator-name = "mvs0_gdsc"; | |
| vdd_parent-supply = <0x69>; | |
| compatible = "qcom,gdsc"; | |
| reg = <0xabf0d18 0x04>; | |
| phandle = <0x32e>; | |
| qcom,msm-bus,vectors-KBps = <0x01 0x254 0x00 0x00 0x01 0x254 0x00 0x01>; | |
| }; | |
| jtagmm@7140000 { | |
| clock-names = "core_clk"; | |
| reg-names = "etm-base"; | |
| clocks = <0x49 0x00>; | |
| compatible = "qcom,jtagv8-mm"; | |
| qcom,coresight-jtagmm-cpu = <0x0e>; | |
| reg = <0x7140000 0x1000>; | |
| phandle = <0x353>; | |
| }; | |
| wt_boardinfo { | |
| qcom,msm-board-id-2 = <0x66 0x49 0x00>; | |
| qcom,msm-board-id-0 = <0x66 0x45 0x00>; | |
| compatible = "wt:boardinfo"; | |
| qcom,msm-board-id-1 = <0x66 0x47 0x00>; | |
| }; | |
| slim@3ac0000 { | |
| iommus = <0x47 0x1826 0x00 0x47 0x182f 0x00 0x47 0x1830 0x01>; | |
| reg-names = "slimbus_physical\0slimbus_bam_physical"; | |
| cell-index = <0x01>; | |
| interrupts = <0x00 0xa3 0x04 0x00 0xa4 0x04>; | |
| qcom,apps-ch-pipes = <0x700000>; | |
| compatible = "qcom,slim-ngd"; | |
| status = "ok"; | |
| interrupt-names = "slimbus_irq\0slimbus_bam_irq"; | |
| qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>; | |
| reg = <0x3ac0000 0x2c000 0x3a84000 0x2c000>; | |
| phandle = <0x34b>; | |
| qcom,ea-pc = <0x2d0>; | |
| qcom,iommu-dma = "atomic"; | |
| qca6390 { | |
| qcom,btfm-slim-ifd = "btfmslim_slave_ifd"; | |
| elemental-addr = [00 01 20 02 17 02]; | |
| qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02]; | |
| compatible = "qcom,btfmslim_slave"; | |
| phandle = <0x34c>; | |
| }; | |
| }; | |
| goodix_fp { | |
| fp-gpio-irq = <0x66 0x17 0x00>; | |
| fp-gpio-reset = <0x66 0x16 0x00>; | |
| fp-gpio-envdd = <0x66 0x64 0x00>; | |
| interrupt-parent = <0x66>; | |
| vdd-supply = <0x337>; | |
| compatible = "goodix,fingerprint"; | |
| status = "okay"; | |
| }; | |
| qcom,msm-pri-auxpcm { | |
| qcom,msm-cpudai-auxpcm-quant = <0x02 0x02>; | |
| qcom,msm-cpudai-auxpcm-frame = <0x05 0x04>; | |
| qcom,msm-cpudai-auxpcm-sync = <0x01 0x01>; | |
| qcom,msm-auxpcm-interface = "primary"; | |
| qcom,msm-cpudai-auxpcm-slot-mapping = <0x01 0x01>; | |
| qcom,msm-cpudai-auxpcm-data = <0x00 0x00>; | |
| qcom,msm-cpudai-afe-clk-ver = <0x02>; | |
| qcom,msm-cpudai-auxpcm-num-slots = <0x01 0x01>; | |
| compatible = "qcom,msm-auxpcm-dev"; | |
| qcom,msm-cpudai-auxpcm-mode = <0x00 0x00>; | |
| phandle = <0x2f5>; | |
| qcom,msm-cpudai-auxpcm-pcm-clk-rate = <0x1f4000 0x1f4000>; | |
| }; | |
| qcom,msm-ssc-sensors { | |
| compatible = "qcom,msm-ssc-sensors"; | |
| status = "ok"; | |
| phandle = <0x3a4>; | |
| qcom,firmware-name = "slpi"; | |
| }; | |
| qcom,cpucc { | |
| clock-output-names = "cpucc_clocks"; | |
| #clock-cells = <0x01>; | |
| compatible = "qcom,dummycc"; | |
| phandle = <0x1ae>; | |
| }; | |
| cti@6e0e000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti-ddr_dl_1_cti_2"; | |
| compatible = "arm,primecell"; | |
| reg = <0x6e0e000 0x1000>; | |
| phandle = <0x511>; | |
| }; | |
| funnel@69c2000 { | |
| arm,primecell-periphid = <0xbb908>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "funnel-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-funnel-dl-south"; | |
| compatible = "arm,primecell"; | |
| reg = <0x69c2000 0x1000>; | |
| phandle = <0x4f5>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x1d3>; | |
| phandle = <0x1dd>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x00>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x1d4>; | |
| phandle = <0x1d5>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| tpdm@7860000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "tpdm-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-tpdm-actpm"; | |
| compatible = "arm,primecell"; | |
| reg = <0x7860000 0x1000>; | |
| phandle = <0x4ff>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x20f>; | |
| phandle = <0x20b>; | |
| }; | |
| }; | |
| }; | |
| cti@6b41000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti-ssc_cti1"; | |
| compatible = "arm,primecell"; | |
| status = "disabled"; | |
| reg = <0x6b41000 0x1000>; | |
| phandle = <0x53d>; | |
| }; | |
| tpdm@6c40000 { | |
| arm,primecell-periphid = <0xbb968>; | |
| qcom,proxy-regs = "vdd\0vdd_cx"; | |
| clock-names = "apb_pclk\0gcc_npu_axi_clk\0gcc_npu_cfg_ahb_clk\0npu_cc_xo_clk\0npu_core_clk\0npu_core_clk_src\0npu_cc_atb_clk\0npu_cc_llm_clk\0npu_cc_llm_xo_clk\0npu_cc_llm_temp_clk\0npu_cc_llm_curr_clk\0npu_cc_dl_llm_clk"; | |
| reg-names = "tpdm-base"; | |
| qcom,proxy-clks = "gcc_npu_axi_clk\0gcc_npu_cfg_ahb_clk\0npu_cc_xo_clk\0npu_core_clk\0npu_core_clk_src\0npu_cc_atb_clk\0npu_cc_llm_clk\0npu_cc_llm_xo_clk\0npu_cc_llm_temp_clk\0npu_cc_llm_curr_clk\0npu_cc_dl_llm_clk"; | |
| clocks = <0x49 0x00 0x16 0x28 0x16 0x2b 0x55 0x28 0x55 0x0d 0x55 0x0e 0x55 0x00 0x55 0x1a 0x55 0x1d 0x55 0x1c 0x55 0x1b 0x55 0x10>; | |
| coresight-name = "coresight-tpdm-npu-llm"; | |
| vdd-supply = <0x1de>; | |
| compatible = "arm,primecell"; | |
| reg = <0x6c40000 0x1000>; | |
| phandle = <0x1f7>; | |
| vdd_cx-supply = <0x67>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x1e0>; | |
| phandle = <0x21c>; | |
| }; | |
| }; | |
| }; | |
| cti@6b2b000 { | |
| arm,primecell-periphid = <0xbb966>; | |
| clock-names = "apb_pclk"; | |
| reg-names = "cti-base"; | |
| clocks = <0x49 0x00>; | |
| coresight-name = "coresight-cti-lpass_q6_cti"; | |
| compatible = "arm,primecell"; | |
| status = "disabled"; | |
| reg = <0x6b2b000 0x1000>; | |
| phandle = <0x535>; | |
| }; | |
| qcom,spcom { | |
| qcom,spcom-sp2soc-rmb-reg-addr = <0x1881020>; | |
| qcom,spcom-sp2soc-rmb-pbldone-bit = <0x19>; | |
| qcom,spcom-soc2sp-rmb-reg-addr = <0x1881030>; | |
| qcom,spcom-rmb-err-reg-addr = <0x188103c>; | |
| qcom,spcom-sp2soc-rmb-initdone-bit = <0x18>; | |
| compatible = "qcom,spcom"; | |
| qcom,spcom-soc2sp-rmb-sp-ssr-bit = <0x00>; | |
| status = "ok"; | |
| qcom,spcom-ch-names = "sp_kernel\0sp_ssr"; | |
| }; | |
| }; | |
| psci { | |
| method = "smc"; | |
| compatible = "arm,psci-1.0"; | |
| }; | |
| aliases { | |
| sdhc2 = "/soc/sdhci@8804000"; | |
| swr2 = "/soc/qcom,msm-audio-apr/qcom,q6core-audio/bolero-cdc/tx-macro@3220000/tx_swr_master"; | |
| pci-domain2 = "/soc/qcom,pcie@1c10000"; | |
| swr0 = "/soc/qcom,msm-audio-apr/qcom,q6core-audio/bolero-cdc/wsa-macro@3240000/wsa_swr_master"; | |
| pci-domain0 = "/soc/qcom,pcie@1c00000"; | |
| i2c4 = "/soc/i2c@884000"; | |
| i2c2 = "/soc/i2c@990000"; | |
| swr1 = "/soc/qcom,msm-audio-apr/qcom,q6core-audio/bolero-cdc/rx-macro@3200000/rx_swr_master"; | |
| pci-domain1 = "/soc/qcom,pcie@1c08000"; | |
| ufshc1 = "/soc/ufshc@1d84000"; | |
| serial0 = "/soc/qcom,qup_uart@988000"; | |
| mhi-netdev0 = "/soc/qcom,pcie@1c10000/pcie2_rp/qcom,mhi@0/mhi_devices/mhi_rmnet@0"; | |
| }; | |
| firmware { | |
| phandle = <0x613>; | |
| android { | |
| compatible = "android,firmware"; | |
| fstab { | |
| compatible = "android,fstab"; | |
| vendor { | |
| fsmgr_flags = "wait,slotselect,avb"; | |
| mnt_flags = "ro,barrier=1,discard"; | |
| dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor"; | |
| type = "ext4"; | |
| compatible = "android,vendor"; | |
| status = "disabled"; | |
| }; | |
| }; | |
| vbmeta { | |
| parts = "vbmeta,boot,system,vendor,dtbo"; | |
| compatible = "android,vbmeta"; | |
| }; | |
| }; | |
| }; | |
| chosen { | |
| linux,initrd-end = <0x00 0xafffe4cc>; | |
| bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off console=ttyMSM0,115200n8 earlycon=msm_geni_serial,0xa90000 androidboot.hardware=qcom androidboot.console=ttyMSM0 androidboot.memcg=1 lpm_levels.sleep_disabled=1 video=vfb:640x400,bpp=32,memsize=3072000 msm_rtb.filter=0x237 service_locator.enable=1 androidboot.usbcontroller=a600000.dwc3 swiotlb=2048 loop.max_part=7 cgroup.memory=nokmem,nosocket reboot=panic_warm buildvariant=user androidboot.verifiedbootstate=orange androidboot.keymaster=1 androidboot.bootdevice=1d84000.ufshc androidboot.fstab_suffix=default androidboot.boot_devices=soc/1d84000.ufshc androidboot.serialno=12345678 androidboot.bootreason=hard_rst androidboot.secboot=true androidboot.baseband=apq msm_drm.dsi_display0=qcom,mdss_dsi_rm69380_edo_amoled_cmd: androidboot.slot_suffix=_a rootwait ro init=/init androidboot.dtbo_idx=3 androidboot.dtb_idx=0"; | |
| kaslr-seed = <0x00 0x00>; | |
| linux,initrd-start = <0x00 0xafe6a000>; | |
| }; | |
| cpus { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| cpu@300 { | |
| capacity-dmips-mhz = <0x400>; | |
| qcom,freq-domain = <0x04 0x00 0x04>; | |
| device_type = "cpu"; | |
| compatible = "qcom,kryo"; | |
| dynamic-power-coefficient = <0x64>; | |
| next-level-cache = <0x08>; | |
| reg = <0x00 0x300>; | |
| enable-method = "psci"; | |
| phandle = <0x10>; | |
| cpu-release-addr = <0x00 0x90000000>; | |
| l2-cache { | |
| cache-level = <0x02>; | |
| compatible = "arm,arch-cache"; | |
| next-level-cache = <0x05>; | |
| phandle = <0x08>; | |
| }; | |
| l1-dcache { | |
| compatible = "arm,arch-cache"; | |
| phandle = <0x33f>; | |
| }; | |
| l1-icache { | |
| compatible = "arm,arch-cache"; | |
| phandle = <0x33e>; | |
| }; | |
| }; | |
| cpu@600 { | |
| capacity-dmips-mhz = <0x766>; | |
| qcom,freq-domain = <0x04 0x01 0x04>; | |
| device_type = "cpu"; | |
| compatible = "qcom,kryo"; | |
| dynamic-power-coefficient = <0x215>; | |
| next-level-cache = <0x0b>; | |
| reg = <0x00 0x600>; | |
| enable-method = "psci"; | |
| phandle = <0x13>; | |
| cpu-release-addr = <0x00 0x90000000>; | |
| l2-cache { | |
| cache-level = <0x02>; | |
| compatible = "arm,arch-cache"; | |
| next-level-cache = <0x05>; | |
| phandle = <0x0b>; | |
| }; | |
| l1-dcache { | |
| compatible = "arm,arch-cache"; | |
| phandle = <0x345>; | |
| }; | |
| l1-icache { | |
| compatible = "arm,arch-cache"; | |
| phandle = <0x344>; | |
| }; | |
| }; | |
| cpu-map { | |
| cluster2 { | |
| core0 { | |
| cpu = <0x14>; | |
| }; | |
| }; | |
| cluster0 { | |
| core3 { | |
| cpu = <0x10>; | |
| }; | |
| core1 { | |
| cpu = <0x0e>; | |
| }; | |
| core2 { | |
| cpu = <0x0f>; | |
| }; | |
| core0 { | |
| cpu = <0x0d>; | |
| }; | |
| }; | |
| cluster1 { | |
| core1 { | |
| cpu = <0x12>; | |
| }; | |
| core2 { | |
| cpu = <0x13>; | |
| }; | |
| core0 { | |
| cpu = <0x11>; | |
| }; | |
| }; | |
| }; | |
| cpu@200 { | |
| capacity-dmips-mhz = <0x400>; | |
| qcom,freq-domain = <0x04 0x00 0x04>; | |
| device_type = "cpu"; | |
| compatible = "qcom,kryo"; | |
| dynamic-power-coefficient = <0x64>; | |
| next-level-cache = <0x07>; | |
| reg = <0x00 0x200>; | |
| enable-method = "psci"; | |
| phandle = <0x0f>; | |
| cpu-release-addr = <0x00 0x90000000>; | |
| l2-cache { | |
| cache-level = <0x02>; | |
| compatible = "arm,arch-cache"; | |
| next-level-cache = <0x05>; | |
| phandle = <0x07>; | |
| }; | |
| l1-dcache { | |
| compatible = "arm,arch-cache"; | |
| phandle = <0x33d>; | |
| }; | |
| l1-icache { | |
| compatible = "arm,arch-cache"; | |
| phandle = <0x33c>; | |
| }; | |
| }; | |
| cpu@500 { | |
| capacity-dmips-mhz = <0x766>; | |
| qcom,freq-domain = <0x04 0x01 0x04>; | |
| device_type = "cpu"; | |
| compatible = "qcom,kryo"; | |
| dynamic-power-coefficient = <0x215>; | |
| next-level-cache = <0x0a>; | |
| reg = <0x00 0x500>; | |
| enable-method = "psci"; | |
| phandle = <0x12>; | |
| cpu-release-addr = <0x00 0x90000000>; | |
| l2-cache { | |
| cache-level = <0x02>; | |
| compatible = "arm,arch-cache"; | |
| next-level-cache = <0x05>; | |
| phandle = <0x0a>; | |
| }; | |
| l1-dcache { | |
| compatible = "arm,arch-cache"; | |
| phandle = <0x343>; | |
| }; | |
| l1-icache { | |
| compatible = "arm,arch-cache"; | |
| phandle = <0x342>; | |
| }; | |
| }; | |
| cpu@0 { | |
| capacity-dmips-mhz = <0x400>; | |
| qcom,freq-domain = <0x04 0x00 0x04>; | |
| device_type = "cpu"; | |
| compatible = "qcom,kryo"; | |
| dynamic-power-coefficient = <0x64>; | |
| next-level-cache = <0x03>; | |
| reg = <0x00 0x00>; | |
| enable-method = "psci"; | |
| phandle = <0x0d>; | |
| cpu-release-addr = <0x00 0x90000000>; | |
| #cooling-cells = <0x02>; | |
| l2-cache { | |
| cache-level = <0x02>; | |
| compatible = "arm,arch-cache"; | |
| next-level-cache = <0x05>; | |
| phandle = <0x03>; | |
| l3-cache { | |
| cache-level = <0x03>; | |
| compatible = "arm,arch-cache"; | |
| phandle = <0x05>; | |
| }; | |
| }; | |
| l1-dcache { | |
| compatible = "arm,arch-cache"; | |
| phandle = <0x339>; | |
| }; | |
| l1-icache { | |
| compatible = "arm,arch-cache"; | |
| phandle = <0x338>; | |
| }; | |
| }; | |
| cpu@100 { | |
| capacity-dmips-mhz = <0x400>; | |
| qcom,freq-domain = <0x04 0x00 0x04>; | |
| device_type = "cpu"; | |
| compatible = "qcom,kryo"; | |
| dynamic-power-coefficient = <0x64>; | |
| next-level-cache = <0x06>; | |
| reg = <0x00 0x100>; | |
| enable-method = "psci"; | |
| phandle = <0x0e>; | |
| cpu-release-addr = <0x00 0x90000000>; | |
| l2-cache { | |
| cache-level = <0x02>; | |
| compatible = "arm,arch-cache"; | |
| next-level-cache = <0x05>; | |
| phandle = <0x06>; | |
| }; | |
| l1-dcache { | |
| compatible = "arm,arch-cache"; | |
| phandle = <0x33b>; | |
| }; | |
| l1-icache { | |
| compatible = "arm,arch-cache"; | |
| phandle = <0x33a>; | |
| }; | |
| }; | |
| cpu@400 { | |
| capacity-dmips-mhz = <0x766>; | |
| qcom,freq-domain = <0x04 0x01 0x04>; | |
| device_type = "cpu"; | |
| compatible = "qcom,kryo"; | |
| dynamic-power-coefficient = <0x215>; | |
| next-level-cache = <0x09>; | |
| reg = <0x00 0x400>; | |
| enable-method = "psci"; | |
| phandle = <0x11>; | |
| cpu-release-addr = <0x00 0x90000000>; | |
| #cooling-cells = <0x02>; | |
| l2-cache { | |
| cache-level = <0x02>; | |
| compatible = "arm,arch-cache"; | |
| next-level-cache = <0x05>; | |
| phandle = <0x09>; | |
| }; | |
| l1-dcache { | |
| compatible = "arm,arch-cache"; | |
| phandle = <0x341>; | |
| }; | |
| l1-icache { | |
| compatible = "arm,arch-cache"; | |
| phandle = <0x340>; | |
| }; | |
| }; | |
| cpu@700 { | |
| capacity-dmips-mhz = <0x766>; | |
| qcom,freq-domain = <0x04 0x02 0x04>; | |
| device_type = "cpu"; | |
| compatible = "qcom,kryo"; | |
| dynamic-power-coefficient = <0x282>; | |
| next-level-cache = <0x0c>; | |
| reg = <0x00 0x700>; | |
| enable-method = "psci"; | |
| phandle = <0x14>; | |
| cpu-release-addr = <0x00 0x90000000>; | |
| #cooling-cells = <0x02>; | |
| l2-cache { | |
| cache-level = <0x02>; | |
| compatible = "arm,arch-cache"; | |
| next-level-cache = <0x05>; | |
| phandle = <0x0c>; | |
| }; | |
| l1-dcache { | |
| compatible = "arm,arch-cache"; | |
| phandle = <0x347>; | |
| }; | |
| l1-icache { | |
| compatible = "arm,arch-cache"; | |
| phandle = <0x346>; | |
| }; | |
| }; | |
| }; | |
| __symbols__ { | |
| slv_qhs_tlmm1 = "/soc/ad-hoc-bus/slv-qhs-tlmm1"; | |
| eud_in_replicator_swao = "/soc/dummy_sink/port/endpoint"; | |
| pm8150_l4_level = "/soc/rsc@18200000/rpmh-regulator-lmxlvl/regulator-pm8150-l4-level"; | |
| sec_mi2s_mclk_sleep = "/soc/pinctrl@f000000/sec_mi2s_mclk/sec_mi2s_mclk_sleep"; | |
| funnel_turing_in_turing_etm0 = "/soc/funnel@6983000/ports/port@3/endpoint"; | |
| smmu_sde_unsec = "/soc/qcom,mdss_mdp@ae00000/qcom,smmu_sde_unsec_cb"; | |
| mdss_dsi0_pll = "/soc/qcom,mdss_dsi_pll@ae94900"; | |
| smp2p_rdbg5_out = "/soc/qcom,smp2p-cdsp/qcom,smp2p-rdbg5-out"; | |
| qupv3_se11_spi_sleep = "/soc/pinctrl@f000000/qupv3_se11_spi_pins/qupv3_se11_spi_sleep"; | |
| cam_sensor_6dof_vana_suspend = "/soc/pinctrl@f000000/cam_sensor_6dof_vana_suspend"; | |
| cpu4_cpu_llcc_latmon = "/soc/qcom,cpu4-cpugrp/qcom,cpu4-cpu-llcc-latmon"; | |
| tdm_pri_tx = "/soc/qcom,msm-dai-tdm-pri-tx"; | |
| qupv3_se16_spi_sleep = "/soc/pinctrl@f000000/qupv3_se16_spi_pins/qupv3_se16_spi_sleep"; | |
| cpu1_isolate = "/soc/qcom,cpufreq-hw/qcom,cpu-isolation/cpu1-isolate"; | |
| bcm_sn4 = "/soc/ad-hoc-bus/bcm-sn4"; | |
| cdsp_smp2p_in = "/soc/qcom,smp2p-cdsp/slave-kernel"; | |
| cti3 = "/soc/cti@6013000"; | |
| S4C_LEVEL = "/soc/rsc@18200000/rpmh-regulator-mmcxlvl/regulator-pm8150a-s4-level"; | |
| cti_cpu4 = "/soc/cti@7420000"; | |
| tpda_dl_north_in_tpdm_dl_north = "/soc/tpda@6ac1000/ports/port@1/endpoint"; | |
| qupv3_se2_i2c_sleep = "/soc/pinctrl@f000000/qupv3_se2_i2c_pins/qupv3_se2_i2c_sleep"; | |
| wcd938x_reset_sleep = "/soc/pinctrl@f000000/wcd938x_reset_sleep"; | |
| qupv3_se7_i2c_sleep = "/soc/pinctrl@f000000/qupv3_se7_i2c_pins/qupv3_se7_i2c_sleep"; | |
| cpu15_config = "/soc/thermal-zones/cpu-1-5-step/trips/cpu15-config"; | |
| mdss_dp_pll = "/soc/qcom,mdss_dp_pll@c011000"; | |
| va_cdc_dma_0_tx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-va-cdc-dma-0-tx"; | |
| i2c_freq_custom_cci0 = "/soc/qcom,cci@ac4f000/qcom,i2c_custom_mode"; | |
| funnel_npu = "/soc/funnel@6c44000"; | |
| cpufreq_13_config = "/soc/thermal-zones/cpu-1-3-step/trips/cpufreq-13-config"; | |
| icp_iova_mem_map = "/soc/qcom,cam_smmu/msm_cam_smmu_icp/iova-mem-map"; | |
| pri_tdm_clk_active = "/soc/pinctrl@f000000/pri_tdm_clk/pri_tdm_clk_active"; | |
| funnel_dl_north = "/soc/funnel@6ac2000"; | |
| L2A = "/soc/rsc@18200000/rpmh-regulator-ldoa2/regulator-pm8150-l2"; | |
| slv_qhs_cpr_cx = "/soc/ad-hoc-bus/slv-qhs-cpr-cx"; | |
| msm_hvx_rm = "/soc/qcom,glink/cdsp/qcom,msm_cdsprm_rpmsg/qcom,msm_hvx_rm"; | |
| tpda_swao_in_tpdm_swao0 = "/soc/tpda@6b08000/ports/port@1/endpoint"; | |
| jpeg_enc0_all_wr = "/soc/qcom,cam-cpas@ac40000/camera-bus-nodes/level0-nodes/jpeg-enc0-all-wr"; | |
| titan_top_gdsc = "/soc/qcom,gdsc@ad0c144"; | |
| slv_srvc_even_gemnoc = "/soc/ad-hoc-bus/slv-srvc-even-gemnoc"; | |
| fab_ipa_virt = "/soc/ad-hoc-bus/fab-ipa_virt"; | |
| funnel_dl_north_in_tpda_dl_north = "/soc/funnel@6ac2000/ports/port@1/endpoint"; | |
| gpu_opp_table_v2 = "/soc/gpu-opp-table_v2"; | |
| etm7 = "/soc/etm@7740000"; | |
| tpda_apss_in_tpdm_apss = "/soc/tpda@7863000/ports/port@4/endpoint"; | |
| pil_npu_mem = "/reserved-memory/pil_npu_region@86900000"; | |
| cam_sensor_rgb_vdig_suspend = "/soc/pinctrl@f000000/cam_sensor_rgb_vdig_suspend"; | |
| tpda_dl_south = "/soc/tpda@69c1000"; | |
| msm_cdsp_rm = "/soc/qcom,glink/cdsp/qcom,msm_cdsprm_rpmsg/qcom,msm_cdsp_rm"; | |
| clock_dispcc = "/soc/qcom,dispcc@af00000"; | |
| cti1_ddr1 = "/soc/cti@6e0d000"; | |
| thermal_zones = "/soc/thermal-zones"; | |
| qcom_msmhdcp = "/soc/qcom,msm_hdcp"; | |
| gpu_trip0 = "/soc/thermal-zones/gpuss-max-step/trips/gpu-trip0"; | |
| npu_llcc_ddr_bwmon = "/soc/qcom,npu-llcc-ddr-bwmon@0x9093000"; | |
| cci3_active = "/soc/pinctrl@f000000/cci3_active"; | |
| intc = "/soc/interrupt-controller@17a00000"; | |
| sec_mi2s_sd1_active = "/soc/pinctrl@f000000/sec_mi2s_sd1/sec_mi2s_sd1_active"; | |
| sec_boot_fuse = "/soc/secbootfuse@0x7805E8"; | |
| mas_qhm_a2noc_cfg = "/soc/ad-hoc-bus/mas-qhm-a2noc-cfg"; | |
| gpu_gx_gdsc = "/soc/qcom,gdsc@3d9100c"; | |
| mas_qxm_rot_display = "/soc/ad-hoc-bus/mas-qxm-rot_display"; | |
| L1_I_100 = "/cpus/cpu@100/l1-icache"; | |
| adsp_smp2p_in = "/soc/qcom,smp2p-adsp/slave-kernel"; | |
| level1_rt0_wr1 = "/soc/qcom,cam-cpas@ac40000/camera-bus-nodes/level1-nodes/level1-rt0-wr1"; | |
| slv_qns_pcie_mem_noc = "/soc/ad-hoc-bus/slv-qns-pcie-mem-noc"; | |
| jpeg_iova_mem_map = "/soc/qcom,cam_smmu/msm_cam_smmu_jpeg/iova-mem-map"; | |
| sec_tdm_sck_active = "/soc/pinctrl@f000000/sec_tdm/sec_tdm_sck_active"; | |
| cam_sensor_active_3 = "/soc/pinctrl@f000000/cam_sensor_active_3"; | |
| sec_aux_pcm_dout_active = "/soc/pinctrl@f000000/sec_aux_pcm_dout/sec_aux_pcm_dout_active"; | |
| slv_qns_cnoc = "/soc/ad-hoc-bus/slv-qns-cnoc"; | |
| fab_mc_virt_display = "/soc/ad-hoc-bus/fab-mc_virt_display"; | |
| cpu0_cpu_llcc_lat = "/soc/qcom,cpu0-cpu-llcc-lat"; | |
| sdc2_cmd_on = "/soc/pinctrl@f000000/sdc2_cmd_on"; | |
| funnel_ddr_0_in_funnel_ddr_ch02 = "/soc/funnel@6e04000/ports/port@1/endpoint"; | |
| ife0_linear_pdaf_wr = "/soc/qcom,cam-cpas@ac40000/camera-bus-nodes/level0-nodes/ife0-linear-pdaf-wr"; | |
| rx_cdc_dma_6_rx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-rx-cdc-dma-6-rx"; | |
| sec_aux_pcm_din_active = "/soc/pinctrl@f000000/sec_aux_pcm_din/sec_aux_pcm_din_active"; | |
| pm8150a_bob_ao = "/soc/rsc@18200000/rpmh-regulator-bobc1/regulator-pm8150a-bob-ao"; | |
| swao_csr = "/soc/csr@6b0c000"; | |
| adsp_tbu = "/soc/apps-smmu@15000000/adsp_tbu@1519d000"; | |
| funnel_swao_in_audio_etm0 = "/soc/funnel@6b04000/ports/port@2/endpoint"; | |
| level1_rt0_rd0 = "/soc/qcom,cam-cpas@ac40000/camera-bus-nodes/level1-nodes/level1-rt0-rd0"; | |
| tdm_pri_rx = "/soc/qcom,msm-dai-tdm-pri-rx"; | |
| mdss_dsi0 = "/soc/qcom,mdss_dsi_ctrl0@ae94000"; | |
| mas_qnm_snoc = "/soc/ad-hoc-bus/mas-qnm-snoc"; | |
| funnel_dl_mm_out_funnel_dl_center = "/soc/funnel@6c0b000/ports/port@0/endpoint"; | |
| qupv3_se2_spi_sleep = "/soc/pinctrl@f000000/qupv3_se2_spi_pins/qupv3_se2_spi_sleep"; | |
| i2c_freq_100Khz_cci1 = "/soc/qcom,cci@ac50000/qcom,i2c_standard_mode"; | |
| cam_sensor_suspend_6dofleft = "/soc/pinctrl@f000000/cam_sensor_suspend_6dofleft"; | |
| qupv3_se15_spi_pins = "/soc/pinctrl@f000000/qupv3_se15_spi_pins"; | |
| tpdm_swao0_out_tpda_swao = "/soc/tpdm@6b09000/port/endpoint"; | |
| replicator_swao = "/soc/replicator@6b06000"; | |
| cnss_pci = "/soc/qcom,pcie@1c00000/pcie0_rp/cnss_pci"; | |
| funnel_center_in_tpdm_dlct = "/soc/funnel@6c2d000/ports/port@19/endpoint"; | |
| slv_qhs_qup2 = "/soc/ad-hoc-bus/slv-qhs-qup2"; | |
| voice = "/soc/qcom,msm-pcm-voice"; | |
| cpu16_config = "/soc/thermal-zones/cpu-1-6-step/trips/cpu16-config"; | |
| qupv3_se7_spi_sleep = "/soc/pinctrl@f000000/qupv3_se7_spi_pins/qupv3_se7_spi_sleep"; | |
| kgsl_msm_iommu = "/soc/qcom,kgsl-iommu@3da0000"; | |
| slv_qns_npu_sys = "/soc/ad-hoc-bus/slv-qns-npu-sys"; | |
| cpufreq_14_config = "/soc/thermal-zones/cpu-1-4-step/trips/cpufreq-14-config"; | |
| pm8150a_bob = "/soc/rsc@18200000/rpmh-regulator-bobc1/regulator-pm8150a-bob"; | |
| qupv3_se6_spi_pins = "/soc/pinctrl@f000000/qupv3_se6_spi_pins"; | |
| tmc_etr_in_replicator0 = "/soc/tmc@6048000/port/endpoint"; | |
| funnel_npu_in_tpdm_npu_llm = "/soc/funnel@6c44000/ports/port@2/endpoint"; | |
| rx_cdc_dma_3_rx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-rx-cdc-dma-3-rx"; | |
| cti10 = "/soc/cti@601a000"; | |
| cpu4_computemon = "/soc/qcom,cpu4-cpugrp/qcom,cpu4-computemon"; | |
| cam_sensor_suspend_5 = "/soc/pinctrl@f000000/cam_sensor_suspend_5"; | |
| slv_ipa_core_slave = "/soc/ad-hoc-bus/slv-ipa-core-slave"; | |
| spkr_2_sd_n_active = "/soc/pinctrl@f000000/spkr_2_sd_n/spkr_2_sd_n_active"; | |
| funnel_in1_in_funnel_dl_north = "/soc/funnel@6042000/ports/port@1/endpoint"; | |
| qupv3_se6_default_tx = "/soc/pinctrl@f000000/qupv3_se6_4uart_pins/qupv3_se6_default_tx"; | |
| mas_qhm_cnoc_dc_noc = "/soc/ad-hoc-bus/mas-qhm-cnoc-dc-noc"; | |
| anoc_2_tbu = "/soc/apps-smmu@15000000/anoc_2_tbu@15189000"; | |
| pm8150a_l11 = "/soc/rsc@18200000/rpmh-regulator-ldoc11/regulator-pm8150a-l11"; | |
| replicator_swao_out_cx_in = "/soc/replicator@6b06000/ports/port@1/endpoint"; | |
| tpdm_mdss = "/soc/tpdm@6c60000"; | |
| tsens0 = "/soc/tsens@c222000"; | |
| ipe_0_gdsc = "/soc/qcom,gdsc@ad08004"; | |
| bcm_mc0_display = "/soc/ad-hoc-bus/bcm-mc0_display"; | |
| L2_3 = "/cpus/cpu@300/l2-cache"; | |
| slv_qhs_npu_cfg = "/soc/ad-hoc-bus/slv-qhs-npu-cfg"; | |
| pil_gpu_mem = "/reserved-memory/pil_gpu_region@8681a000"; | |
| mas_qnm_camnoc_icp = "/soc/ad-hoc-bus/mas-qnm-camnoc-icp"; | |
| ts_int_suspend = "/soc/pinctrl@f000000/pmx_ts_int_suspend/ts_int_suspend"; | |
| pri_aux_pcm_dout_sleep = "/soc/pinctrl@f000000/pri_aux_pcm_dout/pri_aux_pcm_dout_sleep"; | |
| qupv3_se12_spi_active = "/soc/pinctrl@f000000/qupv3_se12_spi_pins/qupv3_se12_spi_active"; | |
| incall_record_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-incall-record-tx"; | |
| mhi_netdev_0_rsc = "/soc/qcom,pcie@1c10000/pcie2_rp/qcom,mhi@0/mhi_devices/mhi_rmnet@1"; | |
| pm8150_l12 = "/soc/rsc@18200000/rpmh-regulator-ldoa12/regulator-pm8150-l12"; | |
| tert_tdm_din_active = "/soc/pinctrl@f000000/tert_tdm_din/tert_tdm_din_active"; | |
| cti_ssc1 = "/soc/cti@6b41000"; | |
| pm8150_l5_ao = "/soc/rsc@18200000/rpmh-regulator-ldoa5/regulator-pm8150-l5-ao"; | |
| tdm_quat_tx = "/soc/qcom,msm-dai-tdm-quat-tx"; | |
| rx_cdc_dma_0_rx = "/soc/qcom,msm-dai-cdc-dma/qcom,msm-dai-rx-cdc-dma-0-rx"; | |
| funnel_dl_compute = "/soc/funnel@6c39000"; | |
| VDD_CX_LEVEL_AO = "/soc/rsc@18200000/rpmh-regulator-cxlvl/regulator-pm8150-s3-level-ao"; | |
| nfc_int_suspend = "/soc/pinctrl@f000000/nfc/nfc_int_suspend"; | |
| gpi_dma2 = "/soc/qcom,gpi-dma@800000"; | |
| qupv3_se11_i2c_pins = "/soc/pinctrl@f000000/qupv3_se11_i2c_pins"; | |
| tpdm_ddr_out_funnel_ddr_0 = "/soc/tpdm@6e00000/port/endpoint"; | |
| dai_quin_auxpcm = "/soc/qcom,msm-quin-auxpcm"; | |
| slim_aud = "/soc/slim@3ac0000"; | |
| cti_gpu_m3 = "/soc/cti@6962000"; | |
| sdc2_cmd_ds_50MHz = "/soc/pinctrl@f000000/sdc2_cmd_ds_50MHz"; | |
| pil_spss_mem = "/reserved-memory/pil_spss_region@8be00000"; | |
| funnel_dl_center_out_qatb3 = "/soc/funnel@6c2d000/ports/port@14/endpoint"; | |
| custom0_all_wr = "/soc/qcom,cam-cpas@ac40000/camera-bus-nodes/level0-nodes/custom0-all-wr"; | |
| slv_qhs_cal_dp1 = "/soc/ad-hoc-bus/slv-qhs-cal-dp1"; | |
| pri_tdm_sync_active = "/soc/pinctrl@f000000/pri_tdm_sync/pri_tdm_sync_active"; | |
| xo_board = "/soc/clocks/xo-board"; | |
| VDD_MX_LEVEL_AO = "/soc/rsc@18200000/rpmh-regulator-mxlvl/regulator-pm8150a-s3-level-ao"; | |
| ipa_smmu_uc = "/soc/qcom,ipa@1e00000/ipa_smmu_uc"; | |
| qupv3_se0_i2c = "/soc/i2c@980000"; | |
| qupv3_se2_i2c_pins = "/soc/pinctrl@f000000/qupv3_se2_i2c_pins"; | |
| glink_cdsp = "/soc/qcom,glink/cdsp"; | |
| dsps_smp2p_out = "/soc/qcom,smp2p-dsps/master-kernel"; | |
| funnel_apss_in_etm6 = "/soc/funnel@7800000/ports/port@7/endpoint"; | |
| bcm_sn2 = "/soc/ad-hoc-bus/bcm-sn2"; | |
| slv_qhs_prng = "/soc/ad-hoc-bus/slv-qhs-prng"; | |
| mas_qnm_gemnoc = "/soc/ad-hoc-bus/mas-qnm-gemnoc"; | |
| cti1 = "/soc/cti@6011000"; | |
| mhi_channels = "/soc/qcom,pcie@1c10000/pcie2_rp/qcom,mhi@0/mhi_channels"; | |
| mas_llcc_mc = "/soc/ad-hoc-bus/mas-llcc-mc"; | |
| cti_cpu2 = "/soc/cti@7220000"; | |
| cti0_swao = "/soc/cti@6b00000"; | |
| sdc2_data_on = "/soc/pinctrl@f000000/sdc2_data_on"; | |
| wil6210_refclk_en_pin = "/soc/pinctrl@f000000/wil6210_refclk_en_pin"; | |
| qupv3_se11_i2c_active = "/soc/pinctrl@f000000/qupv3_se11_i2c_pins/qupv3_se11_i2c_active"; | |
| pri_tdm_dout_active = "/soc/pinctrl@f000000/pri_tdm_dout/pri_tdm_dout_active"; | |
| sde_led_driver_en2_gpio = "/soc/pinctrl@f000000/sde_led_driver_en2_gpio"; | |
| qupv3_se11_spi = "/soc/spi@a8c000"; | |
| S6C_LEVEL = "/soc/rsc@18200000/rpmh-regulator-ebilvl/regulator-pm8150a-s6-level"; | |
| etm2_out_funnel_apss = "/soc/etm@7240000/port/endpoint"; | |
| pm8150_l2 = "/soc/rsc@18200000/rpmh-regulator-ldoa2/regulator-pm8150-l2"; | |
| pri_mi2s_sck_sleep = "/soc/pinctrl@f000000/pri_mi2s_sck/pri_mi2s_sck_sleep"; | |
| cpu4_cpu_ddr_qoslat = "/soc/qcom,cpu4-cpu-ddr-qoslat"; | |
| fab_aggre2_noc = "/soc/ad-hoc-bus/fab-aggre2_noc"; | |
| clock_mccc = "/soc/syscon@90ba000"; | |
| tert_mi2s_ws_sleep = "/soc/pinctrl@f000000/tert_mi2s_ws/tert_mi2s_ws_sleep"; | |
| qupv3_se2_2uart_active = "/soc/pinctrl@f000000/qupv3_se2_2uart_pins/qupv3_se2_2uart_active"; | |
| sb_8_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-8-tx"; | |
| replicator_swao_in_tmc_etf_swao = "/soc/replicator@6b06000/ports/port@2/endpoint"; | |
| cam_sensor_mclk6_suspend = "/soc/pinctrl@f000000/cam_sensor_mclk6_suspend"; | |
| cpu17_config = "/soc/thermal-zones/cpu-1-7-step/trips/cpu17-config"; | |
| smmu_rot_unsec = "/soc/qcom,mdss_rotator@aea8800/qcom,smmu_rot_unsec_cb"; | |
| qupv3_se2_spi = "/soc/spi@988000"; | |
| slv_qhs_dma_bwmon = "/soc/ad-hoc-bus/slv-qhs-dma-bwmon"; | |
| swr2 = "/soc/qcom,msm-audio-apr/qcom,q6core-audio/bolero-cdc/tx-macro@3220000/tx_swr_master"; | |
| cpufreq_15_config = "/soc/thermal-zones/cpu-1-5-step/trips/cpufreq-15-config"; | |
| pcie2_perst_default = "/soc/pinctrl@f000000/pcie2/pcie2_perst_default"; | |
| pcm2 = "/soc/qcom,msm-ultra-low-latency"; | |
| etm5 = "/soc/etm@7540000"; | |
| mas_alc = "/soc/ad-hoc-bus/mas-alc"; | |
| qupv3_se6_default_cts = "/soc/pinctrl@f000000/qupv3_se6_4uart_pins/qupv3_se6_default_cts"; | |
| sde_te_suspend = "/soc/pinctrl@f000000/pmx_sde_te/sde_te_suspend"; | |
| funnel_ddr_ch02 = "/soc/funnel@6e12000"; | |
| tpdm_npu_llm_out_funnel_npu = "/soc/tpdm@6c40000/port/endpoint"; | |
| tsif1_sync_active = "/soc/pinctrl@f000000/tsif1_sync_active"; | |
| qupv3_se17_spi_active = "/soc/pinctrl@f000000/qupv3_se17_spi_pins/qupv3_se17_spi_active"; | |
| slv_qhs_tsif = "/soc/ad-hoc-bus/slv-qhs-tsif"; | |
| sec_tdm_sck_sleep = "/soc/pinctrl@f000000/sec_tdm/sec_tdm_sck_sleep"; | |
| qupv3_se13_i2c = "/soc/i2c@a94000"; | |
| mas_xm_pcie3_0 = "/soc/ad-hoc-bus/mas-xm-pcie3-0"; | |
| sleepstate_smp2p_out = "/soc/qcom,smp2p-dsps/sleepstate-out"; | |
| hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = "/soc/qcom,gdsc@17d058"; | |
| cpu0_l3 = "/soc/qcom,devfreq-l3/qcom,cpu0-cpu-l3-lat"; | |
| cam_sensor_suspend_rgbleft = "/soc/pinctrl@f000000/cam_sensor_suspend_rgbleft"; | |
| mas_qnm_mnoc_hf = "/soc/ad-hoc-bus/mas-qnm-mnoc-hf"; | |
| L1_I_400 = "/cpus/cpu@400/l1-icache"; | |
| tert_tdm_ws_active = "/soc/pinctrl@f000000/tert_tdm/tert_tdm_ws_active"; | |
| qupv3_se4_i2c = "/soc/i2c@990000"; | |
| pm8150a_l9 = "/soc/rsc@18200000/rpmh-regulator-ldoc9/regulator-pm8150a-l9"; | |
| cam_sensor_rgb_vio_active = "/soc/pinctrl@f000000/cam_sensor_rgb_vio_active"; | |
| cpu3_isolate = "/soc/qcom,cpufreq-hw/qcom,cpu-isolation/cpu3-isolate"; | |
| cpu4_cpu_l3_latmon = "/soc/qcom,cpu4-cpugrp/qcom,cpu4-cpu-l3-latmon"; | |
| funnel_apss_out_funnel_apss_merg = "/soc/funnel@7800000/ports/port@0/endpoint"; | |
| slv_qhs_tcm = "/soc/ad-hoc-bus/slv-qhs-tcm"; | |
| L7F = "/soc/rsc@18200000/rpmh-regulator-ldof7/regulator-pm8009-l7"; | |
| bcm_co2 = "/soc/ad-hoc-bus/bcm-co2"; | |
| BOB = "/soc/rsc@18200000/rpmh-regulator-bobc1/regulator-pm8150a-bob"; | |
| funnel_ddr_ch02_out_funnel_ddr_0 = "/soc/funnel@6e12000/ports/port@0/endpoint"; | |
| funnel_gpu = "/soc/funnel@6902000"; | |
| L1_D_300 = "/cpus/cpu@300/l1-dcache"; | |
| incall_record_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-incall-record-rx"; | |
| mnoc_hf_1_tbu = "/soc/apps-smmu@15000000/mnoc_hf_1_tbu@15191000"; | |
| bt_en_sleep = "/soc/pinctrl@f000000/bt_en_sleep"; | |
| jtag_mm6 = "/soc/jtagmm@7640000"; | |
| qupv3_se15_spi = "/soc/spi@884000"; | |
| funnel_apss_merg_out_funnel_in1 = "/soc/funnel@7810000/ports/port@0/endpoint"; | |
| tdm_quat_rx = "/soc/qcom,msm-dai-tdm-quat-rx"; | |
| slv_qns_gemnoc_gc = "/soc/ad-hoc-bus/slv-qns-gemnoc-gc"; | |
| mas_xm_ufs_card = "/soc/ad-hoc-bus/mas-xm-ufs-card"; | |
| level1_nrt0_wr0 = "/soc/qcom,cam-cpas@ac40000/camera-bus-nodes/level1-nodes/level1-nrt0-wr0"; | |
| qupv3_se16_i2c_active = "/soc/pinctrl@f000000/qupv3_se16_i2c_pins/qupv3_se16_i2c_active"; | |
| ufs_phy_gdsc = "/soc/qcom,gdsc@177004"; | |
| funnel_swao_in_ssc_etm0 = "/soc/funnel@6b04000/ports/port@1/endpoint"; | |
| L11A_LEVEL = "/soc/rsc@18200000/rpmh-regulator-lcxlvl/regulator-pm8150-l11-level"; | |
| funnel_merg = "/soc/funnel@6045000"; | |
| ife1_rdi_all_rd = "/soc/qcom,cam-cpas@ac40000/camera-bus-nodes/level0-nodes/ife1-rdi-all-rd"; | |
| nfc_enable_active = "/soc/pinctrl@f000000/nfc/nfc_enable_active"; | |
| mas_xm_gic = "/soc/ad-hoc-bus/mas-xm-gic"; | |
| ufs_dev_reset_assert = "/soc/pinctrl@f000000/ufs_dev_reset_assert"; | |
| ife2_rdi_all_wr = "/soc/qcom,cam-cpas@ac40000/camera-bus-nodes/level0-nodes/ife2-rdi-all-wr"; | |
| qupv3_se6_spi = "/soc/spi@998000"; | |
| qupv3_se14_i2c_sleep = "/soc/pinctrl@f000000/qupv3_se14_i2c_pins/qupv3_se14_i2c_sleep"; | |
| slv_qns_sys_pcie = "/soc/ad-hoc-bus/slv-qns-sys-pcie"; | |
| removed_mem = "/reserved-memory/removed_region@80b00000"; | |
| qupv3_se6_4uart = "/soc/qcom,qup_uart@998000"; | |
| slv_qhs_usb3_0 = "/soc/ad-hoc-bus/slv-qhs-usb3-0"; | |
| modem_mmw2 = "/soc/qmi-tmd-devices/modem/modem_mmw2"; | |
| cpu_cpu_llcc_bwmon = "/soc/qcom,cpu-cpu-llcc-bwmon@90b6400"; | |
| dfps_data_memory = "/reserved-memory/dfps_data_region@9e300000"; | |
| qupv3_se19_i2c_sleep = "/soc/pinctrl@f000000/qupv3_se19_i2c_pins/qupv3_se19_i2c_sleep"; | |
| qupv3_se4_spi_active = "/soc/pinctrl@f000000/qupv3_se4_spi_pins/qupv3_se4_spi_active"; | |
| pm8009_s2 = "/soc/rsc@18200000/rpmh-regulator-smpf2/regulator-pm8009-s2"; | |
| ts_reset_suspend = "/soc/pinctrl@f000000/pmx_ts_reset_suspend/ts_reset_suspend"; | |
| tpdm_ddr_ch02_out_funnel_ddr_ch02 = "/soc/tpdm@6e10000/port/endpoint"; | |
| bcm_mm2 = "/soc/ad-hoc-bus/bcm-mm2"; | |
| funnel_turing_out_funnel_dl_compute = "/soc/funnel@6983000/ports/port@0/endpoint"; | |
| qupv3_se1_i3c_pins = "/soc/pinctrl@f000000/qupv3_se1_i3c_pins"; | |
| adsp_smp2p_out = "/soc/qcom,smp2p-adsp/master-kernel"; | |
| qupv3_se17_i2c = "/soc/i2c@88c000"; | |
| slv_qhs_qup0 = "/soc/ad-hoc-bus/slv-qhs-qup0"; | |
| tpdm_llm_turing = "/soc/tpdm@69810000"; | |
| funnel_swao_in_lpass_lpi = "/soc/funnel@6b04000/ports/port@5/endpoint"; | |
| rot_reg = "/soc/qcom,mdss_rotator@aea8800/qcom,rot-reg-bus"; | |
| usb30_sec_gdsc = "/soc/qcom,gdsc@110004"; | |
| pm8150_s6 = "/soc/rsc@18200000/rpmh-regulator-smpa6/regulator-pm8150-s6"; | |
| slv_xs_pcie_modem = "/soc/ad-hoc-bus/slv-xs-pcie-modem"; | |
| funnel_swao_out_tmc_etf_swao = "/soc/funnel@6b04000/ports/port@0/endpoint"; | |
| afe_loopback_tx = "/soc/qcom,msm-dai-q6-afe-loopback-tx"; | |
| mvs0c_gdsc = "/soc/qcom,gdsc@abf0bf8"; | |
| smem = "/soc/qcom,smem"; | |
| lpass_lpi_out_funnel_swao = "/soc/tpdm@6b26000/port/endpoint"; | |
| L6F = "/soc/rsc@18200000/rpmh-regulator-ldof6/regulator-pm8009-l6"; | |
| tpdm_dlct = "/soc/tpdm@6c28000"; | |
| mas_qxm_ipa = "/soc/ad-hoc-bus/mas-qxm-ipa"; | |
| qupv3_se8_i2c = "/soc/i2c@a80000"; | |
| modem_pa_fr1 = "/soc/qmi-tmd-devices/modem/modem_pa_fr1"; | |
| cam_sensor_suspend_3 = "/soc/pinctrl@f000000/cam_sensor_suspend_3"; | |
| mas_xm_qdss_dap = "/soc/ad-hoc-bus/mas-xm-qdss-dap"; | |
| cpufreq_16_config = "/soc/thermal-zones/cpu-1-6-step/trips/cpufreq-16-config"; | |
| tmc_etr = "/soc/tmc@6048000"; | |
| mhi_netdev_0 = "/soc/qcom,pcie@1c10000/pcie2_rp/qcom,mhi@0/mhi_devices/mhi_rmnet@0"; | |
| slv_qhs_venus_cfg = "/soc/ad-hoc-bus/slv-qhs-venus-cfg"; | |
| bcm_sh4 = "/soc/ad-hoc-bus/bcm-sh4"; | |
| stm = "/soc/stm@6002000"; | |
| funnel_qatb_in_tpda = "/soc/funnel@6005000/ports/port@1/endpoint"; | |
| mas_amm_npu_sys_cdp_w = "/soc/ad-hoc-bus/mas-amm-npu-sys-cdp-w"; | |
| tert_aux_pcm_clk_active = "/soc/pinctrl@f000000/tert_aux_pcm/tert_aux_pcm_clk_active"; | |
| mas_xm_usb3_0 = "/soc/ad-hoc-bus/mas-xm-usb3-0"; | |
| pm8009_l7 = "/soc/rsc@18200000/rpmh-regulator-ldof7/regulator-pm8009-l7"; | |
| pcie1_clkreq_default = "/soc/pinctrl@f000000/pcie1/pcie1_clkreq_default"; | |
| mas_ipa_core_master = "/soc/ad-hoc-bus/mas-ipa-core-master"; | |
| funnel_dl_mm_in_tpdm_mm = "/soc/funnel@6c0b00 |
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