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Ulefone Note 7 device tree source (Downstream Linux 3.18.79)
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| /dts-v1/; | |
| / { | |
| model = "MT6580"; | |
| compatible = "mediatek,MT6580"; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| interrupt-parent = <0x01>; | |
| fp { | |
| interrupts = <0x0a 0x02>; | |
| pinctrl-0 = <0x9a>; | |
| pinctrl-1 = <0x9b>; | |
| pinctrl-2 = <0x9c>; | |
| pinctrl-3 = <0x9d>; | |
| pinctrl-4 = <0x9e>; | |
| pinctrl-5 = <0x9f>; | |
| pinctrl-6 = <0xa0>; | |
| pinctrl-7 = <0xa1>; | |
| pinctrl-8 = <0xa2>; | |
| pinctrl-9 = <0xa3>; | |
| compatible = "mediatek,mt6755-fpc"; | |
| debounce = <0x0a 0x00>; | |
| status = "okay"; | |
| phandle = <0x4a>; | |
| pinctrl-names = "default\0fpc_eint_as_int\0fpc_eint_high\0fpc_eint_low\0fpc_rst_pullhigh\0fpc_rst_pulllow\0fpc_pwr_pullhigh\0fpc_pwr_pulllow\0fpc_spi_mode0\0fpc_spi_mode1"; | |
| linux,phandle = <0x4a>; | |
| interrupt-parent = <0x03>; | |
| }; | |
| bus { | |
| compatible = "simple-bus"; | |
| ranges = <0x00 0x00 0x00 0xffffffff>; | |
| #address-cells = <0x01>; | |
| phandle = <0x27>; | |
| #size-cells = <0x01>; | |
| linux,phandle = <0x27>; | |
| als { | |
| interrupts = <0x06 0x08>; | |
| compatible = "mediatek, als-eint"; | |
| debounce = <0x06 0x3e8>; | |
| status = "okay"; | |
| phandle = <0x47>; | |
| linux,phandle = <0x47>; | |
| interrupt-parent = <0x03>; | |
| }; | |
| gps { | |
| compatible = "mediatek,gps"; | |
| }; | |
| lcm { | |
| compatible = "mediatek,mt6580-lcm"; | |
| phandle = <0x41>; | |
| linux,phandle = <0x41>; | |
| }; | |
| nfc { | |
| compatible = "mediatek,nfc-gpio-v2"; | |
| gpio-eint = <0x0c>; | |
| phandle = <0x42>; | |
| gpio-irq = <0x09>; | |
| gpio-rst = <0x0a>; | |
| gpio-ven = <0x0b>; | |
| linux,phandle = <0x42>; | |
| }; | |
| DISP_COLOR@0x1400C000 { | |
| reg = <0x1400c000 0x1000>; | |
| interrupts = <0x00 0x7c 0x08>; | |
| compatible = "mediatek,DISP_COLOR"; | |
| }; | |
| consys@18070000 { | |
| reg = <0x18070000 0x200 0x10007000 0x100 0x10000000 0x2000 0x10006000 0x1000 0x10005000 0x1000>; | |
| interrupts = <0x00 0x9a 0x08 0x00 0x9c 0x08>; | |
| pinctrl-0 = <0x8e>; | |
| pinctrl-1 = <0x8f>; | |
| pinctrl-2 = <0x90>; | |
| pinctrl-3 = <0x91>; | |
| vcn28-supply = <0x07>; | |
| compatible = "mediatek,mt6580-consys"; | |
| vcn33_wifi-supply = <0x09>; | |
| vcn18-supply = <0x06>; | |
| status = "okay"; | |
| phandle = <0x3c>; | |
| vcn33_bt-supply = <0x08>; | |
| pinctrl-names = "default\0gps_lna_state_init\0gps_lna_state_oh\0gps_lna_state_ol"; | |
| linux,phandle = <0x3c>; | |
| }; | |
| audio@11140000 { | |
| reg = <0x11140000 0x10000>; | |
| interrupts = <0x00 0x50 0x08>; | |
| compatible = "mediatek,audio"; | |
| }; | |
| gpio { | |
| GPIO_SIM1_SIO = <0x17>; | |
| GPIO_SIM2_SIO = <0x18>; | |
| compatible = "mediatek,gpio_usage_mapping"; | |
| GPIO_SIM1_HOT_PLUG = <0x07>; | |
| GPIO_FDD_BAND_SUPPORT_DETECT_1ST_PIN = <0x41>; | |
| GPIO_SIM1_SCLK = <0x16>; | |
| GPIO_SIM2_SCLK = <0x19>; | |
| phandle = <0x2b>; | |
| GPIO_SIM2_HOT_PLUG = <0x08>; | |
| linux,phandle = <0x2b>; | |
| }; | |
| ISP_SYSR@0x15000000 { | |
| compatible = "mediatek,ISP_SYSR"; | |
| }; | |
| SLEEP@0x10006000 { | |
| reg = <0x10006000 0x1000>; | |
| interrupts = <0x00 0x58 0x08 0x00 0x59 0x08 0x00 0x5a 0x08 0x00 0x5b 0x08>; | |
| compatible = "mediatek,SLEEP"; | |
| }; | |
| DBGSYS_CPU@0x10160000 { | |
| reg = <0x10160000 0x20000>; | |
| compatible = "mediatek,DBGSYS_CPU"; | |
| }; | |
| face_down@0 { | |
| compatible = "mediatek,face_down"; | |
| }; | |
| m_pkup_pl@0 { | |
| compatible = "mediatek,m_pkup_pl"; | |
| }; | |
| AHB_MOM@0x11150000 { | |
| reg = <0x11150000 0x10000>; | |
| compatible = "mediatek,AHB_MOM"; | |
| }; | |
| eintc@1000b000 { | |
| reg = <0x1000b000 0x1000>; | |
| interrupts = <0x00 0x5e 0x04>; | |
| mediatek,max_eint_num = <0x1a>; | |
| compatible = "mediatek,mt-eic"; | |
| mediatek,builtin_mapping = <0x00 0x03 0x14 0x01 0x03 0x12 0x07 0x04 0x14 0x08 0x04 0x12 0x09 0x03 0x14 0x0a 0x03 0x12 0x18 0x05 0x14 0x19 0x05 0x12 0x4d 0x02 0x14 0x4e 0x02 0x12 0x0d 0x01 0x11>; | |
| mediatek,mapping_table = <0x00 0x00 0x01 0x01 0x02 0x02 0x03 0x03 0x04 0x04 0x05 0x05 0x06 0x06 0x07 0x07 0x08 0x08 0x09 0x09 0x0a 0x0a 0x0b 0x0b 0x0c 0x0c 0x0d 0x0d 0x0e 0x0e 0x0f 0x0f 0x10 0x00 0x11 0x01 0x12 0x02 0x13 0x03 0x14 0x04 0x15 0x05 0x16 0x06 0x17 0x07 0x18 0x08 0x19 0x09 0x1a 0x0a 0x1b 0x0b 0x1c 0x0c 0x1d 0x0d 0x1e 0x0e 0x1f 0x0f 0x20 0x00 0x21 0x01 0x22 0x02 0x23 0x03 0x24 0x04 0x25 0x05 0x26 0x06 0x27 0x07 0x28 0x08 0x29 0x09 0x2a 0x0a 0x2b 0x0b 0x2c 0x0c 0x2d 0x0d 0x2e 0x0e 0x2f 0x0f 0x30 0x00 0x31 0x01 0x32 0x02 0x33 0x03 0x34 0x03 0x35 0x04 0x36 0x05 0x37 0x06 0x38 0x07 0x39 0x08 0x3a 0x0a 0x3b 0x0b 0x3c 0x0c 0x3d 0x0d 0x3e 0x0e 0x3f 0x0f 0x40 0x00 0x41 0x01 0x42 0x02 0x43 0x03 0x44 0x10 0x45 0x04 0x46 0x05 0x47 0x06 0x48 0x07 0x49 0x08 0x4a 0x09 0x4b 0x0a 0x4c 0x0b 0x4d 0x0c 0x4e 0x0d 0x51 0x00 0x52 0x01 0x53 0x02 0x54 0x03>; | |
| #interrupt-cells = <0x02>; | |
| mediatek,builtin_entry = <0x0b>; | |
| mediatek,mapping_table_entry = <0x53>; | |
| phandle = <0x03>; | |
| interrupt-controller; | |
| linux,phandle = <0x03>; | |
| MD1_SIM1_HOT_PLUG_EINT@1 { | |
| interrupts = <0x01 0x04>; | |
| compatible = "mediatek,MD1_SIM1_HOT_PLUG_EINT-eint"; | |
| dedicated = <0x01 0x01>; | |
| src_pin = <0x01 0x820f078>; | |
| debounce = <0x01 0x186a0>; | |
| sockettype = <0x01 0x00>; | |
| status = "okay"; | |
| }; | |
| pmic@13 { | |
| interrupts = <0x0d 0x04>; | |
| compatible = "mediatek, pmic-eint"; | |
| debounce = <0x0d 0x3e8>; | |
| interrupt-parent = <0x03>; | |
| }; | |
| }; | |
| PWM@0x11008000 { | |
| reg = <0x11008000 0x1000>; | |
| interrupts = <0x00 0x24 0x08>; | |
| compatible = "mediatek,PWM"; | |
| }; | |
| NFIECC@0x11002000 { | |
| reg = <0x11002000 0x1000>; | |
| interrupts = <0x00 0x2e 0x08>; | |
| compatible = "mediatek,NFIECC"; | |
| }; | |
| bat_meter { | |
| compatible = "mediatek,bat_meter"; | |
| phandle = <0x28>; | |
| linux,phandle = <0x28>; | |
| }; | |
| TOPCKGEN@0x10000000 { | |
| reg = <0x10000000 0x1000>; | |
| compatible = "mediatek,TOPCKGEN"; | |
| }; | |
| in_pocket@0 { | |
| compatible = "mediatek,in_pocket"; | |
| }; | |
| DEVAPC@0x10204000 { | |
| reg = <0x10204000 0x1000>; | |
| interrupts = <0x00 0x4a 0x08>; | |
| compatible = "mediatek,DEVAPC"; | |
| }; | |
| mt_soc_mrgrx_pcm { | |
| compatible = "mediatek,mt_soc_pcm_mrgrx"; | |
| }; | |
| m_shk_pl@0 { | |
| compatible = "mediatek,m_shk_pl"; | |
| }; | |
| btif_rx@11000400 { | |
| reg = <0x11000400 0x80>; | |
| interrupts = <0x00 0x37 0x08>; | |
| compatible = "mediatek,btif_rx"; | |
| phandle = <0x3a>; | |
| linux,phandle = <0x3a>; | |
| }; | |
| orientation@0 { | |
| compatible = "mediatek,orientation"; | |
| }; | |
| mdp_tdshp@14006000 { | |
| reg = <0x14006000 0x1000>; | |
| interrupts = <0x00 0x74 0x08>; | |
| compatible = "mediatek,mdp_tdshp"; | |
| }; | |
| gse_1 { | |
| interrupts = <0x0f 0x08>; | |
| compatible = "mediatek, gse_1-eint"; | |
| debounce = <0x0f 0x00>; | |
| status = "okay"; | |
| phandle = <0x38>; | |
| linux,phandle = <0x38>; | |
| interrupt-parent = <0x03>; | |
| }; | |
| AP_DMA_UART0_RX@0x11000500 { | |
| reg = <0x11000500 0x80>; | |
| interrupts = <0x00 0x39 0x08>; | |
| compatible = "mediatek,AP_DMA_UART0_RX"; | |
| }; | |
| EMI@0x10205000 { | |
| reg = <0x10205000 0x1000>; | |
| interrupts = <0x00 0x4c 0x04>; | |
| compatible = "mediatek,EMI"; | |
| }; | |
| chipid@08000000 { | |
| reg = <0x8000000 0x04 0x8000004 0x04 0x8000008 0x04 0x800000c 0x04>; | |
| compatible = "mediatek,chipid"; | |
| }; | |
| shf@0 { | |
| compatible = "mediatek,shf"; | |
| }; | |
| pinctrl@0x10005000 { | |
| reg = <0x10005000 0x1000>; | |
| #gpio-cells = <0x02>; | |
| compatible = "mediatek,mt6580-pinctrl"; | |
| mediatek,pctl-regmap = <0x04>; | |
| phandle = <0x02>; | |
| pins-are-numbered; | |
| gpio-controller; | |
| linux,phandle = <0x02>; | |
| fpceint@0 { | |
| phandle = <0x9b>; | |
| linux,phandle = <0x9b>; | |
| pins_cmd_dat { | |
| pins = <0xa06>; | |
| bias-disable; | |
| slew-rate = <0x00>; | |
| }; | |
| }; | |
| alspspincfg { | |
| phandle = <0x52>; | |
| linux,phandle = <0x52>; | |
| pins_cmd_dat { | |
| pins = <0x606>; | |
| bias-pull-up = <0x00>; | |
| slew-rate = <0x00>; | |
| }; | |
| }; | |
| default { | |
| phandle = <0x8e>; | |
| linux,phandle = <0x8e>; | |
| }; | |
| cam1serial@0 { | |
| phandle = <0x88>; | |
| linux,phandle = <0x88>; | |
| pins_cmd_dat { | |
| pins = <0x2302>; | |
| }; | |
| pins_cmd_dat1 { | |
| pins = <0x2402>; | |
| }; | |
| pins_cmd_dat2 { | |
| pins = <0x2502>; | |
| }; | |
| pins_cmd_dat3 { | |
| pins = <0x2602>; | |
| }; | |
| pins_cmd_dat4 { | |
| pins = <0x2702>; | |
| }; | |
| }; | |
| gyropincfg { | |
| phandle = <0x5d>; | |
| linux,phandle = <0x5d>; | |
| pins_cmd_dat { | |
| pins = <0x600>; | |
| slew-rate = <0x00>; | |
| bias-pull-down = <0x00>; | |
| }; | |
| }; | |
| gpslna@0 { | |
| phandle = <0x8f>; | |
| linux,phandle = <0x8f>; | |
| pins_cmd_dat { | |
| pins = <0x400>; | |
| bias-disable; | |
| output-low; | |
| slew-rate = <0x00>; | |
| }; | |
| }; | |
| gpslna@1 { | |
| phandle = <0x90>; | |
| linux,phandle = <0x90>; | |
| pins_cmd_dat { | |
| pins = <0x400>; | |
| slew-rate = <0x01>; | |
| output-high; | |
| }; | |
| }; | |
| gpslna@2 { | |
| phandle = <0x91>; | |
| linux,phandle = <0x91>; | |
| pins_cmd_dat { | |
| pins = <0x400>; | |
| output-low; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| lcd_inc33_enp0_gpio { | |
| phandle = <0x77>; | |
| linux,phandle = <0x77>; | |
| pins_cmd_dat { | |
| pins = <0x5500>; | |
| output-low; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| lcd_inc33_enp1_gpio { | |
| phandle = <0x78>; | |
| linux,phandle = <0x78>; | |
| pins_cmd_dat { | |
| pins = <0x5500>; | |
| slew-rate = <0x01>; | |
| output-high; | |
| }; | |
| }; | |
| fpceintlow { | |
| phandle = <0x9d>; | |
| linux,phandle = <0x9d>; | |
| pins_cmd_dat { | |
| pins = <0xa00>; | |
| output-low; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| alspsdefaultcfg { | |
| phandle = <0x51>; | |
| linux,phandle = <0x51>; | |
| }; | |
| toucheint@5 { | |
| phandle = <0x61>; | |
| linux,phandle = <0x61>; | |
| pins_cmd_dat { | |
| pins = <0x506>; | |
| bias-disable; | |
| slew-rate = <0x00>; | |
| }; | |
| }; | |
| eintoutput0 { | |
| phandle = <0x62>; | |
| linux,phandle = <0x62>; | |
| pins_cmd_dat { | |
| pins = <0x500>; | |
| output-low; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| eintoutput1 { | |
| phandle = <0x63>; | |
| linux,phandle = <0x63>; | |
| pins_cmd_dat { | |
| pins = <0x500>; | |
| slew-rate = <0x01>; | |
| output-high; | |
| }; | |
| }; | |
| fpcrsthigh { | |
| phandle = <0x9e>; | |
| linux,phandle = <0x9e>; | |
| pins_cmd_dat { | |
| pins = <0xb00>; | |
| slew-rate = <0x01>; | |
| output-high; | |
| }; | |
| }; | |
| mmc1@register_default { | |
| cmd_edge = [01]; | |
| cmdrddly = [00]; | |
| rdata_edge = [01]; | |
| wdata_edge = [01]; | |
| datwrddly = [00]; | |
| dat0rddly = [00]; | |
| dat1rddly = [00]; | |
| dat2rddly = [00]; | |
| dat3rddly = [00]; | |
| cmdrrddly = [00]; | |
| phandle = <0x5b>; | |
| linux,phandle = <0x5b>; | |
| }; | |
| eint0default { | |
| phandle = <0x5e>; | |
| linux,phandle = <0x5e>; | |
| }; | |
| fpcpwrlow { | |
| phandle = <0xa1>; | |
| linux,phandle = <0xa1>; | |
| }; | |
| fpcrstlow { | |
| phandle = <0x9f>; | |
| linux,phandle = <0x9f>; | |
| pins_cmd_dat { | |
| pins = <0xb00>; | |
| output-low; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| mclk2disable@0 { | |
| phandle = <0xa6>; | |
| linux,phandle = <0xa6>; | |
| }; | |
| cam1mipi@0 { | |
| phandle = <0x89>; | |
| linux,phandle = <0x89>; | |
| pins_cmd_dat { | |
| pins = <0x2301>; | |
| }; | |
| pins_cmd_dat1 { | |
| pins = <0x2401>; | |
| }; | |
| pins_cmd_dat2 { | |
| pins = <0x2501>; | |
| }; | |
| pins_cmd_dat3 { | |
| pins = <0x2601>; | |
| }; | |
| pins_cmd_dat4 { | |
| pins = <0x2701>; | |
| }; | |
| pins_cmd_dat5 { | |
| pins = <0x2801>; | |
| }; | |
| }; | |
| toucheint5default { | |
| phandle = <0x60>; | |
| linux,phandle = <0x60>; | |
| }; | |
| mtkfb_default { | |
| phandle = <0x6b>; | |
| linux,phandle = <0x6b>; | |
| }; | |
| otg_ldo_en_high { | |
| phandle = <0x99>; | |
| linux,phandle = <0x99>; | |
| pins_cmd_dat { | |
| pins = <0x4b00>; | |
| slew-rate = <0x01>; | |
| output-high; | |
| }; | |
| }; | |
| mmc1_ins_default { | |
| phandle = <0x55>; | |
| linux,phandle = <0x55>; | |
| }; | |
| gyrodefaultcfg { | |
| phandle = <0x5c>; | |
| linux,phandle = <0x5c>; | |
| }; | |
| mclk2enable@0 { | |
| phandle = <0xa5>; | |
| linux,phandle = <0xa5>; | |
| }; | |
| audexamphigh { | |
| phandle = <0x69>; | |
| linux,phandle = <0x69>; | |
| pins_cmd_dat { | |
| pins = <0x1200>; | |
| slew-rate = <0x01>; | |
| output-high; | |
| }; | |
| }; | |
| iddig_default { | |
| phandle = <0x92>; | |
| linux,phandle = <0x92>; | |
| }; | |
| cam0@0 { | |
| phandle = <0x80>; | |
| linux,phandle = <0x80>; | |
| pins_cmd_dat { | |
| pins = <0x4900>; | |
| output-low; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| cam0@1 { | |
| phandle = <0x81>; | |
| linux,phandle = <0x81>; | |
| pins_cmd_dat { | |
| pins = <0x4900>; | |
| slew-rate = <0x01>; | |
| output-high; | |
| }; | |
| }; | |
| cam0@2 { | |
| phandle = <0x82>; | |
| linux,phandle = <0x82>; | |
| pins_cmd_dat { | |
| pins = <0x4700>; | |
| output-low; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| cam0@3 { | |
| phandle = <0x83>; | |
| linux,phandle = <0x83>; | |
| pins_cmd_dat { | |
| pins = <0x4700>; | |
| slew-rate = <0x01>; | |
| output-high; | |
| }; | |
| }; | |
| cam1@0 { | |
| phandle = <0x84>; | |
| linux,phandle = <0x84>; | |
| pins_cmd_dat { | |
| pins = <0x4c00>; | |
| output-low; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| cam1@1 { | |
| phandle = <0x85>; | |
| linux,phandle = <0x85>; | |
| pins_cmd_dat { | |
| pins = <0x4c00>; | |
| slew-rate = <0x01>; | |
| output-high; | |
| }; | |
| }; | |
| cam1@2 { | |
| phandle = <0x86>; | |
| linux,phandle = <0x86>; | |
| pins_cmd_dat { | |
| pins = <0x4a00>; | |
| output-low; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| cam1@3 { | |
| phandle = <0x87>; | |
| linux,phandle = <0x87>; | |
| pins_cmd_dat { | |
| pins = <0x4a00>; | |
| slew-rate = <0x01>; | |
| output-high; | |
| }; | |
| }; | |
| cam5@2 { | |
| phandle = <0x8c>; | |
| linux,phandle = <0x8c>; | |
| pins_cmd_dat { | |
| pins = <0x5400>; | |
| output-low; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| cam5@3 { | |
| phandle = <0x8d>; | |
| linux,phandle = <0x8d>; | |
| pins_cmd_dat { | |
| pins = <0x5400>; | |
| slew-rate = <0x01>; | |
| output-high; | |
| }; | |
| }; | |
| fpceinthigh { | |
| phandle = <0x9c>; | |
| linux,phandle = <0x9c>; | |
| pins_cmd_dat { | |
| pins = <0xa00>; | |
| slew-rate = <0x01>; | |
| output-high; | |
| }; | |
| }; | |
| lcd_inc25_enp0_gpio { | |
| phandle = <0x75>; | |
| linux,phandle = <0x75>; | |
| pins_cmd_dat { | |
| pins = <0x5500>; | |
| output-low; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| eint@0 { | |
| phandle = <0x5f>; | |
| linux,phandle = <0x5f>; | |
| pins_cmd_dat { | |
| pins = <0xe06>; | |
| bias-disable; | |
| slew-rate = <0x00>; | |
| }; | |
| }; | |
| lcd_inc25_enp1_gpio { | |
| phandle = <0x76>; | |
| linux,phandle = <0x76>; | |
| pins_cmd_dat { | |
| pins = <0x5500>; | |
| slew-rate = <0x01>; | |
| output-high; | |
| }; | |
| }; | |
| mmc1@default { | |
| phandle = <0x57>; | |
| linux,phandle = <0x57>; | |
| pins_clk { | |
| drive-strength = [03]; | |
| }; | |
| pins_cmd { | |
| drive-strength = [03]; | |
| }; | |
| pins_dat { | |
| drive-strength = [03]; | |
| }; | |
| }; | |
| audiodefault { | |
| phandle = <0x66>; | |
| linux,phandle = <0x66>; | |
| }; | |
| mmc1@sdr104 { | |
| phandle = <0x58>; | |
| linux,phandle = <0x58>; | |
| pins_clk { | |
| drive-strength = [03]; | |
| }; | |
| pins_cmd { | |
| drive-strength = [02]; | |
| }; | |
| pins_dat { | |
| drive-strength = [02]; | |
| }; | |
| }; | |
| camdefault { | |
| phandle = <0x7f>; | |
| linux,phandle = <0x7f>; | |
| }; | |
| drvvbus_high { | |
| phandle = <0x96>; | |
| linux,phandle = <0x96>; | |
| pins_cmd_dat { | |
| pins = <0x1300>; | |
| slew-rate = <0x01>; | |
| output-high; | |
| }; | |
| }; | |
| drvvbus_init { | |
| phandle = <0x94>; | |
| linux,phandle = <0x94>; | |
| pins_cmd_dat { | |
| pins = <0x1300>; | |
| slew-rate = <0x01>; | |
| bias-pull-down = <0x00>; | |
| }; | |
| }; | |
| lcd_inc18_enp0_gpio { | |
| phandle = <0x79>; | |
| linux,phandle = <0x79>; | |
| pins_cmd_dat { | |
| pins = <0x5500>; | |
| output-low; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| audexamplow { | |
| phandle = <0x6a>; | |
| linux,phandle = <0x6a>; | |
| pins_cmd_dat { | |
| pins = <0x1200>; | |
| output-low; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| lcd_inc18_enp1_gpio { | |
| phandle = <0x7a>; | |
| linux,phandle = <0x7a>; | |
| pins_cmd_dat { | |
| pins = <0x5500>; | |
| slew-rate = <0x01>; | |
| output-high; | |
| }; | |
| }; | |
| lcd_ldo18_enp0_gpio { | |
| phandle = <0x7b>; | |
| linux,phandle = <0x7b>; | |
| pins_cmd_dat { | |
| pins = <0x1500>; | |
| output-low; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| lcd_bias_enn0_gpio { | |
| phandle = <0x73>; | |
| linux,phandle = <0x73>; | |
| pins_cmd_dat { | |
| pins = <0x1100>; | |
| output-low; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| lcd_ldo18_enp1_gpio { | |
| phandle = <0x7c>; | |
| linux,phandle = <0x7c>; | |
| pins_cmd_dat { | |
| pins = <0x1500>; | |
| slew-rate = <0x01>; | |
| output-high; | |
| }; | |
| }; | |
| lcd_bias_enn1_gpio { | |
| phandle = <0x74>; | |
| linux,phandle = <0x74>; | |
| pins_cmd_dat { | |
| pins = <0x1100>; | |
| slew-rate = <0x01>; | |
| output-high; | |
| }; | |
| }; | |
| iddig_irq_init { | |
| phandle = <0x93>; | |
| linux,phandle = <0x93>; | |
| pins_cmd_dat { | |
| pins = <0x903>; | |
| bias-pull-up = <0x00>; | |
| slew-rate = <0x00>; | |
| }; | |
| }; | |
| otg_ldo_init { | |
| phandle = <0x97>; | |
| linux,phandle = <0x97>; | |
| pins_cmd_dat { | |
| pins = <0x4b00>; | |
| slew-rate = <0x01>; | |
| bias-pull-down = <0x00>; | |
| }; | |
| }; | |
| mode_te_te { | |
| phandle = <0x6d>; | |
| linux,phandle = <0x6d>; | |
| pins_cmd_dat { | |
| pins = <0x4401>; | |
| }; | |
| }; | |
| drvvbus_low { | |
| phandle = <0x95>; | |
| linux,phandle = <0x95>; | |
| pins_cmd_dat { | |
| pins = <0x1300>; | |
| output-low; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| pwm_test_pin_mux_gpio66 { | |
| phandle = <0x70>; | |
| linux,phandle = <0x70>; | |
| pins_cmd_dat { | |
| pins = <0x4201>; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| lcd_ldo28_enp0_gpio { | |
| phandle = <0x7d>; | |
| linux,phandle = <0x7d>; | |
| pins_cmd_dat { | |
| pins = <0x2200>; | |
| output-low; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| lcd_ldo28_enp1_gpio { | |
| phandle = <0x7e>; | |
| linux,phandle = <0x7e>; | |
| pins_cmd_dat { | |
| pins = <0x2200>; | |
| slew-rate = <0x01>; | |
| output-high; | |
| }; | |
| }; | |
| mmc0@register_default { | |
| cmd_edge = [01]; | |
| cmdrddly = [00]; | |
| rdata_edge = [01]; | |
| wdata_edge = [01]; | |
| datwrddly = [00]; | |
| dat0rddly = [00]; | |
| dat1rddly = [00]; | |
| dat2rddly = [00]; | |
| dat3rddly = [00]; | |
| dat4rddly = [00]; | |
| dat5rddly = [00]; | |
| dat6rddly = [00]; | |
| dat7rddly = [00]; | |
| ett-hs200-default = <0xb0 0x380 0x00 0xb0 0x7c00 0x00 0xb4 0x38 0x01 0x04 0x02 0x01 0xf0 0x1f0000 0x00 0xf0 0x7c00000 0x00 0xb4 0x07 0x01 0xf0 0x1f 0x00 0x04 0x100 0x01 0xf8 0x1f000000 0x00 0xf0 0x1f00 0x00 0xb0 0x08 0x01>; | |
| cmdrrddly = [00]; | |
| phandle = <0x54>; | |
| ett-hs200-cells = <0x0c>; | |
| linux,phandle = <0x54>; | |
| }; | |
| rstoutput0 { | |
| phandle = <0x64>; | |
| linux,phandle = <0x64>; | |
| pins_cmd_dat { | |
| pins = <0x1000>; | |
| output-low; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| rstoutput1 { | |
| phandle = <0x65>; | |
| linux,phandle = <0x65>; | |
| pins_cmd_dat { | |
| pins = <0x1000>; | |
| slew-rate = <0x01>; | |
| output-high; | |
| }; | |
| }; | |
| mclk1enable@0 { | |
| phandle = <0x8a>; | |
| linux,phandle = <0x8a>; | |
| pins_cmd_dat { | |
| pins = <0x4801>; | |
| }; | |
| }; | |
| pmicclkmode0 { | |
| phandle = <0x67>; | |
| linux,phandle = <0x67>; | |
| pins_cmd0_dat { | |
| pins = <0x1a00>; | |
| }; | |
| pins_cmd1_dat { | |
| pins = <0x1c00>; | |
| }; | |
| pins_cmd2_dat { | |
| pins = <0x1b00>; | |
| }; | |
| }; | |
| pmicclkmode1 { | |
| phandle = <0x68>; | |
| linux,phandle = <0x68>; | |
| pins_cmd0_dat { | |
| pins = <0x1a01>; | |
| }; | |
| pins_cmd1_dat { | |
| pins = <0x1c01>; | |
| }; | |
| pins_cmd2_dat { | |
| pins = <0x1b01>; | |
| }; | |
| }; | |
| lcm_rst_out0_gpio { | |
| phandle = <0x6e>; | |
| linux,phandle = <0x6e>; | |
| pins_cmd_dat { | |
| pins = <0x4601>; | |
| output-low; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| lcm_rst_out1_gpio { | |
| phandle = <0x6f>; | |
| linux,phandle = <0x6f>; | |
| pins_cmd_dat { | |
| pins = <0x4601>; | |
| slew-rate = <0x01>; | |
| output-high; | |
| }; | |
| }; | |
| fpcspimode0 { | |
| phandle = <0xa2>; | |
| linux,phandle = <0xa2>; | |
| pins_cmd0_dat { | |
| pins = <0x200>; | |
| }; | |
| pins_cmd1_dat { | |
| pins = <0x00>; | |
| }; | |
| pins_cmd2_dat { | |
| pins = <0x300>; | |
| }; | |
| pins_cmd3_dat { | |
| pins = <0x100>; | |
| }; | |
| }; | |
| fpcspimode1 { | |
| phandle = <0xa3>; | |
| linux,phandle = <0xa3>; | |
| pins_cmd0_dat { | |
| pins = <0x201>; | |
| bias-pull-up = <0x00>; | |
| }; | |
| pins_cmd1_dat { | |
| pins = <0x01>; | |
| bias-pull-up = <0x00>; | |
| }; | |
| pins_cmd2_dat { | |
| pins = <0x301>; | |
| bias-pull-up = <0x00>; | |
| }; | |
| pins_cmd3_dat { | |
| pins = <0x101>; | |
| bias-pull-down = <0x00>; | |
| }; | |
| }; | |
| fpcdefault { | |
| phandle = <0x9a>; | |
| linux,phandle = <0x9a>; | |
| }; | |
| mmc0@default { | |
| phandle = <0x53>; | |
| linux,phandle = <0x53>; | |
| pins_clk { | |
| drive-strength = [02]; | |
| }; | |
| pins_cmd { | |
| drive-strength = [02]; | |
| }; | |
| pins_dat { | |
| drive-strength = [02]; | |
| }; | |
| pins_rst { | |
| drive-strength = [02]; | |
| }; | |
| pins_ds { | |
| drive-strength = [02]; | |
| }; | |
| }; | |
| fpcpwrhigh { | |
| phandle = <0xa0>; | |
| linux,phandle = <0xa0>; | |
| }; | |
| otg_ldo_en_low { | |
| phandle = <0x98>; | |
| linux,phandle = <0x98>; | |
| pins_cmd_dat { | |
| pins = <0x4b00>; | |
| output-low; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| lcd_bias_enp0_gpio { | |
| phandle = <0x71>; | |
| linux,phandle = <0x71>; | |
| pins_cmd_dat { | |
| pins = <0x5500>; | |
| output-low; | |
| slew-rate = <0x01>; | |
| }; | |
| }; | |
| mmc1@ddr50 { | |
| phandle = <0x5a>; | |
| linux,phandle = <0x5a>; | |
| pins_clk { | |
| drive-strength = [03]; | |
| }; | |
| pins_cmd { | |
| drive-strength = [02]; | |
| }; | |
| pins_dat { | |
| drive-strength = [02]; | |
| }; | |
| }; | |
| lcd_bias_enp1_gpio { | |
| phandle = <0x72>; | |
| linux,phandle = <0x72>; | |
| pins_cmd_dat { | |
| pins = <0x5500>; | |
| slew-rate = <0x01>; | |
| output-high; | |
| }; | |
| }; | |
| mclk1disable@0 { | |
| phandle = <0x8b>; | |
| linux,phandle = <0x8b>; | |
| pins_cmd_dat { | |
| pins = <0x4800>; | |
| }; | |
| }; | |
| mmc1@sdr50 { | |
| phandle = <0x59>; | |
| linux,phandle = <0x59>; | |
| pins_clk { | |
| drive-strength = [03]; | |
| }; | |
| pins_cmd { | |
| drive-strength = [02]; | |
| }; | |
| pins_dat { | |
| drive-strength = [02]; | |
| }; | |
| }; | |
| mmc1_ins_cfg { | |
| phandle = <0x56>; | |
| linux,phandle = <0x56>; | |
| pins_insert { | |
| pins = <0x5306>; | |
| slew-rate = <0x00>; | |
| input-schmitt-enable = <0x01>; | |
| }; | |
| }; | |
| mode_te_gpio { | |
| phandle = <0x6c>; | |
| linux,phandle = <0x6c>; | |
| pins_cmd_dat { | |
| pins = <0x4400>; | |
| }; | |
| }; | |
| }; | |
| DEVAPC_AO@0x10010000 { | |
| reg = <0x10010000 0x1000>; | |
| compatible = "mediatek,DEVAPC_AO"; | |
| }; | |
| gce@1020a000 { | |
| disp_pwm0_sof = <0x11>; | |
| reg = <0x1020a000 0x1000>; | |
| disp_gamma_frame_done = <0x21>; | |
| interrupts = <0x00 0x55 0x08 0x00 0x56 0x08>; | |
| disp_wdma0_frame_done = <0x1d>; | |
| mdp_rsz0_sof = <0x01>; | |
| mdp_rsz1_sof = <0x02>; | |
| conn_peri_base = <0x18000000 0x07 0xffff0000>; | |
| infra_na3_base = <0x10030000 0x0b 0xffff0000>; | |
| mdp_tdshp_frame_done = <0x15>; | |
| mdp_wrot_read_frame_done = <0x18>; | |
| infra_na4_base = <0x10040000 0x0c 0xffff0000>; | |
| seninf_cam0_fifo_full = <0x49>; | |
| mdp_wrot_write_frame_done = <0x17>; | |
| msdc0_base = <0x11230000 0x13 0xffff0000>; | |
| msdc1_base = <0x11240000 0x14 0xffff0000>; | |
| disp_wdma0_sof = <0x0a>; | |
| g3d_config_base = <0x13000000 0x00 0xffff0000>; | |
| msdc2_base = <0x11250000 0x15 0xffff0000>; | |
| disp_dither_frame_done = <0x22>; | |
| disp_ovl0_sof = <0x06>; | |
| msdc3_base = <0x11260000 0x16 0xffff0000>; | |
| mdp_rdma0_sof = <0x00>; | |
| disp_dsi0_frame_done = <0x25>; | |
| compatible = "mediatek,gce"; | |
| kp_base = <0x10010000 0x09 0xffff0000>; | |
| disp_dither_base = <0x14010000 0x02 0xffff0000>; | |
| mdp_wdma_frame_done = <0x16>; | |
| disp_aal_frame_done = <0x20>; | |
| disp_rdma0_frame_done = <0x1b>; | |
| vdec_gcon_base = <0x16000000 0x05 0xffff0000>; | |
| disp_rdma0_sof = <0x08>; | |
| disp_color_frame_done = <0x1f>; | |
| disp_color_sof = <0x0c>; | |
| mdp_tdshp_sof = <0x03>; | |
| disp_gamma_sof = <0x0e>; | |
| scp_base = <0x10050000 0x0d 0xffff0000>; | |
| disp_dither_sof = <0x0f>; | |
| mdp_rdma0_frame_done = <0x12>; | |
| mmsys_config_base = <0x14000000 0x01 0xffff0000>; | |
| venc_gcon_base = <0x17000000 0x06 0xffff0000>; | |
| buf_underrun_event_0 = <0x30>; | |
| usb0_base = <0x11200000 0x10 0xffff0000>; | |
| stream_done_0 = <0x26>; | |
| stream_done_1 = <0x27>; | |
| stream_done_2 = <0x28>; | |
| stream_done_3 = <0x29>; | |
| stream_done_4 = <0x2a>; | |
| stream_done_5 = <0x2b>; | |
| stream_done_6 = <0x2c>; | |
| stream_done_7 = <0x2d>; | |
| stream_done_8 = <0x2e>; | |
| stream_done_9 = <0x2f>; | |
| mdp_rsz0_frame_done = <0x13>; | |
| usb_sif_base = <0x11210000 0x11 0xffff0000>; | |
| mdp_rsz1_frame_done = <0x14>; | |
| mdp_wdma_sof = <0x04>; | |
| dsi0_te_event = <0x32>; | |
| mm_na_base = <0x14020000 0x03 0xffff0000>; | |
| disp_mutex_reg = <0x14015000 0x1000>; | |
| gcpu_base = <0x10210000 0x0f 0xffff0000>; | |
| mdp_wrot_sof = <0x05>; | |
| mcucfg_base = <0x10200000 0x0e 0xffff0000>; | |
| disp_aal_sof = <0x0d>; | |
| disp_ovl0_frame_done = <0x19>; | |
| topckgen_base = <0x10000000 0x08 0xffff0000>; | |
| apxgpt2_count = <0x10008028>; | |
| imgsys_base = <0x15000000 0x04 0xffff0000>; | |
| scp_sram_base = <0x10020000 0x0a 0xffff0000>; | |
| audio_base = <0x11220000 0x12 0xffff0000>; | |
| pwm_sw_base = <0x1100f000 0x63 0xfffff000>; | |
| isp_frame_done_p2_0 = <0x43>; | |
| isp_frame_done_p2_1 = <0x42>; | |
| }; | |
| step_counter@0 { | |
| compatible = "mediatek,step_counter"; | |
| }; | |
| NFI@0x11001000 { | |
| reg = <0x11001000 0x1000>; | |
| interrupts = <0x00 0x2f 0x08>; | |
| compatible = "mediatek,NFI"; | |
| }; | |
| RESERVED@0x10004000 { | |
| reg = <0x10004000 0x1000>; | |
| compatible = "mediatek,RESERVED"; | |
| }; | |
| adc_hw@11003000 { | |
| reg = <0x11003000 0x1000>; | |
| interrupts = <0x00 0x23 0x02>; | |
| compatible = "mediatek,mt6735-auxadc"; | |
| phandle = <0x32>; | |
| linux,phandle = <0x32>; | |
| adc_channel@ { | |
| compatible = "mediatek,adc_channel"; | |
| mediatek,temperature0 = <0x00>; | |
| mediatek,temperature1 = <0x01>; | |
| status = "okay"; | |
| }; | |
| }; | |
| RESERVED@0x10013000 { | |
| reg = <0x10013000 0x1000>; | |
| compatible = "mediatek,RESERVED"; | |
| }; | |
| msensor@0 { | |
| compatible = "mediatek,msensor"; | |
| }; | |
| WIFI@0x180F0000 { | |
| reg = <0x180f0000 0x5c>; | |
| interrupts = <0x00 0x9b 0x08>; | |
| compatible = "mediatek,WIFI"; | |
| }; | |
| DBGSYS_CTI@0x10112000 { | |
| reg = <0x10112000 0x1000>; | |
| compatible = "mediatek,DBGSYS_CTI"; | |
| }; | |
| hwmsensor@0 { | |
| compatible = "mediatek,hwmsensor"; | |
| }; | |
| dma@0x11000000 { | |
| reg = <0x11000000 0x1000>; | |
| interrupts = <0x00 0x30 0x08>; | |
| compatible = "mediatek,ap_dma"; | |
| phandle = <0x31>; | |
| linux,phandle = <0x31>; | |
| }; | |
| MCUCFG_BIU@0x1020D000 { | |
| reg = <0x1020d000 0x1000>; | |
| compatible = "mediatek,MCUCFG_BIU"; | |
| }; | |
| INFRACFG_AO@0x10001000 { | |
| reg = <0x10001000 0x1000>; | |
| compatible = "mediatek,INFRACFG_AO"; | |
| }; | |
| mdp_rdma@14001000 { | |
| reg = <0x14001000 0x1000>; | |
| interrupts = <0x00 0x71 0x08>; | |
| compatible = "mediatek,mdp_rdma"; | |
| }; | |
| AP_UART0@0x11005000 { | |
| reg = <0x11005000 0x1000>; | |
| interrupts = <0x00 0x2c 0x08>; | |
| compatible = "mediatek,AP_UART0"; | |
| cell-index = <0x00>; | |
| }; | |
| ap_ccif0@1000C000 { | |
| reg = <0x1000c000 0x1000 0x1000d000 0x1000>; | |
| interrupts = <0x00 0x5d 0x08 0x00 0x98 0x02>; | |
| mediatek,ccif_capability = <0x02>; | |
| compatible = "mediatek,ap_ccif0"; | |
| mediatek,md_smem_size = <0x200000>; | |
| phandle = <0x2e>; | |
| linux,phandle = <0x2e>; | |
| }; | |
| shake@0 { | |
| compatible = "mediatek,shake"; | |
| }; | |
| m_alsps_pl@0 { | |
| compatible = "mediatek,m_alsps_pl"; | |
| }; | |
| DBGSYS_DAPROM@0x10110000 { | |
| reg = <0x10110000 0x1000>; | |
| compatible = "mediatek,DBGSYS_DAPROM"; | |
| }; | |
| i2c@11009000 { | |
| reg = <0x11009000 0x1000>; | |
| interrupts = <0x00 0x28 0x08 0x00 0x32 0x08>; | |
| compatible = "mediatek,mt6580-i2c\0mediatek,i2c0"; | |
| clock-div = <0x0a>; | |
| cell-index = <0x00>; | |
| #address-cells = <0x01>; | |
| phandle = <0x33>; | |
| #size-cells = <0x00>; | |
| linux,phandle = <0x33>; | |
| spc_r@21 { | |
| reg = <0x21>; | |
| compatible = "prize,spc_r"; | |
| sensor_type = <0x310>; | |
| pdn_pin = <0x02 0x54 0x00>; | |
| }; | |
| i2c_lcd_bias@3e { | |
| reg = <0x3e>; | |
| compatible = "ti,tps65132"; | |
| status = "okay"; | |
| }; | |
| camera_main_af@0c { | |
| reg = <0x0c>; | |
| compatible = "mediatek,camera_main_af"; | |
| status = "okay"; | |
| }; | |
| camera_main@10 { | |
| reg = <0x10>; | |
| compatible = "mediatek,camera_main"; | |
| status = "okay"; | |
| }; | |
| }; | |
| ISP_PIPEM@0x15000000 { | |
| compatible = "mediatek,ISP_PIPEM"; | |
| }; | |
| AP_DMA_UART1_RX@0x11000600 { | |
| reg = <0x11000600 0x80>; | |
| interrupts = <0x00 0x3b 0x08>; | |
| compatible = "mediatek,AP_DMA_UART1_RX"; | |
| }; | |
| glance_gesture@0 { | |
| compatible = "mediatek,glance_gesture"; | |
| }; | |
| i2c@1100a000 { | |
| reg = <0x1100a000 0x1000>; | |
| interrupts = <0x00 0x29 0x08 0x00 0x33 0x08>; | |
| compatible = "mediatek,mt6580-i2c\0mediatek,i2c1"; | |
| clock-div = <0x0a>; | |
| cell-index = <0x01>; | |
| #address-cells = <0x01>; | |
| phandle = <0x34>; | |
| #size-cells = <0x00>; | |
| linux,phandle = <0x34>; | |
| sw_charger@6a { | |
| reg = <0x6a>; | |
| compatible = "mediatek,swithing_charger"; | |
| status = "okay"; | |
| }; | |
| sw_charger@6b { | |
| reg = <0x6b>; | |
| compatible = "ti,bq24296"; | |
| status = "disable"; | |
| }; | |
| cap_touch@20 { | |
| reg = <0x20>; | |
| compatible = "synaptics,td4100"; | |
| }; | |
| cap_touch@26 { | |
| reg = <0x26>; | |
| compatible = "mstar,msg5846"; | |
| }; | |
| cap_touch@38 { | |
| reg = <0x38>; | |
| compatible = "mediatek,cap_touch1"; | |
| }; | |
| cap_touch@48 { | |
| reg = <0x48>; | |
| compatible = "chipone,icn8xx"; | |
| }; | |
| cap_touch@5d { | |
| reg = <0x5d>; | |
| compatible = "mediatek,cap_touch"; | |
| }; | |
| }; | |
| i2c@1100b000 { | |
| reg = <0x1100b000 0x1000>; | |
| interrupts = <0x00 0x2a 0x08 0x00 0x34 0x08>; | |
| compatible = "mediatek,mt6580-i2c\0mediatek,i2c2"; | |
| clock-div = <0x0a>; | |
| cell-index = <0x02>; | |
| #address-cells = <0x01>; | |
| phandle = <0x35>; | |
| #size-cells = <0x00>; | |
| linux,phandle = <0x35>; | |
| camera_sub_af@0c { | |
| reg = <0x0c>; | |
| compatible = "mediatek,camera_sub_af"; | |
| status = "disable"; | |
| }; | |
| msensor@0c { | |
| power_vol = <0x00>; | |
| i2c_addr = <0x0c 0x00 0x00 0x00>; | |
| is_batch_supported = <0x00>; | |
| i2c_num = <0x02>; | |
| compatible = "mediatek,mxg2320"; | |
| power_id = <0xffff>; | |
| direction = <0x04>; | |
| }; | |
| camera_sub@3c { | |
| reg = <0x3c>; | |
| compatible = "mediatek,camera_sub"; | |
| status = "okay"; | |
| }; | |
| spc_r_1@21 { | |
| reg = <0x21>; | |
| compatible = "prize,spc_r_1"; | |
| sensor_type = <0x32a>; | |
| pdn_pin = <0x02 0x13 0x00>; | |
| }; | |
| gsensor@15 { | |
| reg = <0x15>; | |
| power_vol = <0x00>; | |
| i2c_addr = <0x15 0x00 0x00 0x00>; | |
| is_batch_supported = <0x00>; | |
| i2c_num = <0x02>; | |
| compatible = "memsic,mxc4005xc"; | |
| power_id = <0xffff>; | |
| firlen = <0x00>; | |
| status = "okay"; | |
| direction = <0x02>; | |
| }; | |
| gsensor@18 { | |
| reg = <0x18>; | |
| power_vol = <0x00>; | |
| i2c_addr = <0x18 0x00 0x00 0x00>; | |
| is_batch_supported = <0x00>; | |
| i2c_num = <0x02>; | |
| compatible = "mediatek,accsensor"; | |
| power_id = <0xffff>; | |
| firlen = <0x00>; | |
| status = "okay"; | |
| direction = <0x05>; | |
| }; | |
| gsensor@26 { | |
| power_vol = <0x00>; | |
| i2c_addr = <0x26 0x00 0x00 0x00>; | |
| is_batch_supported = <0x00>; | |
| i2c_num = <0x02>; | |
| compatible = "mediatek,gsensor"; | |
| power_id = <0xffff>; | |
| firlen = <0x00>; | |
| direction = <0x06>; | |
| }; | |
| gsensor@68 { | |
| reg = <0x68>; | |
| compatible = "bosch,bmi160_acc"; | |
| status = "disable"; | |
| }; | |
| gyro@68 { | |
| reg = <0x68>; | |
| power_vol = <0x00>; | |
| i2c_addr = <0x68 0x00 0x00 0x00>; | |
| is_batch_supported = <0x00>; | |
| i2c_num = <0x02>; | |
| compatible = "bosch,bmi160_gyro"; | |
| power_id = <0xffff>; | |
| firlen = <0x00>; | |
| status = "disable"; | |
| direction = <0x01>; | |
| }; | |
| breath_led@5b { | |
| reg = <0x5b>; | |
| compatible = "awinic,aw9106b"; | |
| }; | |
| alsps@23 { | |
| reg = <0x23>; | |
| power_vol = <0x00>; | |
| i2c_addr = <0x23 0x00 0x00 0x00>; | |
| ps_threshold_low = <0x15>; | |
| i2c_num = <0x02>; | |
| pinctrl-0 = <0x51>; | |
| pinctrl-1 = <0x52>; | |
| compatible = "mediatek,alsps"; | |
| ps_threshold_high = <0x1a>; | |
| polling_mode_als = <0x01>; | |
| is_batch_supported_ps = <0x00>; | |
| power_id = <0xffff>; | |
| is_batch_supported_als = <0x00>; | |
| status = "okay"; | |
| polling_mode_ps = <0x00>; | |
| als_level = <0x00 0x1f4 0x5dc 0x7d0 0x1388 0x1b58 0x1f40 0x2328 0x2710 0x3a98 0x4650 0x4e20 0x55f0 0x88b8 0xfff0>; | |
| als_value = <0x00 0x32 0x50 0x64 0x96 0xc8 0x1f4 0x258 0x3e8 0x7d0 0xfa0 0x1770 0x1f40 0x3a98 0x4e20 0x4e20>; | |
| pinctrl-names = "pin_default\0pin_cfg"; | |
| }; | |
| }; | |
| mt_soc_hdmi_pcm { | |
| compatible = "mediatek,mt_soc_pcm_hdmi"; | |
| }; | |
| mt_soc_ul1_PCM { | |
| compatible = "mediatek,mt_soc_pcm_capture"; | |
| }; | |
| INFRACFG@0x10201000 { | |
| reg = <0x10201000 0x1000>; | |
| compatible = "mediatek,INFRACFG"; | |
| }; | |
| mt_soc_ul2_pcm { | |
| compatible = "mediatek,mt_soc_pcm_capture2"; | |
| }; | |
| wake_gesture@0 { | |
| compatible = "mediatek,wake_gesture"; | |
| }; | |
| gyroscope@0 { | |
| pinctrl-0 = <0x5c>; | |
| pinctrl-1 = <0x5d>; | |
| compatible = "mediatek,gyroscope"; | |
| status = "okay"; | |
| phandle = <0x46>; | |
| pinctrl-names = "pin_default\0pin_cfg"; | |
| linux,phandle = <0x46>; | |
| }; | |
| mt_soc_voip_bt_in { | |
| compatible = "mediatek,mt_soc_pcm_bt_dai"; | |
| }; | |
| THERM_CTRL@0x1100D000 { | |
| reg = <0x1100d000 0x1000>; | |
| interrupts = <0x00 0x25 0x08>; | |
| compatible = "mediatek,THERM_CTRL"; | |
| }; | |
| CAM_0@0x15004000 { | |
| reg = <0x15004000 0x1000>; | |
| interrupts = <0x00 0x8b 0x08>; | |
| compatible = "mediatek,CAM_0"; | |
| }; | |
| DRAMC0@0x10207000 { | |
| reg = <0x10207000 0x1000>; | |
| compatible = "mediatek,DRAMC0"; | |
| }; | |
| DISP_PWM@0x1100F000 { | |
| reg = <0x1100f000 0x1000>; | |
| interrupts = <0x00 0x21 0x08>; | |
| compatible = "mediatek,DISP_PWM"; | |
| }; | |
| DSI@0x14012000 { | |
| reg = <0x14012000 0x1000>; | |
| compatible = "mediatek,DSI"; | |
| }; | |
| TOPRGU@0x10007000 { | |
| reg = <0x10007000 0x1000>; | |
| interrupts = <0x00 0x9d 0x02>; | |
| compatible = "mediatek,TOPRGU"; | |
| }; | |
| DISP_OVL0@0x14007000 { | |
| reg = <0x14007000 0x1000>; | |
| interrupts = <0x00 0x77 0x08>; | |
| compatible = "mediatek,DISP_OVL0"; | |
| }; | |
| DRAMC_NAO@0x10206000 { | |
| reg = <0x10206000 0x1000>; | |
| compatible = "mediatek,DRAMC_NAO"; | |
| }; | |
| m_mag_pl@0 { | |
| compatible = "mediatek,m_mag_pl"; | |
| }; | |
| mt_soc_fm_mrgtx_pcm { | |
| compatible = "mediatek,mt_soc_pcm_fmtx"; | |
| }; | |
| AP_UART1@0x11006000 { | |
| reg = <0x11006000 0x1000>; | |
| interrupts = <0x00 0x2d 0x08>; | |
| compatible = "mediatek,AP_UART1"; | |
| cell-index = <0x01>; | |
| }; | |
| gpio@0x10005000 { | |
| reg = <0x10005000 0x1000>; | |
| compatible = "mediatek,gpio"; | |
| phandle = <0x2c>; | |
| linux,phandle = <0x2c>; | |
| }; | |
| DISP_AAL@0x1400E000 { | |
| reg = <0x1400e000 0x1000>; | |
| interrupts = <0x00 0x7e 0x08>; | |
| compatible = "mediatek,DISP_AAL"; | |
| }; | |
| m_glg_pl@0 { | |
| compatible = "mediatek,m_glg_pl"; | |
| }; | |
| mt_soc_hp_impedance_pcm { | |
| compatible = "mediatek,Mt_soc_pcm_hp_impedance"; | |
| }; | |
| mt_soc_deep_buffer_dl_pcm { | |
| compatible = "mediatek,mt_soc_pcm_deep_buffer_dl"; | |
| }; | |
| MM_MUTEX@0x14015000 { | |
| reg = <0x14015000 0x1000>; | |
| interrupts = <0x00 0x70 0x08>; | |
| compatible = "mediatek,MM_MUTEX"; | |
| }; | |
| mt_soc_i2s0_awb_pcm { | |
| compatible = "mediatek,mt_soc_pcm_i2s0_awb"; | |
| }; | |
| activity@0 { | |
| compatible = "mediatek,activity"; | |
| }; | |
| PERICFG@0x10003000 { | |
| reg = <0x10003000 0x1000>; | |
| compatible = "mediatek,PERICFG"; | |
| }; | |
| accdet { | |
| accdet-plugout-debounce = <0x14>; | |
| interrupts = <0x0e 0x08>; | |
| pinctrl-0 = <0x5e>; | |
| pinctrl-1 = <0x5f>; | |
| compatible = "mediatek,mt6580-accdet"; | |
| accdet-mic-vol = <0x07>; | |
| headset-three-key-threshold = <0x00 0x5a 0xf0 0x1f4>; | |
| debounce = <0x0e 0x3e800>; | |
| accdet-mic-mode = <0x01>; | |
| status = "okay"; | |
| headset-four-key-threshold = <0x00 0x3b 0x7b 0xc3 0x1c2>; | |
| phandle = <0x37>; | |
| pinctrl-names = "default\0state_eint_as_int"; | |
| linux,phandle = <0x37>; | |
| headset-mode-setting = <0x500 0x200 0x01 0x1f0 0x800 0x800 0x20>; | |
| interrupt-parent = <0x03>; | |
| }; | |
| mdp_rsz0@14002000 { | |
| reg = <0x14002000 0x1000>; | |
| interrupts = <0x00 0x72 0x08>; | |
| compatible = "mediatek,mdp_rsz0"; | |
| }; | |
| mt_soc_dai_name { | |
| compatible = "mediatek,mt_soc_dai_stub"; | |
| }; | |
| m_wag_pl@0 { | |
| compatible = "mediatek,m_wag_pl"; | |
| }; | |
| m_acc_pl@0 { | |
| compatible = "mediatek,m_acc_pl"; | |
| }; | |
| DBGSYS_MDSYS@0x10120000 { | |
| reg = <0x10120000 0x10000>; | |
| compatible = "mediatek,DBGSYS_MDSYS"; | |
| }; | |
| DISP_RDMA0@0x14009000 { | |
| reg = <0x14009000 0x1000>; | |
| interrupts = <0x00 0x79 0x08>; | |
| compatible = "mediatek,DISP_RDMA0"; | |
| }; | |
| CAM_1@0x15005000 { | |
| reg = <0x15005000 0x1000>; | |
| compatible = "mediatek,CAM_1"; | |
| }; | |
| mt_soc_fm_i2s_pcm { | |
| compatible = "mediatek,mt_soc_pcm_fm_i2s"; | |
| }; | |
| DISP_OVL1@0x14008000 { | |
| reg = <0x14008000 0x1000>; | |
| compatible = "mediatek,DISP_OVL1"; | |
| }; | |
| SMI_LARB0@0x14016000 { | |
| reg = <0x14016000 0x1000>; | |
| interrupts = <0x00 0x85 0x08>; | |
| compatible = "mediatek,SMI_LARB0"; | |
| }; | |
| dsi_te { | |
| interrupts = <0x44 0x01>; | |
| compatible = "mediatek, dsi_te-eint"; | |
| debounce = <0x44 0x00>; | |
| status = "okay"; | |
| phandle = <0x49>; | |
| linux,phandle = <0x49>; | |
| interrupt-parent = <0x03>; | |
| }; | |
| IOCFG_B@0x10015000 { | |
| reg = <0x10015000 0x1000>; | |
| compatible = "mediatek,IOCFG_B"; | |
| }; | |
| mdp_wdma@14004000 { | |
| reg = <0x14004000 0x1000>; | |
| interrupts = <0x00 0x75 0x08>; | |
| compatible = "mediatek,mdp_wdma"; | |
| }; | |
| mt_soc_voice_md1 { | |
| compatible = "mediatek,mt_soc_pcm_voice_md1"; | |
| }; | |
| mt_soc_voice_md2 { | |
| compatible = "mediatek,mt_soc_pcm_voice_md2"; | |
| }; | |
| EFUSEC@0x10009000 { | |
| reg = <0x10009000 0x1000>; | |
| compatible = "mediatek,EFUSEC"; | |
| }; | |
| touch@0 { | |
| tpd-filter-pixel-density = <0x5d>; | |
| interrupts = <0x05 0x01>; | |
| pinctrl-0 = <0x60>; | |
| pinctrl-1 = <0x61>; | |
| pinctrl-2 = <0x62>; | |
| pinctrl-3 = <0x63>; | |
| pinctrl-4 = <0x64>; | |
| pinctrl-5 = <0x65>; | |
| compatible = "mediatek,mt6580-touch"; | |
| tpd-max-touch-num = <0x05>; | |
| tpd-key-dim-local = <0x64 0x546 0x64 0x28 0x168 0x546 0x64 0x28 0x258 0x546 0x64 0x28 0x00 0x00 0x00 0x00>; | |
| use-tpd-button = <0x01>; | |
| vtouch-supply = <0x05>; | |
| tpd-filter-custom-prameters = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; | |
| debounce = <0x05 0x00>; | |
| tpd-key-num = <0x03>; | |
| tpd-filter-enable = <0x01>; | |
| status = "okay"; | |
| tpd-resolution = <0x2d0 0x500>; | |
| phandle = <0x36>; | |
| tpd-key-local = <0x8b 0xac 0x9e 0x00>; | |
| tpd-filter-custom-speed = <0x00 0x00 0x00>; | |
| pinctrl-names = "default\0state_eint_as_int\0state_eint_output0\0state_eint_output1\0state_rst_output0\0state_rst_output1"; | |
| linux,phandle = <0x36>; | |
| interrupt-parent = <0x03>; | |
| }; | |
| syscfg_pctl_a@0x10005000 { | |
| reg = <0x10211000 0x1000>; | |
| compatible = "mediatek,mt6580-pctl-a-syscfg\0syscon"; | |
| phandle = <0x04>; | |
| linux,phandle = <0x04>; | |
| }; | |
| spi@1100c000 { | |
| reg = <0x1100c000 0x1000>; | |
| interrupts = <0x00 0x40 0x08>; | |
| compatible = "mediatek,mt6580-spi"; | |
| cell-index = <0x00>; | |
| mediatek,spi-padmacro = <0x00>; | |
| }; | |
| MIPI_TX_CONFIG@0x14018000 { | |
| reg = <0x14018000 0x1000>; | |
| compatible = "mediatek,MIPI_TX_CONFIG"; | |
| }; | |
| DISP_RDMA1@0x1400A000 { | |
| reg = <0x1400a000 0x1000>; | |
| compatible = "mediatek,DISP_RDMA1"; | |
| }; | |
| DISPSYS@0x14007000 { | |
| reg = <0x14000000 0x1000 0x14007000 0x1000 0x14008000 0x1000 0x14009000 0x1000 0x1400a000 0x1000 0x1400b000 0x1000 0x1400c000 0x1000 0x1400d000 0x1000 0x1400e000 0x1000 0x1400f000 0x1000 0x14010000 0x1000 0x14011000 0x1000 0x14012000 0x1000 0x14013000 0x1000 0x1100f000 0x1000 0x14015000 0x1000 0x14016000 0x1000 0x14017000 0x1000 0x14018000 0x1000>; | |
| interrupts = <0x00 0x00 0x08 0x00 0x77 0x08 0x00 0x00 0x08 0x00 0x79 0x08 0x00 0x00 0x08 0x00 0x7b 0x08 0x00 0x7c 0x08 0x00 0x00 0x08 0x00 0x7e 0x08 0x00 0x7f 0x08 0x00 0x80 0x08 0x00 0x00 0x08 0x00 0x82 0x08 0x00 0x00 0x08 0x00 0x00 0x08 0x00 0x70 0x08 0x00 0x00 0x08 0x00 0x00 0x08 0x00 0x00 0x08>; | |
| compatible = "mediatek,DISPSYS"; | |
| }; | |
| mtkfb@0 { | |
| pinctrl-10 = <0x75>; | |
| pinctrl-11 = <0x76>; | |
| pinctrl-12 = <0x77>; | |
| pinctrl-13 = <0x78>; | |
| pinctrl-14 = <0x79>; | |
| pinctrl-15 = <0x7a>; | |
| pinctrl-16 = <0x7b>; | |
| pinctrl-17 = <0x7c>; | |
| pinctrl-18 = <0x7d>; | |
| pinctrl-19 = <0x7e>; | |
| pinctrl-0 = <0x6b>; | |
| pinctrl-1 = <0x6c>; | |
| pinctrl-2 = <0x6d>; | |
| pinctrl-3 = <0x6e>; | |
| pinctrl-4 = <0x6f>; | |
| pinctrl-5 = <0x70>; | |
| pinctrl-6 = <0x71>; | |
| pinctrl-7 = <0x72>; | |
| pinctrl-8 = <0x73>; | |
| pinctrl-9 = <0x74>; | |
| compatible = "mediatek,mtkfb"; | |
| status = "okay"; | |
| phandle = <0x48>; | |
| pinctrl-names = "default\0mode_te_gpio\0mode_te_te\0lcm_rst_out0_gpio\0lcm_rst_out1_gpio\0pwm_test_pin_mux_gpio66\0lcd_bias_enp0_gpio\0lcd_bias_enp1_gpio\0lcd_bias_enn0_gpio\0lcd_bias_enn1_gpio\0lcd_inc25_enp0_gpio\0lcd_inc25_enp1_gpio\0lcd_inc33_enp0_gpio\0lcd_inc33_enp1_gpio\0lcd_inc18_enp0_gpio\0lcd_inc18_enp1_gpio\0lcd_ldo18_enp0_gpio\0lcd_ldo18_enp1_gpio\0lcd_ldo28_enp0_gpio\0lcd_ldo28_enp1_gpio"; | |
| linux,phandle = <0x48>; | |
| }; | |
| mt_soc_fm_i2s_awb_pcm { | |
| compatible = "mediatek,mt_soc_pcm_fm_i2s_awb"; | |
| }; | |
| m_baro_pl@0 { | |
| compatible = "mediatek,m_baro_pl"; | |
| }; | |
| pick_up@0 { | |
| compatible = "mediatek,pick_up"; | |
| }; | |
| m_step_c_pl@0 { | |
| compatible = "mediatek,m_step_c_pl"; | |
| }; | |
| btif_tx@11000380 { | |
| reg = <0x11000380 0x80>; | |
| interrupts = <0x00 0x36 0x08>; | |
| compatible = "mediatek,btif_tx"; | |
| phandle = <0x39>; | |
| linux,phandle = <0x39>; | |
| }; | |
| BTCVSD@0x10001000 { | |
| reg = <0x10001000 0x1000 0x18000000 0x10000 0x18080000 0x8000>; | |
| interrupts = <0x00 0x99 0x08>; | |
| compatible = "mediatek,audio_bt_cvsd"; | |
| offset = <0xc00 0x02 0xfd0 0xfd4 0xfd8>; | |
| }; | |
| MIPI_CONFG@0x10011000 { | |
| reg = <0x10011000 0x1000>; | |
| compatible = "mediatek,MIPI_CONFG"; | |
| }; | |
| mt_soc_dummy_pcm { | |
| compatible = "mediatek,mt_soc_pcm_dummy"; | |
| }; | |
| mt_soc_tdmrx_pcm { | |
| compatible = "mediatek,mt_soc_tdm_capture"; | |
| }; | |
| DPI@0x14013000 { | |
| reg = <0x14013000 0x1000>; | |
| compatible = "mediatek,DPI"; | |
| }; | |
| FHCTL@0x11004000 { | |
| reg = <0x11004000 0x1000>; | |
| compatible = "mediatek,FHCTL"; | |
| }; | |
| mt_soc_routing_pcm { | |
| compatible = "mediatek,mt_soc_pcm_routing"; | |
| }; | |
| mt_soc_codec_dummy_name { | |
| compatible = "mediatek,mt_soc_codec_dummy"; | |
| }; | |
| keypad@10002000 { | |
| reg = <0x10002000 0x1000>; | |
| interrupts = <0x00 0x6d 0x02>; | |
| mediatek,kpd-use-extend-type = <0x00>; | |
| mediatek,kpd-sw-pwrkey = <0x74>; | |
| compatible = "mediatek,mt6580-keypad"; | |
| mediatek,kpd-hw-dl-key0 = <0x01>; | |
| mediatek,kpd-hw-dl-key1 = <0x00>; | |
| mediatek,kpd-hw-dl-key2 = <0x08>; | |
| mediatek,kpd-pwrkey-eint-gpio = <0x00>; | |
| mediatek,kpd-hw-map-num = <0x48>; | |
| mediatek,kpd-pwkey-gpio-din = <0x00>; | |
| mediatek,kpd-hw-init-map = <0x72 0x73 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; | |
| status = "okay"; | |
| mediatek,kpd-hw-factory-key = <0x00>; | |
| mediatek,kpd-key-debounce = <0x400>; | |
| mediatek,kpd-hw-recovery-key = <0x01>; | |
| phandle = <0x2a>; | |
| mediatek,kpd-hw-pwrkey = <0x08>; | |
| linux,phandle = <0x2a>; | |
| }; | |
| IOCFG_L@0x10016000 { | |
| reg = <0x10016000 0x1000>; | |
| compatible = "mediatek,IOCFG_L"; | |
| }; | |
| heart_rate@0 { | |
| compatible = "mediatek,heart_rate"; | |
| }; | |
| INFRA_MBIST@0x10012000 { | |
| reg = <0x10012000 0x1000>; | |
| compatible = "mediatek,INFRA_MBIST"; | |
| }; | |
| kd_camera_hw1@15008000 { | |
| reg = <0x15008000 0x1000>; | |
| vcama_main2-supply = <0x0a>; | |
| pinctrl-10 = <0x89>; | |
| pinctrl-11 = <0x8a>; | |
| pinctrl-12 = <0x8b>; | |
| pinctrl-13 = <0x8a>; | |
| pinctrl-14 = <0x8b>; | |
| pinctrl-15 = <0x8c>; | |
| pinctrl-16 = <0x8d>; | |
| pinctrl-0 = <0x7f>; | |
| pinctrl-1 = <0x80>; | |
| pinctrl-2 = <0x81>; | |
| pinctrl-3 = <0x82>; | |
| pinctrl-4 = <0x83>; | |
| pinctrl-5 = <0x84>; | |
| pinctrl-6 = <0x85>; | |
| pinctrl-7 = <0x86>; | |
| pinctrl-8 = <0x87>; | |
| pinctrl-9 = <0x88>; | |
| vcamio-supply = <0x4d>; | |
| compatible = "mediatek,camera_hw"; | |
| vcamd_main2-supply = <0x0b>; | |
| vcamaf-supply = <0x0c>; | |
| vcamd_sub-supply = <0x0b>; | |
| vcamd-supply = <0x0b>; | |
| vcamio_main2-supply = <0x4d>; | |
| vcama-supply = <0x0a>; | |
| vcamio_sub-supply = <0x4d>; | |
| status = "okay"; | |
| phandle = <0x43>; | |
| pinctrl-names = "default\0cam0_rst0\0cam0_rst1\0cam0_pnd0\0cam0_pnd1\0cam1_rst0\0cam1_rst1\0cam1_pnd0\0cam1_pnd1\0cam1_gpio_serial\0cam1_gpio_mipi\0cam_mclk1_enable\0cam_mclk1_disable\0cam_mclk2_enable\0cam_mclk2_disable\0cam5_pnd0\0cam5_pnd1"; | |
| linux,phandle = <0x43>; | |
| vcama_sub-supply = <0x0a>; | |
| }; | |
| mt_soc_i2s0_pcm { | |
| compatible = "mediatek,mt_soc_pcm_dl1_i2s0"; | |
| }; | |
| AP_DMA_UART0_TX@0x11000480 { | |
| reg = <0x11000480 0x80>; | |
| interrupts = <0x00 0x38 0x08>; | |
| compatible = "mediatek,AP_DMA_UART0_TX"; | |
| }; | |
| mt_soc_mrgrx_awb_pcm { | |
| compatible = "mediatek,mt_soc_pcm_mrgrx_awb"; | |
| }; | |
| mt_soc_voip_bt_out { | |
| compatible = "mediatek,mt_soc_pcm_dl1_bt"; | |
| }; | |
| DISP_GAMMA@0x1400F000 { | |
| reg = <0x1400f000 0x1000>; | |
| interrupts = <0x00 0x7f 0x08>; | |
| compatible = "mediatek,DISP_GAMMA"; | |
| }; | |
| sensorHub@0 { | |
| compatible = "mediatek,sensorHub"; | |
| }; | |
| btif@1100e000 { | |
| reg = <0x1100e000 0x1000>; | |
| interrupts = <0x00 0x43 0x08>; | |
| compatible = "mediatek,btif"; | |
| phandle = <0x3b>; | |
| linux,phandle = <0x3b>; | |
| }; | |
| m_act_pl@0 { | |
| compatible = "mediatek,m_act_pl"; | |
| }; | |
| mdp_rsz1@14003000 { | |
| reg = <0x14003000 0x1000>; | |
| interrupts = <0x00 0x73 0x08>; | |
| compatible = "mediatek,mdp_rsz1"; | |
| }; | |
| mt_soc_routing_dai_name { | |
| compatible = "mediatek,mt_soc_dai_routing"; | |
| }; | |
| MALI@0x13010000 { | |
| reg = <0x13010000 0x10000>; | |
| compatible = "mediatek,MALI"; | |
| }; | |
| m4u@10203000 { | |
| reg = <0x10203000 0x1000>; | |
| interrupts = <0x00 0x51 0x08>; | |
| compatible = "mediatek,m4u"; | |
| cell-index = <0x00>; | |
| }; | |
| mmsys_config@14000000 { | |
| reg = <0x14000000 0x1000>; | |
| interrupts = <0x00 0x84 0x08>; | |
| compatible = "mediatek,mmsys_config"; | |
| }; | |
| BAT_NOTIFY { | |
| compatible = "mediatek,bat_notify"; | |
| }; | |
| DDRPHY@0x10208000 { | |
| reg = <0x10208000 0x1000>; | |
| compatible = "mediatek,DDRPHY"; | |
| }; | |
| m_fdn_pl@0 { | |
| compatible = "mediatek,m_fdn_pl"; | |
| }; | |
| G3D_CONFIG@0x13000000 { | |
| reg = <0x13000000 0x1000>; | |
| compatible = "mediatek,G3D_CONFIG"; | |
| }; | |
| PWRAP@0x1000F000 { | |
| reg = <0x1000f000 0x1000>; | |
| interrupts = <0x00 0x6c 0x00>; | |
| compatible = "mediatek,PWRAP"; | |
| }; | |
| SMI_LARB1@0x15001000 { | |
| reg = <0x15001000 0x1000>; | |
| interrupts = <0x00 0x88 0x08>; | |
| compatible = "mediatek,SMI_LARB1"; | |
| }; | |
| seninf_top@15008000 { | |
| reg = <0x15008000 0x1000>; | |
| interrupts = <0x00 0x8e 0x08>; | |
| compatible = "mediatek,SENINF_TOP"; | |
| }; | |
| cpu_dbgapb@10170000 { | |
| num = <0x04>; | |
| reg = <0x10170000 0x2000 0x10172000 0x2000 0x10174000 0x2000 0x10176000 0x2000>; | |
| compatible = "mediatek,hw_dbg"; | |
| phandle = <0x2d>; | |
| linux,phandle = <0x2d>; | |
| }; | |
| barometer@0 { | |
| compatible = "mediatek,barometer"; | |
| }; | |
| mt_soc_i2s0dl1_pcm { | |
| compatible = "mediatek,mt_soc_pcm_dl1_i2s0Dl1"; | |
| }; | |
| AES@0x1000E000 { | |
| reg = <0x1000e000 0x1000>; | |
| compatible = "mediatek,AES"; | |
| }; | |
| IOCFG_R@0x10017000 { | |
| reg = <0x10017000 0x1000>; | |
| compatible = "mediatek,IOCFG_R"; | |
| }; | |
| hacc@0x1000A000 { | |
| reg = <0x1000a000 0x1000>; | |
| interrupts = <0x00 0x6e 0x00>; | |
| compatible = "mediatek,hacc"; | |
| }; | |
| SMI_COMMON@0x14017000 { | |
| reg = <0x14017000 0x1000 0x14016000 0x1000 0x15001000 0x1000>; | |
| compatible = "mediatek,SMI_COMMON"; | |
| }; | |
| sys_cirq@10202000 { | |
| reg = <0x10202000 0x1000>; | |
| interrupts = <0x00 0x9e 0x08>; | |
| compatible = "mediatek,mt6580-sys_cirq\0mediatek,mt6735-sys_cirq"; | |
| mediatek,cirq_num = <0x7e>; | |
| mediatek,spi_start_offset = <0x20>; | |
| phandle = <0x30>; | |
| linux,phandle = <0x30>; | |
| }; | |
| usbphy@0 { | |
| compatible = "usb-nop-xceiv"; | |
| phandle = <0x3f>; | |
| linux,phandle = <0x3f>; | |
| }; | |
| MCUCFG@0x10200000 { | |
| reg = <0x10200000 0x1000>; | |
| compatible = "mediatek,MCUCFG"; | |
| }; | |
| bus_dbg@1020b000 { | |
| reg = <0x1020b000 0x1000>; | |
| interrupts = <0x00 0x49 0x08>; | |
| compatible = "mediatek,bus_dbg-v2"; | |
| two_stage_timeout = <0x01>; | |
| }; | |
| DBGSYS_DEM@0x1011A000 { | |
| reg = <0x1011a000 0x1000>; | |
| compatible = "mediatek,DBGSYS_DEM"; | |
| }; | |
| gsensor@0 { | |
| compatible = "mediatek,gsensor"; | |
| }; | |
| APMIXED@0x10018000 { | |
| reg = <0x10018000 0x1000>; | |
| compatible = "mediatek,APMIXED"; | |
| }; | |
| USB0@0x11100000 { | |
| dma = <0x01>; | |
| reg = <0x11100000 0x10000 0x11110000 0x10000>; | |
| mode = <0x02>; | |
| interrupts = <0x00 0x20 0x08>; | |
| soft_con = <0x01>; | |
| iddig_gpio = <0x09 0x03>; | |
| pinctrl-0 = <0x92>; | |
| pinctrl-1 = <0x93>; | |
| pinctrl-2 = <0x94>; | |
| pinctrl-3 = <0x95>; | |
| pinctrl-4 = <0x96>; | |
| pinctrl-5 = <0x97>; | |
| pinctrl-6 = <0x98>; | |
| pinctrl-7 = <0x99>; | |
| compatible = "mediatek,USB0"; | |
| multipoint = <0x01>; | |
| dyn_fifo = <0x01>; | |
| drvvbus_gpio = <0x0a 0x03>; | |
| cell-index = <0x00>; | |
| status = "okay"; | |
| num_eps = <0x10>; | |
| phandle = <0x3d>; | |
| dma_channels = <0x08>; | |
| pinctrl-names = "iddig_default\0iddig_irq_init\0drvvbus_init\0drvvbus_low\0drvvbus_high\0otg_ldo_init\0otg_ldo_en_low\0otg_ldo_en_high"; | |
| linux,phandle = <0x3d>; | |
| usbiddig { | |
| interrupts = <0x09 0x08>; | |
| compatible = "mediatek,usb_iddig_eint"; | |
| debounce = <0x09 0x64>; | |
| phandle = <0x3e>; | |
| linux,phandle = <0x3e>; | |
| interrupt-parent = <0x03>; | |
| }; | |
| }; | |
| AP_DMA_UART1_TX@0x11000580 { | |
| reg = <0x11000580 0x80>; | |
| interrupts = <0x00 0x3a 0x08>; | |
| compatible = "mediatek,AP_DMA_UART1_TX"; | |
| }; | |
| mdp_wrot@14005000 { | |
| reg = <0x14005000 0x1000>; | |
| interrupts = <0x00 0x76 0x08>; | |
| compatible = "mediatek,mdp_wrot"; | |
| }; | |
| TRNG@0x1020C000 { | |
| reg = <0x1020c000 0x1000>; | |
| interrupts = <0x00 0x57 0x08>; | |
| compatible = "mediatek,TRNG"; | |
| }; | |
| MCUSYS_CFGREG@0x1020000 { | |
| reg = <0x1020000 0x200>; | |
| compatible = "mediatek,MCUSYS_CFGREG_BASE"; | |
| }; | |
| mt_soc_uldlloopback_pcm { | |
| compatible = "mediatek,mt_soc_pcm_uldlloopback"; | |
| }; | |
| mt_soc_voice_md1_bt { | |
| compatible = "mediatek,mt_soc_pcm_voice_md1_bt"; | |
| }; | |
| mt_soc_voice_md2_bt { | |
| compatible = "mediatek,mt_soc_pcm_voice_md2_bt"; | |
| }; | |
| m_pdr_pl@0 { | |
| compatible = "mediatek,m_pdr_pl"; | |
| }; | |
| m_gyro_pl@0 { | |
| compatible = "mediatek,m_gyro_pl"; | |
| }; | |
| mt_soc_dl2_pcm { | |
| compatible = "mediatek,mt_soc_pcm_dl2"; | |
| }; | |
| IMGSYS_CONFIG@0x15000000 { | |
| reg = <0x15000000 0x1000>; | |
| compatible = "mediatek,IMGSYS_CONFIG"; | |
| }; | |
| m_batch_pl@0 { | |
| compatible = "mediatek,m_batch_pl"; | |
| }; | |
| m_tilt_pl@0 { | |
| compatible = "mediatek,m_tilt_pl"; | |
| }; | |
| pedometer@0 { | |
| compatible = "mediatek,pedometer"; | |
| }; | |
| DISP_WDMA@0x1400B000 { | |
| reg = <0x1400b000 0x1000>; | |
| interrupts = <0x00 0x7b 0x08>; | |
| compatible = "mediatek,DISP_WDMA"; | |
| }; | |
| mt_soc_dl1_awb_pcm { | |
| compatible = "mediatek,mt_soc_pcm_dl1_awb"; | |
| }; | |
| tilt_detector@0 { | |
| compatible = "mediatek,tilt_detector"; | |
| }; | |
| kd_camera_hw2@15008000 { | |
| reg = <0x15008000 0x1000>; | |
| compatible = "mediatek,camera_hw2"; | |
| phandle = <0x44>; | |
| linux,phandle = <0x44>; | |
| }; | |
| als_ps@0 { | |
| pinctrl-0 = <0x51>; | |
| pinctrl-1 = <0x52>; | |
| compatible = "mediatek,als_ps"; | |
| status = "okay"; | |
| phandle = <0x45>; | |
| pinctrl-names = "pin_default\0pin_cfg"; | |
| linux,phandle = <0x45>; | |
| }; | |
| bat_comm { | |
| compatible = "mediatek,battery"; | |
| phandle = <0x29>; | |
| linux,phandle = <0x29>; | |
| }; | |
| SRAMROM@0x10209000 { | |
| reg = <0x10209000 0x1000>; | |
| compatible = "mediatek,SRAMROM"; | |
| }; | |
| m_hrm_pl@0 { | |
| compatible = "mediatek,m_hrm_pl"; | |
| }; | |
| VENC@0x15009000 { | |
| reg = <0x15009000 0x1000>; | |
| interrupts = <0x00 0x8a 0x08>; | |
| compatible = "mediatek,VENC"; | |
| }; | |
| PTP_FSM@0x1100D000 { | |
| reg = <0x1100d000 0x1000>; | |
| interrupts = <0x00 0x2b 0x08>; | |
| compatible = "mediatek,PTP_FSM"; | |
| }; | |
| DISP_CCORR@0x1400D000 { | |
| reg = <0x1400d000 0x1000>; | |
| compatible = "mediatek,DISP_CCORR"; | |
| }; | |
| VDEC@0x1500B000 { | |
| reg = <0x1500b000 0x1000>; | |
| interrupts = <0x00 0x89 0x08>; | |
| compatible = "mediatek,VDEC"; | |
| }; | |
| DISP_DITHER@0x14010000 { | |
| reg = <0x14010000 0x1000>; | |
| interrupts = <0x00 0x80 0x08>; | |
| compatible = "mediatek,DISP_DITHER"; | |
| }; | |
| APXGPT@0x10008000 { | |
| reg = <0x10008000 0x1000>; | |
| interrupts = <0x00 0x5c 0x08>; | |
| compatible = "mediatek,APXGPT"; | |
| clock-frequency = <0xc65d40>; | |
| }; | |
| m_inpk_pl@0 { | |
| compatible = "mediatek,m_inpk_pl"; | |
| }; | |
| mt_soc_dl1_pcm@11140000 { | |
| reg = <0x11140000 0x1000>; | |
| interrupts = <0x00 0x50 0x08>; | |
| pinctrl-0 = <0x66>; | |
| pinctrl-1 = <0x67>; | |
| pinctrl-2 = <0x68>; | |
| pinctrl-3 = <0x69>; | |
| pinctrl-4 = <0x6a>; | |
| compatible = "mediatek,mt_soc_pcm_dl1"; | |
| audmiso-gpio = <0x1c 0x00>; | |
| status = "okay"; | |
| audclk-gpio = <0x1a 0x00>; | |
| phandle = <0x40>; | |
| audmosi-gpio = <0x1b 0x00>; | |
| pinctrl-names = "default\0audpmicclk-mode0\0audpmicclk-mode1\0extamp-pullhigh\0extamp-pulllow"; | |
| linux,phandle = <0x40>; | |
| }; | |
| IOCFG_T@0x10014000 { | |
| reg = <0x10014000 0x1000>; | |
| compatible = "mediatek,IOCFG_T"; | |
| }; | |
| MDI@0x11160000 { | |
| reg = <0x11160000 0x10000>; | |
| compatible = "mediatek,MDI"; | |
| }; | |
| mt_soc_codec_name { | |
| compatible = "mediatek,mt_soc_codec_63xx"; | |
| }; | |
| DISP_UFOE@0x14011000 { | |
| reg = <0x14011000 0x1000>; | |
| compatible = "mediatek,DISP_UFOE"; | |
| }; | |
| ISPSYS@0x15000000 { | |
| reg = <0x15004000 0x9000 0x15000000 0x10000 0x10011000 0x4000 0x10017000 0x1000>; | |
| interrupts = <0x00 0x8e 0x08 0x00 0x8b 0x08>; | |
| compatible = "mediatek,ISPSYS"; | |
| }; | |
| mcucfg@10200000 { | |
| reg = <0x10200000 0x200>; | |
| compatible = "mediatek,mt6580-mcucfg"; | |
| phandle = <0x2f>; | |
| linux,phandle = <0x2f>; | |
| }; | |
| }; | |
| odm { | |
| compatible = "simple-bus"; | |
| phandle = <0x50>; | |
| linux,phandle = <0x50>; | |
| led@0 { | |
| data = <0x01>; | |
| compatible = "mediatek,red"; | |
| led_mode = <0x00>; | |
| pwm_config = <0x00 0x00 0x00 0x00 0x00>; | |
| }; | |
| led@1 { | |
| data = <0x01>; | |
| compatible = "mediatek,green"; | |
| led_mode = <0x00>; | |
| pwm_config = <0x00 0x00 0x00 0x00 0x00>; | |
| }; | |
| led@2 { | |
| data = <0x01>; | |
| compatible = "mediatek,blue"; | |
| led_mode = <0x00>; | |
| pwm_config = <0x00 0x00 0x00 0x00 0x00>; | |
| }; | |
| led@3 { | |
| data = <0x01>; | |
| compatible = "mediatek,jogball-backlight"; | |
| led_mode = <0x00>; | |
| pwm_config = <0x00 0x00 0x00 0x00 0x00>; | |
| }; | |
| led@4 { | |
| data = <0x01>; | |
| compatible = "mediatek,keyboard-backlight"; | |
| led_mode = <0x00>; | |
| pwm_config = <0x00 0x00 0x00 0x00 0x00>; | |
| }; | |
| led@5 { | |
| data = <0x01>; | |
| compatible = "mediatek,button-backlight"; | |
| led_mode = <0x00>; | |
| pwm_config = <0x00 0x00 0x00 0x00 0x00>; | |
| }; | |
| led@6 { | |
| data = <0x01>; | |
| compatible = "mediatek,lcd-backlight"; | |
| led_mode = <0x05>; | |
| pwm_config = <0x00 0x00 0x00 0x00 0x00>; | |
| }; | |
| vibrator@0 { | |
| compatible = "mediatek,vibrator"; | |
| vib_limit = <0x09>; | |
| vib_timer = <0x0f>; | |
| vib_vol = <0x06>; | |
| phandle = <0xa4>; | |
| linux,phandle = <0xa4>; | |
| }; | |
| }; | |
| pmu { | |
| interrupts = <0x00 0x04 0x08 0x00 0x05 0x08 0x00 0x06 0x08 0x00 0x07 0x08>; | |
| compatible = "arm,cortex-a7-pmu"; | |
| }; | |
| cpus { | |
| enable-method = "mediatek,mt6580-smp"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| cpu@0 { | |
| reg = <0x00>; | |
| compatible = "arm,cortex-a7"; | |
| clock-frequency = <0x6553f100>; | |
| device_type = "cpu"; | |
| phandle = <0x22>; | |
| linux,phandle = <0x22>; | |
| }; | |
| cpu@1 { | |
| reg = <0x01>; | |
| compatible = "arm,cortex-a7"; | |
| clock-frequency = <0x6553f100>; | |
| device_type = "cpu"; | |
| phandle = <0x23>; | |
| linux,phandle = <0x23>; | |
| }; | |
| cpu@2 { | |
| reg = <0x02>; | |
| compatible = "arm,cortex-a7"; | |
| clock-frequency = <0x6553f100>; | |
| device_type = "cpu"; | |
| phandle = <0x24>; | |
| linux,phandle = <0x24>; | |
| }; | |
| cpu@3 { | |
| reg = <0x03>; | |
| compatible = "arm,cortex-a7"; | |
| clock-frequency = <0x6553f100>; | |
| device_type = "cpu"; | |
| phandle = <0x25>; | |
| linux,phandle = <0x25>; | |
| }; | |
| }; | |
| timer { | |
| interrupts = <0x01 0x0d 0x08 0x01 0x0e 0x08 0x01 0x0b 0x08 0x01 0x0a 0x08>; | |
| compatible = "arm,armv7-timer"; | |
| clock-frequency = <0xc65d40>; | |
| }; | |
| interrupt-controller@10210000 { | |
| reg = <0x00 0x10211000 0x00 0x1000 0x00 0x10212000 0x00 0x1000 0x00 0x10200100 0x00 0x1000>; | |
| interrupts = <0x01 0x09 0xf04>; | |
| compatible = "arm,cortex-a7-gic"; | |
| #interrupt-cells = <0x03>; | |
| #address-cells = <0x00>; | |
| phandle = <0x01>; | |
| interrupt-controller; | |
| linux,phandle = <0x01>; | |
| }; | |
| chosen { | |
| atag,shutdown_time = [30]; | |
| atag,videolfb-lcmname = "nt35590_AUO"; | |
| atag,videolfb-fb_base = <0x9e800000>; | |
| atag,boot = <0x3000000 0x2080041 0x00>; | |
| atag,masp = <0x16000000 0x66080041 0x22000000 0x22000000 0x00 0x00 0x192537d2 0x9431fd29 0x90c38395 0x9f172d6c 0x31413532 0x41333637 0x43423132 0x43343538 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; | |
| linux,initrd-end = <0x841340c7>; | |
| atag,videolfb-islcmfound = <0x01>; | |
| atag,fg_swocv_i = [30]; | |
| atag,fg_swocv_v = [30]; | |
| atag,videolfb-fps = <0x1770>; | |
| atag,boot_voltage = [30]; | |
| atag,videolfb-vramSize = <0x1800000>; | |
| atag,cmdline = <0x81000000 0x9004154 0x636f6e73 0x6f6c653d 0x74747930 0x20636f6e 0x736f6c65 0x3d747479 0x4d54302c 0x39323136 0x30306e31 0x20726f6f 0x743d2f64 0x65762f72 0x616d2076 0x6d616c6c 0x6f633d34 0x39364d20 0x616e6472 0x6f696462 0x6f6f742e 0x68617264 0x77617265 0x3d6d7436 0x35383020 0x6669726d 0x77617265 0x5f636c61 0x73732e70 0x6174683d 0x2f76656e 0x646f722f 0x6669726d 0x77617265 0x20616e64 0x726f6964 0x626f6f74 0x2e766572 0x69666965 0x64626f6f 0x74737461 0x74653d6f 0x72616e67 0x6520626f 0x6f746f70 0x743d3634 0x53332c33 0x3253312c 0x33325331 0x20627569 0x6c647661 0x7269616e 0x743d7573 0x65722061 0x6e64726f 0x6964626f 0x6f742e76 0x65726974 0x796d6f64 0x653d656e 0x666f7263 0x696e6720 0x6c706464 0x725f7573 0x65645f69 0x6e646578 0x3d302070 0x72696e74 0x6b2e6469 0x7361626c 0x655f7561 0x72743d31 0x20626f6f 0x7470726f 0x662e706c 0x5f743d31 0x33353320 0x626f6f74 0x70726f66 0x2e6c6b5f 0x743d3637 0x39372062 0x6f6f745f 0x72656173 0x6f6e3d34 0x20616e64 0x726f6964 0x626f6f74 0x2e736572 0x69616c6e 0x6f3d3330 0x38304448 0x32303032 0x30303630 0x36302061 0x6e64726f 0x6964626f 0x6f742e62 0x6f6f7472 0x6561736f 0x6e3d7764 0x745f6279 0x5f706173 0x735f7077 0x6b206770 0x743d3120 0x6d726475 0x6d705f64 0x64727376 0x3d796573 0x206d7264 0x756d705f 0x7273766d 0x656d3d30 0x78383165 0x30303030 0x302c3078 0x34303030 0x30302c30 0x78383231 0x30303030 0x302c3078 0x31613263 0x30302c30 0x78386530 0x30303030 0x302c3078 0x38303030 0x30000000>; | |
| atag,devinfo = <0x35000000 0x4080041 0x00 0x00 0x00 0x2100000 0x00 0xb4190000 0x00 0x24000000 0x3000000 0x3000000 0x00 0x40000000 0xa5af539b 0xd7342f8c 0x00 0x4000000 0x80650000 0x00 0x00 0x00 0x80650000 0x80650000 0x80650000 0x80650000 0x00 0x00 0x00 0x00 0x3000000 0x00 0x00 0x3000000 0xc1000000 0x611fb513 0x7d006300 0x00 0x6d820001 0x7f221f81 0x1e00 0x1000080 0xb60000c8 0x820200 0x00 0x00 0x181d700 0xd7000100 0x00 0xb3 0x80650000 0x80650000 0x32000000>; | |
| atag,two_sec_reboot = [30]; | |
| atag,videolfb = <0xc0be 0x00 0x1000000 0xa5180000 0xe000 0x696c6939 0x38383164 0x5f68645f 0x6473695f 0x76646f5f 0x647a785f 0x6c6f6e67 0x74656e67 0x00>; | |
| phandle = <0x1e>; | |
| atag,mem = <0x4000000 0x2004154 0xa03f 0x80>; | |
| atag,mdinfo = <0x3000000 0x6080041 0x00>; | |
| bootargs = "console=tty0 console=ttyMT0,921600n1 root=/dev/ram vmalloc=496M androidboot.hardware=mt6580 firmware_class.path=/vendor/firmware androidboot.verifiedbootstate=orange bootopt=64S3,32S1,32S1 buildvariant=user androidboot.veritymode=enforcing lpddr_used_index=0 printk.disable_uart=1 bootprof.pl_t=1353 bootprof.lk_t=6797 boot_reason=4 androidboot.serialno=3080DH2002006060 androidboot.bootreason=wdt_by_pass_pwk gpt=1 mrdump_ddrsv=yes mrdump_rsvmem=0x81e00000,0x400000,0x82100000,0x1a2c00,0x8e000000,0x80000"; | |
| linux,phandle = <0x1e>; | |
| linux,initrd-start = <0x84000000>; | |
| }; | |
| firmware { | |
| android { | |
| mode = "normal"; | |
| compatible = "android,firmware"; | |
| hardware = "mt6580"; | |
| serialno = "3080DH2002006060"; | |
| fstab { | |
| compatible = "android,fstab"; | |
| system { | |
| dev = "/dev/block/platform/mtk-msdc.0/11120000.msdc0/by-name/system"; | |
| type = "ext4"; | |
| mnt_flags = "ro"; | |
| fsmgr_flags = "wait"; | |
| compatible = "android,system"; | |
| }; | |
| vendor { | |
| dev = "/dev/block/platform/mtk-msdc.0/11120000.msdc0/by-name/vendor"; | |
| type = "ext4"; | |
| mnt_flags = "ro"; | |
| fsmgr_flags = "wait"; | |
| compatible = "android,vendor"; | |
| }; | |
| }; | |
| }; | |
| }; | |
| alias-gic { | |
| reg = <0x00 0x10211000 0x00 0x1000>; | |
| compatible = "mediatek,alias-gic"; | |
| }; | |
| rf_clock_buffer { | |
| mediatek,clkbuf-quantity = <0x04>; | |
| compatible = "mediatek,rf_clock_buffer"; | |
| #mediatek,clkbuf-config = <0x02 0x01 0x01 0x01>; | |
| mediatek,clkbuf-config = <0x02 0x02 0x01 0x01>; | |
| status = "okay"; | |
| phandle = <0x4f>; | |
| #mediatek,clkbuf-quantity = <0x04>; | |
| linux,phandle = <0x4f>; | |
| }; | |
| memory { | |
| reg = <0x00 0x80000000 0x00 0x40000000>; | |
| mblock_info = <0x1000000 0x00 0x80 0x00 0xc03e 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x99999999 0x2000000 0x2000000 0x00 0xa0bf 0x00 0x6000 0x00 0x00 0x7465655f 0x6765745f 0x6c6f6164 0x5f616464 0x72000000 0x6d746b5f 0x7764745f 0x696e6974 0x00 0x7267755f 0x6472616d 0x5f726573 0x65727665 0x64000000 0x7267755f 0x72656c65 0x6173655f 0x72675f64 0x72616d63 0x5f636f6e 0x665f6973 0x6f000000 0x7267755f 0x72656c65 0x6173655f 0x72675f64 0x72616d63 0x5f69736f 0x00 0x7267755f 0x72656c65 0x6173655f 0x00 0xc0be 0x00 0xe000 0x00 0x00 0x6672616d 0x65627566 0x66657200 0x46422062 0x61736520 0x3d203078 0x25782c20 0x46422073 0x697a6520 0x3d202564 0xa000000 0x6c6f676f 0x00 0x3c415353 0x4552543e 0x2025733a 0x6c696e65 0x2025640a 0x00 0x706c6174 0x666f726d 0x2f6d7436 0x3538302f 0x706c6174 0x666f726d 0x2e630000 0x5b4c4b5d 0x20626f6f 0x74206d6f 0x64652069 0x7320444f 0x574e4c4f 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; | |
| lca_reserved_mem = <0x00 0x00 0x00 0x00>; | |
| orig_dram_info = <0x1000000 0x00 0x80 0x00 0x40 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; | |
| device_type = "memory"; | |
| tee_reserved_mem = <0x00 0x00 0x00 0x00>; | |
| }; | |
| mt_pmic_regulator { | |
| compatible = "mediatek,mt_pmic"; | |
| buck_regulators { | |
| compatible = "mediatek,mt_pmic_buck_regulators"; | |
| buck_vpa { | |
| regulator-name = "vpa"; | |
| regulator-min-microvolt = <0x7a120>; | |
| regulator-max-microvolt = <0x37b1d0>; | |
| phandle = <0x4b>; | |
| regulator-enable-ramp-delay = <0xb4>; | |
| regulator-ramp-delay = <0xc350>; | |
| linux,phandle = <0x4b>; | |
| }; | |
| buck_vproc { | |
| regulator-name = "vproc"; | |
| regulator-always-on; | |
| regulator-min-microvolt = <0xaae60>; | |
| regulator-max-microvolt = <0x16caf6>; | |
| phandle = <0x4c>; | |
| regulator-boot-on; | |
| regulator-enable-ramp-delay = <0xb4>; | |
| regulator-ramp-delay = <0x186a>; | |
| linux,phandle = <0x4c>; | |
| }; | |
| }; | |
| ldo_regulators { | |
| compatible = "mediatek,mt_pmic_ldo_regulators"; | |
| ldo_vcn33_wifi { | |
| regulator-name = "vcn33_wifi"; | |
| regulator-min-microvolt = <0x325aa0>; | |
| regulator-max-microvolt = <0x36ee80>; | |
| phandle = <0x09>; | |
| regulator-enable-ramp-delay = <0x108>; | |
| linux,phandle = <0x09>; | |
| }; | |
| ldo_vcamaf { | |
| regulator-name = "vcamaf"; | |
| regulator-default-on = <0x00>; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-max-microvolt = <0x325aa0>; | |
| status = "okay"; | |
| phandle = <0x0c>; | |
| regulator-enable-ramp-delay = <0x108>; | |
| linux,phandle = <0x0c>; | |
| }; | |
| ldo_vcamio { | |
| regulator-name = "vcamio"; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-max-microvolt = <0x1b7740>; | |
| phandle = <0x0d>; | |
| regulator-enable-ramp-delay = <0xdc>; | |
| linux,phandle = <0x0d>; | |
| }; | |
| ldo_vmc { | |
| regulator-name = "vmc"; | |
| regulator-default-on = <0x00>; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-max-microvolt = <0x325aa0>; | |
| status = "okay"; | |
| phandle = <0x16>; | |
| regulator-enable-ramp-delay = <0x2c>; | |
| linux,phandle = <0x16>; | |
| }; | |
| ldo_vgp1 { | |
| regulator-name = "vgp1"; | |
| regulator-default-on = <0x00>; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-max-microvolt = <0x325aa0>; | |
| status = "okay"; | |
| phandle = <0x05>; | |
| regulator-enable-ramp-delay = <0x108>; | |
| linux,phandle = <0x05>; | |
| }; | |
| ldo_vgp2 { | |
| regulator-name = "vgp2"; | |
| regulator-default-on = <0x00>; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-max-microvolt = <0x2dc6c0>; | |
| status = "okay"; | |
| phandle = <0x14>; | |
| regulator-enable-ramp-delay = <0x108>; | |
| linux,phandle = <0x14>; | |
| }; | |
| ldo_vgp3 { | |
| regulator-name = "vgp3"; | |
| regulator-default-on = <0x00>; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-max-microvolt = <0x1b7740>; | |
| status = "okay"; | |
| phandle = <0x1d>; | |
| regulator-enable-ramp-delay = <0x108>; | |
| linux,phandle = <0x1d>; | |
| }; | |
| ldo_vibr { | |
| regulator-name = "vibr"; | |
| regulator-default-on = <0x00>; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-max-microvolt = <0x325aa0>; | |
| status = "okay"; | |
| phandle = <0x18>; | |
| regulator-enable-ramp-delay = <0x2c>; | |
| linux,phandle = <0x18>; | |
| }; | |
| ldo_vmch { | |
| regulator-name = "vmch"; | |
| regulator-default-on = <0x00>; | |
| regulator-min-microvolt = <0x2dc6c0>; | |
| regulator-max-microvolt = <0x325aa0>; | |
| status = "okay"; | |
| phandle = <0x17>; | |
| regulator-enable-ramp-delay = <0x2c>; | |
| linux,phandle = <0x17>; | |
| }; | |
| ldo_vrtc { | |
| regulator-name = "vrtc"; | |
| regulator-min-microvolt = <0x2ab980>; | |
| regulator-max-microvolt = <0x2ab980>; | |
| phandle = <0x19>; | |
| regulator-enable-ramp-delay = <0x2c>; | |
| linux,phandle = <0x19>; | |
| }; | |
| ldo_vusb { | |
| regulator-name = "vusb"; | |
| regulator-min-microvolt = <0x325aa0>; | |
| regulator-max-microvolt = <0x325aa0>; | |
| phandle = <0x13>; | |
| regulator-boot-on; | |
| regulator-enable-ramp-delay = <0x108>; | |
| linux,phandle = <0x13>; | |
| }; | |
| vcn33_ldo_reg { | |
| regulator-name = "vcn33"; | |
| regulator-default-on = <0x00>; | |
| status = "okay"; | |
| phandle = <0x4e>; | |
| linux,phandle = <0x4e>; | |
| }; | |
| ldo_vcn33_bt { | |
| regulator-name = "vcn33_bt"; | |
| regulator-min-microvolt = <0x325aa0>; | |
| regulator-max-microvolt = <0x36ee80>; | |
| phandle = <0x08>; | |
| regulator-enable-ramp-delay = <0x108>; | |
| linux,phandle = <0x08>; | |
| }; | |
| ldo_va { | |
| regulator-name = "va"; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-max-microvolt = <0x2625a0>; | |
| phandle = <0x0f>; | |
| regulator-enable-ramp-delay = <0x6e>; | |
| linux,phandle = <0x0f>; | |
| }; | |
| ldo_vm { | |
| regulator-name = "vm"; | |
| regulator-default-on = <0x00>; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-max-microvolt = <0x1b7740>; | |
| status = "okay"; | |
| phandle = <0x1a>; | |
| regulator-boot-on; | |
| regulator-enable-ramp-delay = <0x108>; | |
| linux,phandle = <0x1a>; | |
| }; | |
| ldo_vcn_1v8 { | |
| regulator-name = "vcn_1v8"; | |
| regulator-default-on = <0x00>; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-max-microvolt = <0x1b7740>; | |
| status = "okay"; | |
| phandle = <0x06>; | |
| regulator-enable-ramp-delay = <0x2c>; | |
| linux,phandle = <0x06>; | |
| }; | |
| vcanio_ldo_reg { | |
| regulator-name = "vcanio"; | |
| regulator-default-on = <0x00>; | |
| status = "okay"; | |
| phandle = <0x4d>; | |
| linux,phandle = <0x4d>; | |
| }; | |
| ldo_vcama { | |
| regulator-name = "vcama"; | |
| regulator-default-on = <0x00>; | |
| regulator-min-microvolt = <0x16e360>; | |
| regulator-max-microvolt = <0x2ab980>; | |
| status = "okay"; | |
| phandle = <0x0a>; | |
| regulator-enable-ramp-delay = <0x108>; | |
| linux,phandle = <0x0a>; | |
| }; | |
| ldo_vcamd { | |
| regulator-name = "vcamd"; | |
| regulator-default-on = <0x00>; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-max-microvolt = <0x1b7740>; | |
| status = "okay"; | |
| phandle = <0x0b>; | |
| regulator-enable-ramp-delay = <0x108>; | |
| linux,phandle = <0x0b>; | |
| }; | |
| ldo_vcn28 { | |
| regulator-name = "vcn28"; | |
| regulator-default-on = <0x00>; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-max-microvolt = <0x2ab980>; | |
| status = "okay"; | |
| phandle = <0x07>; | |
| regulator-enable-ramp-delay = <0x108>; | |
| linux,phandle = <0x07>; | |
| }; | |
| ldo_vio18 { | |
| regulator-name = "vio18"; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-max-microvolt = <0x1b7740>; | |
| phandle = <0x1c>; | |
| regulator-boot-on; | |
| regulator-enable-ramp-delay = <0x108>; | |
| linux,phandle = <0x1c>; | |
| }; | |
| ldo_vio28 { | |
| regulator-name = "vio28"; | |
| regulator-min-microvolt = <0x2ab980>; | |
| regulator-max-microvolt = <0x2ab980>; | |
| phandle = <0x10>; | |
| regulator-boot-on; | |
| regulator-enable-ramp-delay = <0x108>; | |
| linux,phandle = <0x10>; | |
| }; | |
| ldo_vrf18 { | |
| regulator-name = "vrf18"; | |
| regulator-default-on = <0x00>; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-max-microvolt = <0x1b7740>; | |
| status = "okay"; | |
| phandle = <0x1b>; | |
| regulator-enable-ramp-delay = <0xdc>; | |
| linux,phandle = <0x1b>; | |
| }; | |
| ldo_vsim1 { | |
| regulator-name = "vsim1"; | |
| regulator-default-on = <0x00>; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-max-microvolt = <0x2dc6c0>; | |
| status = "okay"; | |
| phandle = <0x11>; | |
| regulator-enable-ramp-delay = <0x108>; | |
| linux,phandle = <0x11>; | |
| }; | |
| ldo_vsim2 { | |
| regulator-name = "vsim2"; | |
| regulator-default-on = <0x00>; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-max-microvolt = <0x2dc6c0>; | |
| status = "okay"; | |
| phandle = <0x12>; | |
| regulator-enable-ramp-delay = <0x108>; | |
| linux,phandle = <0x12>; | |
| }; | |
| ldo_vtcxo { | |
| regulator-name = "vtcxo"; | |
| regulator-min-microvolt = <0x2191c0>; | |
| regulator-max-microvolt = <0x2191c0>; | |
| phandle = <0x0e>; | |
| regulator-enable-ramp-delay = <0x6e>; | |
| linux,phandle = <0x0e>; | |
| }; | |
| ldo_vemc_3v3 { | |
| regulator-name = "vemc_3v3"; | |
| regulator-default-on = <0x00>; | |
| regulator-min-microvolt = <0x2dc6c0>; | |
| regulator-max-microvolt = <0x325aa0>; | |
| status = "okay"; | |
| phandle = <0x15>; | |
| regulator-boot-on; | |
| regulator-enable-ramp-delay = <0x108>; | |
| linux,phandle = <0x15>; | |
| }; | |
| }; | |
| regulators_supply { | |
| vusb-supply = <0x13>; | |
| vtcxo-supply = <0x0e>; | |
| vcamio-supply = <0x0d>; | |
| vcn28-supply = <0x07>; | |
| compatible = "mediatek,mt_pmic_regulator_supply"; | |
| vsim1-supply = <0x11>; | |
| vgp1-supply = <0x05>; | |
| vemc_3v3-supply = <0x15>; | |
| vcamaf-supply = <0x0c>; | |
| vio18-supply = <0x1c>; | |
| vcamd-supply = <0x0b>; | |
| vcn33_wifi-supply = <0x09>; | |
| vmc-supply = <0x16>; | |
| vmch-supply = <0x17>; | |
| vgp3-supply = <0x1d>; | |
| va-supply = <0x0f>; | |
| vrtc-supply = <0x19>; | |
| vrf18-supply = <0x1b>; | |
| vm-supply = <0x1a>; | |
| vcn_1v8-supply = <0x06>; | |
| vsim2-supply = <0x12>; | |
| vgp2-supply = <0x14>; | |
| vio28-supply = <0x10>; | |
| vibr-supply = <0x18>; | |
| vcn33_bt-supply = <0x08>; | |
| }; | |
| }; | |
| reserved-memory { | |
| ranges; | |
| #address-cells = <0x02>; | |
| phandle = <0x26>; | |
| #size-cells = <0x02>; | |
| linux,phandle = <0x26>; | |
| minirdump-reserved-memory@83ff0000 { | |
| reg = <0x00 0x83ff0000 0x00 0x10000>; | |
| compatible = "mediatek, minirdump"; | |
| }; | |
| mblock-1-tee_get_load_addr { | |
| reg = <0x00 0xbfa00000 0x00 0x600000>; | |
| compatible = "mediatek,tee_get_load_addr"; | |
| no-map; | |
| }; | |
| mblock-2-framebuffer { | |
| reg = <0x00 0xbec00000 0x00 0xe00000>; | |
| compatible = "mediatek,framebuffer"; | |
| no-map; | |
| }; | |
| consys-reserve-memory { | |
| size = <0x00 0x200000>; | |
| compatible = "mediatek,consys-reserve-memory"; | |
| alignment = <0x00 0x200000>; | |
| no-map; | |
| }; | |
| ram_console-reserved-memory@83f00000 { | |
| reg = <0x00 0x83f00000 0x00 0x10000>; | |
| compatible = "mediatek,ram_console"; | |
| }; | |
| pstore-reserved-memory@83f10000 { | |
| reg = <0x00 0x83f10000 0x00 0xe0000>; | |
| compatible = "mediatek,pstore"; | |
| }; | |
| reserve-memory-ccci_md1 { | |
| size = <0x00 0x1800000>; | |
| compatible = "mediatek,reserve-memory-ccci_md1"; | |
| alloc-ranges = <0x00 0x80000000 0x00 0x80000000>; | |
| alignment = <0x00 0x2000000>; | |
| no-map; | |
| }; | |
| }; | |
| tkcore { | |
| interrupts = <0x00 0xdb 0x01>; | |
| compatible = "trustkernel,tkcore"; | |
| }; | |
| __symbols__ { | |
| fp = "/fp"; | |
| als = "/bus/als"; | |
| bus = "/bus"; | |
| gic = "/interrupt-controller@10210000"; | |
| lcm = "/bus/lcm"; | |
| nfc = "/bus/nfc"; | |
| odm = "/odm"; | |
| pio = "/bus/pinctrl@0x10005000"; | |
| mt_pmic_vcn_1v8_ldo_reg = "/mt_pmic_regulator/ldo_regulators/ldo_vcn_1v8"; | |
| mt_pmic_vio18_ldo_reg = "/mt_pmic_regulator/ldo_regulators/ldo_vio18"; | |
| btif = "/bus/btif@1100e000"; | |
| cpu0 = "/cpus/cpu@0"; | |
| cpu1 = "/cpus/cpu@1"; | |
| cpu2 = "/cpus/cpu@2"; | |
| cpu3 = "/cpus/cpu@3"; | |
| i2c0 = "/bus/i2c@11009000"; | |
| i2c1 = "/bus/i2c@1100a000"; | |
| i2c2 = "/bus/i2c@1100b000"; | |
| gpio = "/bus/gpio@0x10005000"; | |
| gyro = "/bus/gyroscope@0"; | |
| mmc0 = "/mtk-msdc.0/msdc0@11120000"; | |
| mmc1 = "/mtk-msdc.0/msdc1@11130000"; | |
| usb0 = "/bus/USB0@0x11100000"; | |
| mt_pmic_vm_ldo_reg = "/mt_pmic_regulator/ldo_regulators/ldo_vm"; | |
| rf_clock_buffer_ctrl = "/rf_clock_buffer"; | |
| bat_meter = "/bus/bat_meter"; | |
| mt_pmic_vproc_buck_reg = "/mt_pmic_regulator/buck_regulators/buck_vproc"; | |
| alsps = "/bus/als_ps@0"; | |
| eintc = "/bus/eintc@1000b000"; | |
| gse_1 = "/bus/gse_1"; | |
| mt_pmic_vgp1_ldo_reg = "/mt_pmic_regulator/ldo_regulators/ldo_vgp1"; | |
| mtkfb = "/bus/mtkfb@0"; | |
| touch = "/bus/touch@0"; | |
| mt_pmic_vusb_ldo_reg = "/mt_pmic_regulator/ldo_regulators/ldo_vusb"; | |
| mt_pmic_vmc_ldo_reg = "/mt_pmic_regulator/ldo_regulators/ldo_vmc"; | |
| ap_ccif0 = "/bus/ap_ccif0@1000C000"; | |
| kd_camera_hw1 = "/bus/kd_camera_hw1@15008000"; | |
| kd_camera_hw2 = "/bus/kd_camera_hw2@15008000"; | |
| mt_pmic_va_ldo_reg = "/mt_pmic_regulator/ldo_regulators/ldo_va"; | |
| mt_pmic_vcn33_ldo_reg = "/mt_pmic_regulator/ldo_regulators/vcn33_ldo_reg"; | |
| mt_pmic_vio28_ldo_reg = "/mt_pmic_regulator/ldo_regulators/ldo_vio28"; | |
| cpu_dbgapb = "/bus/cpu_dbgapb@10170000"; | |
| mt_pmic_vgp3_ldo_reg = "/mt_pmic_regulator/ldo_regulators/ldo_vgp3"; | |
| mt_pmic_vpa_buck_reg = "/mt_pmic_regulator/buck_regulators/buck_vpa"; | |
| mt_pmic_vsim1_ldo_reg = "/mt_pmic_regulator/ldo_regulators/ldo_vsim1"; | |
| mt_pmic_vibr_ldo_reg = "/mt_pmic_regulator/ldo_regulators/ldo_vibr"; | |
| mt_pmic_vtcxo_ldo_reg = "/mt_pmic_regulator/ldo_regulators/ldo_vtcxo"; | |
| mt_pmic_vcanio_ldo_reg = "/mt_pmic_regulator/ldo_regulators/vcanio_ldo_reg"; | |
| accdet = "/bus/accdet"; | |
| gpio_usage_mapping = "/bus/gpio"; | |
| ap_dma = "/bus/dma@0x11000000"; | |
| auxadc = "/bus/adc_hw@11003000"; | |
| chosen = "/chosen"; | |
| mt_pmic_vcamd_ldo_reg = "/mt_pmic_regulator/ldo_regulators/ldo_vcamd"; | |
| consys = "/bus/consys@18070000"; | |
| dsi_te = "/bus/dsi_te"; | |
| mt_pmic_vemc_3v3_ldo_reg = "/mt_pmic_regulator/ldo_regulators/ldo_vemc_3v3"; | |
| mt_pmic_vcamaf_ldo_reg = "/mt_pmic_regulator/ldo_regulators/ldo_vcamaf"; | |
| keypad = "/bus/keypad@10002000"; | |
| mcucfg = "/bus/mcucfg@10200000"; | |
| mt_pmic_vcamio_ldo_reg = "/mt_pmic_regulator/ldo_regulators/ldo_vcamio"; | |
| sys_cirq = "/bus/sys_cirq@10202000"; | |
| usbphy0 = "/bus/usbphy@0"; | |
| mt_pmic_vgp2_ldo_reg = "/mt_pmic_regulator/ldo_regulators/ldo_vgp2"; | |
| mt_pmic_vcama_ldo_reg = "/mt_pmic_regulator/ldo_regulators/ldo_vcama"; | |
| mt_pmic_vcn33_wifi_ldo_reg = "/mt_pmic_regulator/ldo_regulators/ldo_vcn33_wifi"; | |
| usbiddig = "/bus/USB0@0x11100000/usbiddig"; | |
| syscfg_pctl_a = "/bus/syscfg_pctl_a@0x10005000"; | |
| mt_pmic_vmch_ldo_reg = "/mt_pmic_regulator/ldo_regulators/ldo_vmch"; | |
| mt_pmic_vrtc_ldo_reg = "/mt_pmic_regulator/ldo_regulators/ldo_vrtc"; | |
| audgpio = "/bus/mt_soc_dl1_pcm@11140000"; | |
| mt_pmic_vcn33_bt_ldo_reg = "/mt_pmic_regulator/ldo_regulators/ldo_vcn33_bt"; | |
| msdc1_ins = "/mtk-msdc.0/default"; | |
| mt_pmic_vrf18_ldo_reg = "/mt_pmic_regulator/ldo_regulators/ldo_vrf18"; | |
| mt_pmic_vcn28_ldo_reg = "/mt_pmic_regulator/ldo_regulators/ldo_vcn28"; | |
| bat_comm = "/bus/bat_comm"; | |
| mt_pmic_vsim2_ldo_reg = "/mt_pmic_regulator/ldo_regulators/ldo_vsim2"; | |
| reserved_memory = "/reserved-memory"; | |
| btif_rx = "/bus/btif_rx@11000400"; | |
| btif_tx = "/bus/btif_tx@11000380"; | |
| }; | |
| trusty { | |
| compatible = "android,trusty-smc-v1"; | |
| ranges; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| irq { | |
| compatible = "android,trusty-irq-v1"; | |
| ppi-interrupt-parent = <0x01>; | |
| }; | |
| log { | |
| compatible = "android,trusty-log-v1"; | |
| }; | |
| mtee { | |
| compatible = "mediatek,trusty-mtee-v1"; | |
| }; | |
| virtio { | |
| compatible = "android,trusty-virtio-v1"; | |
| }; | |
| }; | |
| mtk-msdc.0 { | |
| compatible = "simple-bus"; | |
| ranges = <0x00 0x00 0x00 0xffffffff>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| default { | |
| interrupts = <0x53 0x08>; | |
| compatible = "mediatek,msdc1_ins-eint"; | |
| debounce = <0x53 0x00>; | |
| status = "okay"; | |
| phandle = <0x21>; | |
| linux,phandle = <0x21>; | |
| interrupt-parent = <0x03>; | |
| }; | |
| msdc0@11120000 { | |
| reg = <0x11120000 0x10000 0x10001e84 0x02>; | |
| interrupts = <0x00 0x26 0x08>; | |
| mmc-hs200-1_8v; | |
| msdc-sys-suspend; | |
| compatible = "mediatek,mt6580-mmc"; | |
| register_setting = <0x54>; | |
| bus-width = <0x08>; | |
| host_function = [00]; | |
| non-removable; | |
| cap-mmc-highspeed; | |
| pinctl = <0x53>; | |
| status = "okay"; | |
| max-frequency = <0xc65d400>; | |
| phandle = <0x1f>; | |
| bootable; | |
| linux,phandle = <0x1f>; | |
| clk_src = [07]; | |
| }; | |
| msdc1@11130000 { | |
| reg = <0x11130000 0x10000 0x10001e84 0x02>; | |
| cd-gpios = <0x02 0x53 0x00>; | |
| interrupts = <0x00 0x27 0x08>; | |
| pinctrl-0 = <0x55>; | |
| pinctrl-1 = <0x56>; | |
| msdc-sys-suspend; | |
| pinctl_ddr50 = <0x5a>; | |
| compatible = "mediatek,mt6580-mmc"; | |
| pinctl_sdr50 = <0x59>; | |
| register_setting = <0x5b>; | |
| pinctl_sdr104 = <0x58>; | |
| bus-width = <0x04>; | |
| host_function = [01]; | |
| cap-sd-highspeed; | |
| pinctl = <0x57>; | |
| status = "okay"; | |
| cd_level = [00]; | |
| sd-uhs-sdr104; | |
| max-frequency = <0xc65d400>; | |
| sd-uhs-sdr12; | |
| sd-uhs-sdr25; | |
| sd-uhs-sdr50; | |
| phandle = <0x20>; | |
| pinctrl-names = "default\0insert_cfg"; | |
| linux,phandle = <0x20>; | |
| clk_src = [02]; | |
| }; | |
| }; | |
| MOBICORE { | |
| interrupts = <0x00 0x97 0x01>; | |
| compatible = "trustonic,mobicore"; | |
| }; | |
| }; |
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