Created
July 25, 2022 08:06
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Motorola Moto G 2013 "falcon" downstream DTS
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| /dts-v1/; | |
| / { | |
| interrupt-parent = <0x01>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| qcom,msm-id = <0x91 0x42 0x283c0>; | |
| channel-id-map = "acg\0amxbr\0amxpr\0amxmx\0amxcl\0amxar\0amxla\0amxpe\0amxco\0tefbr\0tefmx\0tefar\0tefcl\0tefpe\0tefco\0perar\0entcl\0iusmx\0niibr\0niicl\0niimx\0niipe\0oibr\0timbr\0tigco\0retbr\0retar\0retla\0retcl\0tefla\0retla1st\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0reteu\0retgb\0retfr\0retes\0retie\0retde\0vfgb\0vfde\0vffr\0o2gb\0o2de\0orafr\0bouyfr\0eegb\0tescogb\0yoigo\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0retca\0bwaca\0tkpca\0vzw\0att\0tmo\0sprint\0repw\0aio\0???\0???\0usc\0tracfone\0retus\0???\0rcica\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined\0undefined"; | |
| compatible = "qcom,msm8226-falcon\0qcom,msm8226-moto\0qcom,msm8226"; | |
| model = "Motorola QC-MSM8226 Falcon"; | |
| soc { | |
| ranges; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| qcom,smp2pgpio-rdbg-2-in { | |
| gpio-controller; | |
| #interrupt-cells = <0x02>; | |
| qcom,is-inbound; | |
| #gpio-cells = <0x02>; | |
| qcom,entry-name = "rdbg"; | |
| compatible = "qcom,smp2pgpio"; | |
| interrupt-controller; | |
| qcom,remote-pid = <0x02>; | |
| phandle = <0x34>; | |
| linux,phandle = <0x34>; | |
| }; | |
| jtagmm@fc33d000 { | |
| reg-names = "etm-base\0debug-base"; | |
| compatible = "qcom,jtag-mm"; | |
| reg = <0xfc33d000 0x1000 0xfc332000 0x1000>; | |
| }; | |
| usb@f9a55000 { | |
| hsusb_vdd_dig-supply = <0x1c>; | |
| qcom,dp-manual-pullup; | |
| id_gnd_active_high = <0x01>; | |
| qcom,hsusb-otg-disable-reset; | |
| qcom,msm-bus,vectors-KBps = <0x57 0x200 0x00 0x00 0x57 0x200 0xea60 0xea600 0x57 0x200 0x1770 0x1770>; | |
| qcom,msm-bus,num-cases = <0x03>; | |
| vbus_otg-supply = <0x3d>; | |
| id_flt_active_high = <0x01>; | |
| interrupts = <0x00 0x86 0x00 0x00 0x8c 0x00>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| HSUSB_1p8-supply = <0x3a>; | |
| qcom,hsusb-otg-mode = <0x03>; | |
| qcom,vdd-voltage-level = <0x01 0x05 0x07>; | |
| qcom,usbin-vadc = <0x3c>; | |
| qcom,hsusb-otg-phy-type = <0x02>; | |
| otg,id_gnd_gpio = <0x08 0x70 0x00>; | |
| compatible = "qcom,hsusb-otg"; | |
| otg,id_flt_gpio = <0x08 0x6f 0x00>; | |
| qcom,hsusb-otg-otg-control = <0x02>; | |
| qcom,hsusb-otg-phy-init-seq = <0x44 0x80 0x28 0x81 0x34 0x82 0x13 0x83 0xffffffff>; | |
| reg = <0xf9a55000 0x400>; | |
| HSUSB_3p3-supply = <0x3b>; | |
| qcom,msm-bus,name = "usb"; | |
| interrupt-names = "core_irq\0async_irq"; | |
| }; | |
| qcom,csiphy@fda0b000 { | |
| reg-names = "csiphy\0csiphy_clk_mux"; | |
| interrupts = <0x00 0x4f 0x00>; | |
| cell-index = <0x01>; | |
| compatible = "qcom,csiphy"; | |
| reg = <0xfda0b000 0x200 0xfda00038 0x04>; | |
| interrupt-names = "csiphy"; | |
| }; | |
| qcom,ocmem@fdd00000 { | |
| qcom,ocmem-num-macros = <0x02>; | |
| qcom,resource-type = <0x706d636f>; | |
| reg-names = "ocmem_ctrl_physical\0dm_ctrl_physical\0br_ctrl_physical\0ocmem_physical"; | |
| interrupts = <0x00 0x4c 0x00 0x00 0x4d 0x00>; | |
| ranges = <0x00 0xfec00000 0x20000>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| compatible = "qcom,msm-ocmem"; | |
| qcom,ocmem-num-regions = <0x01>; | |
| reg = <0xfdd00000 0x2000 0xfdd02000 0x2000 0xfe039000 0x400 0xfec00000 0x20000>; | |
| interrupt-names = "ocmem_irq\0dm_irq"; | |
| partition@0 { | |
| qcom,ocmem-part-name = "graphics"; | |
| qcom,ocmem-part-min = <0x20000>; | |
| reg = <0x00 0x20000>; | |
| }; | |
| }; | |
| qcom,sdcc@f9864000 { | |
| qcom,bus-width = <0x04>; | |
| qcom,gpio-names = "CLK\0CMD\0DAT0\0DAT1\0DAT2\0DAT3"; | |
| qcom,msm-bus,vectors-KBps = <0x4f 0x200 0x00 0x00 0x4f 0x200 0x640 0xc80 0x4f 0x200 0x13880 0x27100 0x4f 0x200 0x186a0 0x30d40 0x4f 0x200 0x30d40 0x61a80 0x4f 0x200 0x61a80 0xc3500 0x4f 0x200 0x61a80 0xc3500 0x4f 0x200 0x1f4000 0x3e8000>; | |
| gpios = <0x08 0x2c 0x00 0x08 0x2b 0x00 0x08 0x2a 0x00 0x08 0x29 0x00 0x08 0x28 0x00 0x08 0x27 0x00>; | |
| qcom,msm-bus,num-cases = <0x08>; | |
| #interrupt-cells = <0x01>; | |
| qcom,clk-rates = <0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100>; | |
| reg-names = "core_mem\0dml_mem\0bam_mem"; | |
| interrupts = <0x00 0x01 0x02>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,bus-bw-vectors-bps = <0x00 0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100 0xbebc200 0xffffffff>; | |
| interrupt-map = <0x00 0x01 0x00 0x7f 0x00 0x01 0x01 0x00 0xdf 0x00 0x02 0x08 0x29 0x08>; | |
| interrupt-parent = <0x4a>; | |
| status = "disabled"; | |
| #address-cells = <0x00>; | |
| cell-index = <0x03>; | |
| interrupt-map-mask = <0xffffffff>; | |
| compatible = "qcom,msm-sdcc"; | |
| phandle = <0x4a>; | |
| reg = <0xf9864000 0x800 0xf9864800 0x100 0xf9844000 0x7000>; | |
| qcom,msm-bus,name = "sdcc3"; | |
| interrupt-names = "core_irq\0bam_irq\0sdiowakeup_irq"; | |
| linux,phandle = <0x4a>; | |
| }; | |
| qcom,rpm-stats@fc19dba0 { | |
| reg-names = "phys_addr_base"; | |
| qcom,sleep-stats-version = <0x02>; | |
| compatible = "qcom,rpm-stats"; | |
| reg = <0xfc19dba0 0x1000>; | |
| }; | |
| qcom,gdsc@fd8c1040 { | |
| regulator-name = "gdsc_venus_core0"; | |
| status = "disabled"; | |
| compatible = "qcom,gdsc"; | |
| reg = <0xfd8c1040 0x04>; | |
| }; | |
| cti@fc30b000 { | |
| reg-names = "cti-base"; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x16>; | |
| compatible = "arm,coresight-cti"; | |
| reg = <0xfc30b000 0x1000>; | |
| coresight-name = "coresight-cti3"; | |
| }; | |
| qcom,rpm-rbcpr-stats@fc000000 { | |
| compatible = "qcom,rpmrbcpr-stats"; | |
| qcom,start-offset = <0x190010>; | |
| reg = <0xfc000000 0x1a0000>; | |
| }; | |
| qcom,smp2pgpio-smp2p-1-in { | |
| gpio-controller; | |
| #interrupt-cells = <0x02>; | |
| qcom,is-inbound; | |
| #gpio-cells = <0x02>; | |
| qcom,entry-name = "smp2p"; | |
| compatible = "qcom,smp2pgpio"; | |
| interrupt-controller; | |
| qcom,remote-pid = <0x01>; | |
| phandle = <0x15>; | |
| linux,phandle = <0x15>; | |
| }; | |
| timer { | |
| interrupts = <0x01 0x02 0x00 0x01 0x03 0x00>; | |
| clock-frequency = <0x124f800>; | |
| compatible = "arm,armv7-timer"; | |
| }; | |
| qcom,usbbam@f9a44000 { | |
| qcom,ignore-core-reset-ack; | |
| reg-names = "hsusb"; | |
| interrupts = <0x00 0x87 0x00>; | |
| qcom,disable-clk-gating; | |
| compatible = "qcom,usb-bam-msm"; | |
| qcom,usb-bam-fifo-baseaddr = <0xfe803000>; | |
| qcom,usb-bam-num-pipes = <0x10>; | |
| reg = <0xf9a44000 0x11000>; | |
| interrupt-names = "hsusb"; | |
| qcom,pipe0 { | |
| qcom,dst-bam-pipe-index = <0x02>; | |
| qcom,src-bam-physical-address = <0xfc37c000>; | |
| qcom,src-bam-pipe-index = <0x00>; | |
| qcom,peer-bam = <0x01>; | |
| qcom,bam-type = <0x01>; | |
| qcom,dir = <0x01>; | |
| qcom,descriptor-fifo-offset = <0x600>; | |
| qcom,dst-bam-physical-address = <0xf9a44000>; | |
| qcom,data-fifo-size = <0x600>; | |
| qcom,pipe-num = <0x00>; | |
| qcom,descriptor-fifo-size = <0x200>; | |
| label = "hsusb-qdss-in-0"; | |
| qcom,usb-bam-mem-type = <0x03>; | |
| qcom,data-fifo-offset = <0x00>; | |
| }; | |
| }; | |
| serial@f991f000 { | |
| qcom,msm-bus,vectors-KBps = <0x56 0x200 0x00 0x00 0x56 0x200 0x1f4 0x320>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| interrupts = <0x00 0x6d 0x00>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| status = "ok"; | |
| compatible = "qcom,msm-lsuart-v14"; | |
| reg = <0xf991f000 0x1000>; | |
| qcom,msm-bus,name = "blsp1_uart2"; | |
| }; | |
| gpio@fd510000 { | |
| gpio-controller; | |
| #interrupt-cells = <0x02>; | |
| #gpio-cells = <0x02>; | |
| interrupts = <0x00 0xd0 0x00>; | |
| qcom,direct-connect-irqs = <0x08>; | |
| compatible = "qcom,msm-gpio"; | |
| interrupt-controller; | |
| ngpio = <0x75>; | |
| phandle = <0x08>; | |
| reg = <0xfd510000 0x4000>; | |
| linux,phandle = <0x08>; | |
| }; | |
| qcom,iommu@fe054000 { | |
| qcom,iommu-pmu-event-classes = <0x00 0x01 0x08 0x09 0x0a 0x10 0x11 0x12 0x80 0x81 0x82 0x83 0x90 0x91 0x92 0xb0 0xb1>; | |
| qcom,msm-bus,vectors-KBps = <0x0b 0x200 0x00 0x00 0x0b 0x200 0x00 0x3e8>; | |
| qcom,iommu-pmu-ngroups = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| qcom,iommu-bfb-data = <0x03 0x04 0x04 0x00 0x00 0x00 0x10 0x00 0x00 0x15e 0x19e 0x00 0x00>; | |
| reg-names = "iommu_base"; | |
| interrupts = <0x00 0xca 0x00>; | |
| qcom,iommu-lpae-bfb-regs = <0x204c 0x2514 0x2540 0x256c 0x20ac 0x215c 0x220c 0x22bc 0x2314 0x2394 0x2414 0x2494 0x2008>; | |
| qcom,iommu-lpae-bfb-data = <0x03 0x00 0x04 0x04 0x00 0x20 0x00 0x10 0x00 0x00 0x15e 0x19e 0x00>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| ranges; | |
| status = "disabled"; | |
| #address-cells = <0x01>; | |
| qcom,iommu-bfb-regs = <0x204c 0x2514 0x2540 0x256c 0x20ac 0x215c 0x220c 0x22bc 0x2314 0x2394 0x2414 0x2494 0x2008>; | |
| #size-cells = <0x01>; | |
| label = "lpass_qdsp_iommu"; | |
| compatible = "qcom,msm-smmu-v1"; | |
| qcom,iommu-pmu-ncounters = <0x08>; | |
| reg = <0xfe054000 0x10000>; | |
| qcom,msm-bus,name = "lpass_qdsp_ebi"; | |
| qcom,iommu-ctx@fe05d000 { | |
| interrupts = <0x00 0x109 0x00>; | |
| qcom,iommu-ctx-sids = <0x01>; | |
| label = "lpass_qdsp_cb_1"; | |
| compatible = "qcom,msm-smmu-v1-ctx"; | |
| reg = <0xfe05d000 0x1000>; | |
| }; | |
| qcom,iommu-ctx@fe05c000 { | |
| interrupts = <0x00 0x109 0x00>; | |
| qcom,iommu-ctx-sids = <0x00>; | |
| label = "lpass_qdsp_cb_0"; | |
| compatible = "qcom,msm-smmu-v1-ctx"; | |
| reg = <0xfe05c000 0x1000>; | |
| }; | |
| qcom,iommu-ctx@fe05e000 { | |
| interrupts = <0x00 0x109 0x00>; | |
| qcom,iommu-ctx-sids = <0x02>; | |
| label = "lpass_qdsp_cb_2"; | |
| compatible = "qcom,msm-smmu-v1-ctx"; | |
| reg = <0xfe05e000 0x1000>; | |
| }; | |
| qcom,iommu-ctx@fe05f000 { | |
| interrupts = <0x00 0x109 0x00>; | |
| qcom,iommu-ctx-sids = <0x03>; | |
| label = "lpass_qdsp_cb_3"; | |
| compatible = "qcom,msm-smmu-v1-ctx"; | |
| reg = <0xfe05f000 0x1000>; | |
| }; | |
| }; | |
| qcom,vfe@fda10000 { | |
| vdd-supply = <0x06>; | |
| reg-names = "vfe\0vfe_vbif\0tcsr"; | |
| interrupts = <0x00 0x39 0x00>; | |
| cell-index = <0x00>; | |
| compatible = "qcom,vfe40"; | |
| reg = <0xfda10000 0x1000 0xfda40000 0x200 0xfd4a8000 0x04>; | |
| interrupt-names = "vfe"; | |
| }; | |
| ram_console { | |
| android,ram-buffer-start = <0x3eae0000>; | |
| status = "ok"; | |
| android,ram-buffer-size = <0x20000>; | |
| compatible = "android,ram-console"; | |
| }; | |
| spi@f9923000 { | |
| qcom,gpio-miso = <0x08 0x01 0x00>; | |
| qcom,gpio-clk = <0x08 0x03 0x00>; | |
| qcom,use-bam; | |
| qcom,infinite-mode = <0x00>; | |
| qcom,bam-consumer-pipe-index = <0x0c>; | |
| qcom,ver-reg-exists; | |
| reg-names = "spi_physical\0spi_bam_physical"; | |
| interrupts = <0x00 0x5f 0x00 0x00 0xee 0x00>; | |
| qcom,gpio-cs0 = <0x08 0x16 0x00>; | |
| qcom,master-id = <0x56>; | |
| status = "disabled"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| spi-max-frequency = <0x124f800>; | |
| compatible = "qcom,spi-qup-v2"; | |
| qcom,gpio-mosi = <0x08 0x00 0x00>; | |
| reg = <0xf9923000 0x1000 0xf9904000 0xf000>; | |
| interrupt-names = "spi_irq\0spi_bam_irq"; | |
| qcom,bam-producer-pipe-index = <0x0d>; | |
| ethernet-switch@3 { | |
| vdd-phy-supply = <0x50>; | |
| rst-gpio = <0x08 0x72 0x00>; | |
| interrupts = <0x00 0x73 0x00>; | |
| vdd-io-supply = <0x50>; | |
| interrupt-parent = <0x08>; | |
| spi-max-frequency = "\0I>"; | |
| compatible = "micrel,ks8851"; | |
| reg = <0x03>; | |
| }; | |
| }; | |
| sdhci@f9824900 { | |
| qcom,bus-width = <0x08>; | |
| qcom,msm-bus,vectors-KBps = <0x4e 0x200 0x00 0x00 0x4e 0x200 0x640 0xc80 0x4e 0x200 0x13880 0x27100 0x4e 0x200 0x186a0 0x30d40 0x4e 0x200 0x30d40 0x61a80 0x4e 0x200 0x61a80 0xc3500 0x4e 0x200 0x61a80 0xc3500 0x4e 0x200 0x1f4000 0x3e8000>; | |
| qcom,msm-bus,num-cases = <0x08>; | |
| reg-names = "hc_mem\0core_mem"; | |
| interrupts = <0x00 0x7b 0x00 0x00 0x8a 0x00>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,bus-bw-vectors-bps = <0x00 0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100 0xbebc200 0xffffffff>; | |
| status = "disabled"; | |
| compatible = "qcom,sdhci-msm"; | |
| reg = <0xf9824900 0x11c 0xf9824000 0x800>; | |
| qcom,msm-bus,name = "sdhc1"; | |
| interrupt-names = "hc_irq\0pwr_irq"; | |
| }; | |
| qcom,iommu@fdfb6000 { | |
| qcom,iommu-pmu-event-classes = <0x00 0x01 0x08 0x09 0x0a 0x10 0x11 0x12 0x80 0x81 0x82 0x83 0x90 0x91 0x92 0xb0 0xb1>; | |
| qcom,msm-bus,vectors-KBps = <0x30 0x200 0x00 0x00 0x30 0x200 0x00 0x3e8>; | |
| qcom,iommu-pmu-ngroups = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| qcom,iommu-bfb-data = <0xff 0x04 0x08 0x00 0x00 0x08 0x28 0x00 0x1000 0x1000 0x3008 0x00 0x00 0x00>; | |
| qcom,needs-alt-core-clk; | |
| reg-names = "iommu_base"; | |
| interrupts = <0x00 0x13b 0x00>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| ranges; | |
| status = "disabled"; | |
| #address-cells = <0x01>; | |
| qcom,iommu-bfb-regs = <0x204c 0x2514 0x2540 0x256c 0x2314 0x2394 0x2414 0x2494 0x20ac 0x215c 0x220c 0x22bc 0x2008 0x200c>; | |
| #size-cells = <0x01>; | |
| label = "vcap_iommu"; | |
| compatible = "qcom,msm-smmu-v1"; | |
| qcom,iommu-pmu-ncounters = <0x08>; | |
| reg = <0xfdfb6000 0x10000>; | |
| qcom,msm-bus,name = "vcap_ebi"; | |
| qcom,iommu-ctx@fdfbe000 { | |
| interrupts = <0x00 0x139 0x00>; | |
| qcom,iommu-ctx-sids = <0x00>; | |
| label = "vcap_cb0"; | |
| compatible = "qcom,msm-smmu-v1-ctx"; | |
| reg = <0xfdfbe000 0x1000>; | |
| }; | |
| qcom,iommu-ctx@fdfc0000 { | |
| interrupts = <0x00 0x139 0x00>; | |
| qcom,iommu-ctx-sids; | |
| label = "vcap_cb2"; | |
| compatible = "qcom,msm-smmu-v1-ctx"; | |
| reg = <0xfdfc0000 0x1000>; | |
| }; | |
| qcom,iommu-ctx@fdfbf000 { | |
| interrupts = <0x00 0x139 0x00>; | |
| qcom,iommu-ctx-sids = <0x01>; | |
| label = "vcap_cb1"; | |
| compatible = "qcom,msm-smmu-v1-ctx"; | |
| reg = <0xfdfbf000 0x1000>; | |
| }; | |
| }; | |
| cti@fc341000 { | |
| reg-names = "cti-base"; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x1d>; | |
| compatible = "arm,coresight-cti"; | |
| reg = <0xfc341000 0x1000>; | |
| coresight-name = "coresight-cti-cpu0"; | |
| }; | |
| qcom,smp2pgpio_test_smp2p_1_out { | |
| gpios = <0x16 0x00 0x00>; | |
| compatible = "qcom,smp2pgpio_test_smp2p_1_out"; | |
| }; | |
| msm-bimc@0xfc380000 { | |
| qcom,hw-sel = "BIMC"; | |
| qcom,qos-freq = <0x12c0>; | |
| qcom,fabclk-dual = "mem_clk"; | |
| qcom,rpm-en; | |
| cell-id = <0x00>; | |
| qcom,ntieredslaves = <0x00>; | |
| qcom,fabclk-active = "mem_a_clk"; | |
| label = "msm_bimc"; | |
| compatible = "msm-bus-fabric"; | |
| reg = <0xfc380000 0x6a000>; | |
| slv-ebi-ch0 { | |
| qcom,buswidth = <0x08>; | |
| qcom,mode = "Bypass"; | |
| qcom,slavep = <0x00>; | |
| qcom,slv-hw-id = <0x00>; | |
| cell-id = <0x200>; | |
| label = "slv-ebi-ch0"; | |
| qcom,tier = <0x02>; | |
| }; | |
| mas-mss-proc { | |
| qcom,hw-sel = "RPM"; | |
| qcom,masterp = <0x01>; | |
| qcom,mas-hw-id = <0x01>; | |
| cell-id = <0x41>; | |
| label = "mas-mss-proc"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-ampss-l2 { | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x01>; | |
| qcom,slv-hw-id = <0x01>; | |
| cell-id = <0x202>; | |
| label = "slv-ampss-l2"; | |
| qcom,tier = <0x02>; | |
| }; | |
| fab-mmss-noc { | |
| qcom,hw-sel = "BIMC"; | |
| qcom,masterp = <0x02>; | |
| qcom,gateway; | |
| qcom,qport = <0x02>; | |
| qcom,buswidth = <0x08>; | |
| qcom,mode = "Bypass"; | |
| qcom,ws = <0x2710>; | |
| qcom,mas-hw-id = <0x02>; | |
| cell-id = <0x800>; | |
| label = "fab_mmss_noc"; | |
| }; | |
| mas-ampss-m0 { | |
| qcom,prio-rd = <0x00>; | |
| qcom,hw-sel = "BIMC"; | |
| qcom,masterp = <0x00>; | |
| qcom,qport = <0x00>; | |
| qcom,mode = "Fixed"; | |
| qcom,ws = <0x2710>; | |
| qcom,mas-hw-id = <0x00>; | |
| cell-id = <0x01>; | |
| qcom,prio-wr = <0x00>; | |
| label = "mas-ampss-m0"; | |
| qcom,tier = <0x02>; | |
| }; | |
| fab-snoc { | |
| qcom,hw-sel = "RPM"; | |
| qcom,masterp = <0x04>; | |
| qcom,gateway; | |
| qcom,qport = <0x04>; | |
| qcom,buswidth = <0x08>; | |
| qcom,mode = "Bypass"; | |
| qcom,slavep = <0x02>; | |
| qcom,ws = <0x2710>; | |
| qcom,slv-hw-id = <0x02>; | |
| qcom,mas-hw-id = <0x03>; | |
| cell-id = <0x400>; | |
| label = "fab-snoc"; | |
| }; | |
| }; | |
| cti@fc30f000 { | |
| reg-names = "cti-base"; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x1a>; | |
| compatible = "arm,coresight-cti"; | |
| reg = <0xfc30f000 0x1000>; | |
| coresight-name = "coresight-cti7"; | |
| }; | |
| regulator@f9018000 { | |
| qcom,pvs-fuse = <0x16 0x06 0x05 0x00>; | |
| vdd-mx-supply = <0x5a>; | |
| qcom,cpr-down-threshold = <0x05>; | |
| qcom,vdd-apc-step-down-limit = <0x01>; | |
| qcom,cpr-step-quotient = <0x1e>; | |
| qcom,cpr-fuse-target-quot = <0x18 0x0c 0x00>; | |
| qcom,cpr-idle-clocks = <0x00>; | |
| qcom,cpr-timer-delay = <0x1388>; | |
| regulator-max-microvolt = <0x0e>; | |
| qcom,cpr-apc-volt-step = <0x2710>; | |
| qcom,cpr-timer-cons-up = <0x00>; | |
| qcom,cpr-quot-adjust-table = <0x01 0x05 0x1c2 0x01 0x06 0x177 0x01 0x07 0x12c 0x01 0x08 0xe1 0x01 0x09 0xbb 0x01 0x0a 0x96 0x01 0x0b 0x4b>; | |
| qcom,speed-bin-fuse-sel = <0x16 0x00 0x03 0x00>; | |
| qcom,cpr-voltage-ceiling = <0x116520 0x118c30 0x138800>; | |
| reg-names = "rbcpr\0rbcpr_clk\0efuse_addr"; | |
| interrupts = <0x00 0x0f 0x00>; | |
| regulator-name = "apc_corner"; | |
| qcom,cpr-uplift-max-volt = <0x149970>; | |
| qcom,vdd-mx-vmin-method = <0x01>; | |
| qcom,cpr-uplift-voltage = <0xc350>; | |
| qcom,cpr-irq-line = <0x00>; | |
| qcom,cpr-fuse-read-val = <0x36 0x2a 0x06 0x07>; | |
| qcom,cpr-cond-min-voltage = <0x116520>; | |
| qcom,cpr-fuse-row = <0x8a 0x00>; | |
| status = "okay"; | |
| qcom,vdd-apc-step-up-limit = <0x01>; | |
| qcom,cpr-voltage-floor = <0x116520 0x116520 0x116520>; | |
| regulator-min-microvolt = <0x01>; | |
| qcom,cpr-enable; | |
| qcom,cpr-fuse-redun-sel = <0x8a 0x39 0x01 0x01 0x00>; | |
| qcom,vdd-mx-vmax = <0x149970>; | |
| qcom,cpr-fuse-bp-cpr-disable = <0x24>; | |
| qcom,cpr-fuse-redun-target-quot = <0x18 0x0c 0x00>; | |
| qcom,cpr-fuse-redun-row = <0x8b 0x00>; | |
| qcom,cpr-uplift-speed-bin = <0x01>; | |
| qcom,cpr-fuse-cond-min-volt-sel = <0x36 0x2a 0x06 0x07 0x01>; | |
| compatible = "qcom,cpr-regulator"; | |
| qcom,cpr-fuse-redun-ro-sel = <0x2e 0x24 0x27>; | |
| vdd-apc-supply = <0x59>; | |
| qcom,cpr-timer-cons-down = <0x02>; | |
| qcom,pvs-voltage-table = <0x100590 0x118c30 0x149970 0x100590 0x118c30 0x147260 0x100590 0x118c30 0x144b50 0x100590 0x118c30 0x142440 0x100590 0x118c30 0x13fd30 0x100590 0x118c30 0x13d620 0x100590 0x118c30 0x13af10 0x100590 0x118c30 0x138800 0x100590 0x118c30 0x1360f0 0x100590 0x116520 0x1339e0 0x100590 0x113e10 0x1312d0 0x100590 0x111700 0x12ebc0 0x100590 0x10eff0 0x12c4b0 0x100590 0x10c8e0 0x129da0 0x100590 0x10a1d0 0x127690 0x100590 0x107ac0 0x124f80 0x100590 0x1053b0 0x122870 0x100590 0x102ca0 0x120160 0x100590 0x100590 0x11da50 0x100590 0x100590 0x11b340 0x100590 0x100590 0x118c30 0x100590 0x100590 0x116520 0x100590 0x100590 0x116520 0x100590 0x100590 0x116520 0x100590 0x100590 0x116520 0x100590 0x100590 0x116520 0x100590 0x100590 0x116520 0x100590 0x100590 0x116520 0x100590 0x100590 0x116520 0x100590 0x100590 0x116520 0x100590 0x100590 0x116520 0x100590 0x100590 0x116520>; | |
| qcom,cpr-fuse-bp-scheme = <0x25>; | |
| qcom,cpr-uplift-quotient = <0x00 0x00 0x78>; | |
| qcom,cpr-ref-clk = <0x4b00>; | |
| phandle = <0x51>; | |
| qcom,cpr-min-volt = <0x116520>; | |
| qcom,cpr-corner-map = <0x01 0x01 0x02 0x02 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03>; | |
| reg = <0xf9018000 0x1000 0xf9011064 0x04 0xfc4b8000 0x1000>; | |
| qcom,pvs-fuse-redun = <0x16 0x1b 0x05 0x00>; | |
| qcom,pvs-fuse-redun-sel = <0x16 0x18 0x03 0x02 0x00>; | |
| qcom,cpr-up-threshold = <0x00>; | |
| linux,phandle = <0x51>; | |
| qcom,cpr-fuse-ro-sel = <0x36 0x26 0x29>; | |
| qcom,cpr-gcnt-time = <0x01>; | |
| qcom,cpr-fuse-uplift-sel = <0x16 0x35 0x01 0x00 0x00>; | |
| }; | |
| jtagfuse@fc4be024 { | |
| reg-names = "fuse-base"; | |
| compatible = "qcom,jtag-fuse"; | |
| reg = <0xfc4be024 0x08>; | |
| }; | |
| vddio_disp_vreg { | |
| enable-active-high; | |
| gpio = <0x08 0x22 0x00>; | |
| startup-delay-us = <0x12c>; | |
| regulator-name = "vddio_disp"; | |
| compatible = "regulator-fixed"; | |
| regulator-boot-on; | |
| phandle = <0x23>; | |
| parent-supply = <0x20>; | |
| linux,phandle = <0x23>; | |
| }; | |
| qcom,gdsc@fc401e84 { | |
| regulator-name = "gdsc_usb30"; | |
| status = "disabled"; | |
| compatible = "qcom,gdsc"; | |
| reg = <0xfc401e84 0x04>; | |
| }; | |
| qcom,smp2pgpio-ssr-smp2p-4-in { | |
| gpio-controller; | |
| #interrupt-cells = <0x02>; | |
| qcom,is-inbound; | |
| #gpio-cells = <0x02>; | |
| qcom,entry-name = "slave-kernel"; | |
| compatible = "qcom,smp2pgpio"; | |
| interrupt-controller; | |
| qcom,remote-pid = <0x04>; | |
| phandle = <0x52>; | |
| linux,phandle = <0x52>; | |
| }; | |
| funnel@fc31b000 { | |
| reg-names = "funnel-base"; | |
| coresight-nr-inports = <0x02>; | |
| coresight-id = <0x04>; | |
| coresight-child-list = <0x2d>; | |
| coresight-outports = <0x00>; | |
| coresight-child-ports = <0x00>; | |
| compatible = "arm,coresight-funnel"; | |
| phandle = <0x2e>; | |
| reg = <0xfc31b000 0x1000>; | |
| linux,phandle = <0x2e>; | |
| coresight-name = "coresight-funnel-merg"; | |
| }; | |
| wcd9xxx-irq { | |
| #interrupt-cells = <0x01>; | |
| interrupts = <0x44 0x00>; | |
| interrupt-parent = <0x08>; | |
| compatible = "qcom,wcd9xxx-irq"; | |
| interrupt-controller; | |
| phandle = <0x40>; | |
| interrupt-names = "cdc-int"; | |
| linux,phandle = <0x40>; | |
| }; | |
| qcom,iris-fm { | |
| compatible = "qcom,iris_fm"; | |
| }; | |
| qcom,msm-mem-hole { | |
| compatible = "qcom,msm-mem-hole"; | |
| qcom,memblock-remove = <0x8400000 0x4000000 0xd200000 0x2400000 0xfa00000 0x500000>; | |
| }; | |
| cti@fc30a000 { | |
| reg-names = "cti-base"; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x15>; | |
| compatible = "arm,coresight-cti"; | |
| reg = <0xfc30a000 0x1000>; | |
| coresight-name = "coresight-cti2"; | |
| }; | |
| qcom,mss@fc880000 { | |
| vdd_mx-supply = <0x44>; | |
| qcom,is-loadable; | |
| qcom,gpio-err-ready = <0x56 0x01 0x00>; | |
| qcom,pil-self-auth; | |
| vdd_cx-supply = <0x1c>; | |
| reg-names = "qdsp6_base\0halt_base\0rmb_base\0restart_reg\0cxrail_bhs_reg"; | |
| interrupts = <0x00 0x18 0x01>; | |
| qcom,gpio-err-fatal = <0x56 0x00 0x00>; | |
| qcom,gpio-force-stop = <0x57 0x00 0x00>; | |
| qcom,gpio-proxy-unvote = <0x56 0x02 0x00>; | |
| qcom,gpio-stop-ack = <0x56 0x03 0x00>; | |
| vdd_pll-supply = <0x20>; | |
| qcom,vdd_pll = <0x1b7740>; | |
| compatible = "qcom,pil-q6v5-mss"; | |
| reg = <0xfc880000 0x100 0xfd485000 0x400 0xfc820000 0x20 0xfc401680 0x04 0xfd485194 0x04>; | |
| qcom,firmware-name = "mba"; | |
| }; | |
| qcom,smp2pgpio-ssr-smp2p-1-out { | |
| gpio-controller; | |
| #interrupt-cells = <0x02>; | |
| #gpio-cells = <0x02>; | |
| qcom,entry-name = "master-kernel"; | |
| compatible = "qcom,smp2pgpio"; | |
| interrupt-controller; | |
| qcom,remote-pid = <0x01>; | |
| phandle = <0x57>; | |
| linux,phandle = <0x57>; | |
| }; | |
| jtagmm@fc33c000 { | |
| reg-names = "etm-base\0debug-base"; | |
| compatible = "qcom,jtag-mm"; | |
| reg = <0xfc33c000 0x1000 0xfc330000 0x1000>; | |
| }; | |
| cti@fc34d000 { | |
| reg-names = "cti-base"; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x22>; | |
| compatible = "arm,coresight-cti"; | |
| reg = <0xfc34d000 0x1000>; | |
| coresight-name = "coresight-cti-wcn-cpu0"; | |
| }; | |
| qcom,tz-log@fe805720 { | |
| qcom,memory-reservation-size = <0x1000>; | |
| qcom,memory-reservation-type = "EBI1"; | |
| compatible = "qcom,tz-log"; | |
| reg = <0xfe805720 0x1000>; | |
| }; | |
| qcom,smp2pgpio_test_smp2p_4_out { | |
| gpios = <0x1a 0x00 0x00>; | |
| compatible = "qcom,smp2pgpio_test_smp2p_4_out"; | |
| }; | |
| bootinfo { | |
| android,bootinfo-buffer-start = <0x3eb00000>; | |
| android,bootinfo-buffer-size = <0x800>; | |
| compatible = "android,bootinfo"; | |
| }; | |
| qcom,spm@f90b9000 { | |
| qcom,core-id = <0x03>; | |
| qcom,saw2-cfg = <0x00>; | |
| qcom,saw2-spm-ctl = <0x08>; | |
| qcom,saw2-spm-cmd-wfi = [60 03 60 0b 0f]; | |
| qcom,saw2-spm-dly = <0x3c102800>; | |
| qcom,saw2-spm-cmd-spc = <0x20108030 0x905b6003 0x603b7676 0xb945b80 0x1026300f>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| compatible = "qcom,spm-v2"; | |
| qcom,saw2-spm-cmd-pc = <0x20108030 0x905b6003 0x603b7676 0xb945b80 0x1026300f>; | |
| reg = <0xf90b9000 0x1000>; | |
| qcom,saw2-ver-reg = <0xfd0>; | |
| }; | |
| cti@fc308000 { | |
| reg-names = "cti-base"; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x13>; | |
| compatible = "arm,coresight-cti"; | |
| phandle = <0x26>; | |
| reg = <0xfc308000 0x1000>; | |
| linux,phandle = <0x26>; | |
| coresight-name = "coresight-cti0"; | |
| }; | |
| qcom,csid@fda08400 { | |
| qcom,csi-vdd-voltage = <0x124f80>; | |
| reg-names = "csid"; | |
| interrupts = <0x00 0x34 0x00>; | |
| qcom,mipi-csi-vdd-supply = <0x05>; | |
| cell-index = <0x01>; | |
| compatible = "qcom,csid"; | |
| reg = <0xfda08400 0x100>; | |
| interrupt-names = "csid"; | |
| }; | |
| funnel@fc31a000 { | |
| reg-names = "funnel-base"; | |
| coresight-nr-inports = <0x08>; | |
| coresight-id = <0x06>; | |
| coresight-child-list = <0x2e>; | |
| coresight-outports = <0x00>; | |
| coresight-child-ports = <0x01>; | |
| compatible = "arm,coresight-funnel"; | |
| phandle = <0x2f>; | |
| reg = <0xfc31a000 0x1000>; | |
| linux,phandle = <0x2f>; | |
| coresight-name = "coresight-funnel-in1"; | |
| }; | |
| qcom,msm-stub-codec { | |
| compatible = "qcom,msm-stub-codec"; | |
| }; | |
| qcom,gdsc@fd8c4034 { | |
| regulator-name = "gdsc_oxili_cx"; | |
| status = "ok"; | |
| compatible = "qcom,gdsc"; | |
| phandle = <0x11>; | |
| qcom,clock-names = "core_clk"; | |
| reg = <0xfd8c4034 0x04>; | |
| linux,phandle = <0x11>; | |
| }; | |
| tsens@fc4a8000 { | |
| qcom,sensors = <0x06>; | |
| reg-names = "tsens_physical\0tsens_eeprom_physical"; | |
| interrupts = <0x00 0xb8 0x00>; | |
| qcom,calib-mode = "fuse_map2"; | |
| qcom,slope = <0xb55 0xb1e 0xbde 0xb8b 0xb55 0xb1e>; | |
| compatible = "qcom,msm-tsens"; | |
| reg = <0xfc4a8000 0x2000 0xfc4bc000 0x1000>; | |
| }; | |
| cti@fc30c000 { | |
| reg-names = "cti-base"; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x17>; | |
| compatible = "arm,coresight-cti"; | |
| reg = <0xfc30c000 0x1000>; | |
| coresight-name = "coresight-cti4"; | |
| }; | |
| cti@fc343000 { | |
| reg-names = "cti-base"; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x1f>; | |
| compatible = "arm,coresight-cti"; | |
| reg = <0xfc343000 0x1000>; | |
| coresight-name = "coresight-cti-cpu2"; | |
| }; | |
| qcom,vidc@fdc00000 { | |
| qcom,reg-presets = <0xe0024 0x00 0x80124 0x03 0xe0020 0x5555556 0x800b0 0x10101001 0x800b4 0x101010 0x800c0 0x1010100f 0x800c4 0x101010 0x800d0 0x10 0x800d4 0x10 0x800d8 0x707>; | |
| vdd-supply = <0x10>; | |
| qcom,bus-ports = <0x01>; | |
| interrupts = <0x00 0x2c 0x00>; | |
| qcom,max-hw-load = <0x56220>; | |
| qcom,dec-ddr-ab-ib = <0x00 0x00 0x19258 0x20b70 0x416e0 0x54f60 0x7b4a8 0xa0668>; | |
| qcom,hfi = "venus"; | |
| qcom,buffer-type-tz-usage-table = <0x01 0x01 0x06 0x02 0x7c0 0x03>; | |
| compatible = "qcom,msm-vidc"; | |
| qcom,load-freq-tbl = <0x56220 0x9896800 0x3bc40 0x7f27450 0x1a5e0 0x3f9c2e0>; | |
| reg = <0xfdc00000 0xff000>; | |
| qcom,enc-ddr-ab-ib = <0x00 0x00 0x1f7e8 0x22ab0 0x5dc00 0x67070 0xd36d0 0xe8aa8>; | |
| qcom,vidc-iommu-domains { | |
| qcom,domain-ns { | |
| qcom,vidc-partition-buffer-types = <0x7ff 0x800>; | |
| qcom,vidc-domain-phandle = <0x38>; | |
| }; | |
| qcom,domain-cp { | |
| qcom,vidc-partition-buffer-types = <0x06 0x7c1>; | |
| qcom,vidc-domain-phandle = <0x39>; | |
| }; | |
| }; | |
| }; | |
| qcom,cci@fda0c000 { | |
| qcom,hw-tsu-sta = <0x15>; | |
| gpios = <0x08 0x1d 0x00 0x08 0x1e 0x00>; | |
| qcom,hw-trdhld = <0x06>; | |
| qcom,hw-tlow = <0x1c>; | |
| reg-names = "cci"; | |
| interrupts = <0x00 0x32 0x00>; | |
| qcom,hw-tsu-sto = <0x15>; | |
| qcom,hw-thd-dat = <0x0d>; | |
| #address-cells = <0x01>; | |
| qcom,hw-thigh = <0x14>; | |
| qcom,gpio-tbl-num = <0x00 0x01>; | |
| qcom,hw-thd-sta = <0x12>; | |
| #size-cells = <0x00>; | |
| qcom,hw-scl-stretch-en = <0x00>; | |
| qcom,hw-tbuf = <0x19>; | |
| qcom,gpio-tbl-flags = <0x01 0x01>; | |
| qcom,hw-tsp = <0x03>; | |
| cell-index = <0x00>; | |
| compatible = "qcom,cci"; | |
| reg = <0xfda0c000 0x1000>; | |
| interrupt-names = "cci"; | |
| qcom,gpio-tbl-label = "CCI_I2C_DATA0\0CCI_I2C_CLK0"; | |
| qcom,camera@6c { | |
| qcom,gpio-req-tbl-num = <0x00 0x01 0x02 0x03>; | |
| qcom,sensor-name = "ar0543"; | |
| gpios = <0x08 0x1a 0x00 0x08 0x25 0x00 0x08 0x24 0x00 0x08 0x17 0x00>; | |
| qcom,csi-lane-assign = <0x4320>; | |
| qcom,gpio-req-tbl-label = "CAMIF_MCLK\0CAM_RESET1\0CAM_STANDBY\0CAM_PWREN"; | |
| qcom,cam-vreg-min-voltage = <0x1b7740 0x00 0x00 0x2ab980>; | |
| cam_vana-supply = <0x0d>; | |
| qcom,gpio-set-tbl-num = <0x01 0x01>; | |
| qcom,led-flash-src = <0x0a>; | |
| qcom,csiphy-sd-index = <0x00>; | |
| qcom,gpio-reset = <0x01>; | |
| cam_vdig-supply = <0x0b>; | |
| status = "ok"; | |
| qcom,cam-vreg-name = "cam_vdig\0cam_vio\0cam_vana\0cam_vaf"; | |
| qcom,gpio-standby = <0x02>; | |
| qcom,cam-vreg-type = <0x00 0x01 0x01 0x00>; | |
| qcom,sensor-position = <0x00>; | |
| qcom,cam-vreg-max-voltage = <0x1b7740 0x00 0x00 0x2ab980>; | |
| qcom,slave-id = <0x6c 0x00 0x4800>; | |
| qcom,csid-sd-index = <0x00>; | |
| qcom,cam-vreg-op-mode = <0x19a28 0x00 0x00 0x186a0>; | |
| qcom,cci-master = <0x00>; | |
| qcom,gpio-set-tbl-delay = <0x3e8 0x7530>; | |
| compatible = "qcom,ar0543"; | |
| qcom,sensor-mode = <0x01>; | |
| qcom,gpio-pwren = <0x03>; | |
| qcom,gpio-set-tbl-flags = <0x00 0x02>; | |
| cam_vaf-supply = <0x0e>; | |
| qcom,gpio-no-mux = <0x00>; | |
| reg = <0x6c>; | |
| qcom,gpio-req-tbl-flags = <0x01 0x00 0x00 0x00>; | |
| cam_vio-supply = <0x0c>; | |
| qcom,actuator-src = <0x09>; | |
| qcom,mount-angle = <0x5a>; | |
| qcom,csi-lane-mask = <0x07>; | |
| }; | |
| qcom,cci-master0 { | |
| qcom,hw-tsu-sta = <0x15>; | |
| qcom,hw-trdhld = <0x06>; | |
| qcom,hw-tlow = <0x1c>; | |
| qcom,hw-tsu-sto = <0x15>; | |
| qcom,hw-thd-dat = <0x0d>; | |
| status = "ok"; | |
| qcom,hw-thigh = <0x14>; | |
| qcom,hw-thd-sta = <0x12>; | |
| qcom,hw-scl-stretch-en = <0x00>; | |
| qcom,hw-tbuf = <0x19>; | |
| qcom,hw-tsp = <0x03>; | |
| }; | |
| qcom,camera@90 { | |
| qcom,gpio-req-tbl-num = <0x00 0x01>; | |
| qcom,sensor-name = "mt9m114"; | |
| gpios = <0x08 0x1b 0x00 0x08 0x17 0x00>; | |
| qcom,csi-lane-assign = <0x4320>; | |
| qcom,gpio-req-tbl-label = "CAMIF_MCLK\0CAM_PWREN"; | |
| qcom,cam-vreg-min-voltage = <0x1b7740>; | |
| qcom,gpio-set-tbl-num = <0x01 0x01>; | |
| qcom,csiphy-sd-index = <0x01>; | |
| cam_vdig-supply = <0x0b>; | |
| status = "ok"; | |
| qcom,cam-vreg-name = "cam_vdig"; | |
| qcom,cam-vreg-type = <0x00>; | |
| qcom,sensor-position = <0x01>; | |
| qcom,cam-vreg-max-voltage = <0x1b7740>; | |
| qcom,slave-id = <0x90 0x00 0x2481>; | |
| qcom,csid-sd-index = <0x00>; | |
| qcom,cam-vreg-op-mode = <0x19a28>; | |
| qcom,cci-master = <0x00>; | |
| qcom,gpio-set-tbl-delay = <0x3e8 0xfa0>; | |
| compatible = "qcom,mt9m114"; | |
| qcom,sensor-mode = <0x01>; | |
| qcom,gpio-pwren = <0x01>; | |
| qcom,gpio-set-tbl-flags = <0x00 0x02>; | |
| qcom,gpio-no-mux = <0x00>; | |
| reg = <0x90>; | |
| qcom,gpio-req-tbl-flags = <0x01 0x00>; | |
| qcom,mount-angle = <0x10e>; | |
| qcom,csi-lane-mask = <0x03>; | |
| }; | |
| qcom,cci-master1 { | |
| qcom,hw-tsu-sta = <0x15>; | |
| qcom,hw-trdhld = <0x06>; | |
| qcom,hw-tlow = <0x1c>; | |
| qcom,hw-tsu-sto = <0x15>; | |
| qcom,hw-thd-dat = <0x0d>; | |
| status = "ok"; | |
| qcom,hw-thigh = <0x14>; | |
| qcom,hw-thd-sta = <0x12>; | |
| qcom,hw-scl-stretch-en = <0x00>; | |
| qcom,hw-tbuf = <0x19>; | |
| qcom,hw-tsp = <0x03>; | |
| }; | |
| qcom,actuator@6c { | |
| qcom,cci-master = <0x00>; | |
| cell-index = <0x04>; | |
| compatible = "qcom,actuator"; | |
| phandle = <0x09>; | |
| reg = <0x18 0x00>; | |
| linux,phandle = <0x09>; | |
| }; | |
| }; | |
| qcom,mdss_dsi@fd922800 { | |
| qcom,mdss-mdp = <0x1f>; | |
| qcom,dsi-pref-prim-pan = <0x21>; | |
| lcdbias-supply = <0x24>; | |
| qcom,platform-bist-ctrl = [00 00 b1 ff 00 00]; | |
| vddio-supply = <0x20>; | |
| vdd_disp-supply = <0x22>; | |
| qcom,platform-strength-ctrl = [ff 06]; | |
| qcom,platform-reset-gpio = <0x08 0x19 0x00>; | |
| qcom,mdss-fb-map = <0x1e>; | |
| qcom,platform-regulator-settings = [07 09 03 00 20 00 01]; | |
| cell-index = <0x00>; | |
| qcom,platform-lane-config = [00 00 00 00 00 00 00 01 97 00 00 00 00 05 00 00 01 97 00 00 00 00 0a 00 00 01 97 00 00 00 00 0f 00 00 01 97 00 c0 00 00 00 00 00 01 bb]; | |
| label = "MDSS DSI CTRL->0"; | |
| compatible = "qcom,mdss-dsi-ctrl"; | |
| qcom,platform-te-gpio = <0x08 0x18 0x00>; | |
| vdda-supply = <0x05>; | |
| phandle = <0x1d>; | |
| vddio_disp-supply = <0x23>; | |
| reg = <0xfd922800 0x600>; | |
| linux,phandle = <0x1d>; | |
| qcom,platform-supply-entry1 { | |
| qcom,supply-pre-off-sleep = <0x00>; | |
| qcom,supply-enable-load = <0x186a0>; | |
| qcom,supply-post-on-sleep = <0x00>; | |
| qcom,supply-min-voltage = <0x1b7740>; | |
| qcom,supply-max-voltage = <0x1b7740>; | |
| qcom,supply-post-off-sleep = <0x00>; | |
| qcom,supply-name = "vddio"; | |
| qcom,supply-pre-on-sleep = <0x00>; | |
| qcom,supply-disable-load = <0x64>; | |
| }; | |
| qcom,platform-supply-entry2 { | |
| qcom,supply-pre-off-sleep = <0x00>; | |
| qcom,supply-enable-load = <0x186a0>; | |
| qcom,supply-post-on-sleep = <0x14>; | |
| qcom,supply-min-voltage = <0x124f80>; | |
| qcom,supply-max-voltage = <0x124f80>; | |
| qcom,supply-post-off-sleep = <0x00>; | |
| qcom,supply-name = "vdda"; | |
| qcom,supply-pre-on-sleep = <0x00>; | |
| qcom,supply-disable-load = <0x64>; | |
| }; | |
| }; | |
| qcom,rpm-master-stats@fc428150 { | |
| qcom,masters = "APSS\0MPSS\0LPSS\0PRONTO"; | |
| compatible = "qcom,rpm-master-stats"; | |
| reg = <0xfc428150 0x3200>; | |
| qcom,master-stats-version = <0x02>; | |
| qcom,master-offset = <0xa00>; | |
| }; | |
| qcom,msm-dai-q6-hdmi { | |
| qcom,msm-dai-q6-dev-id = <0x08>; | |
| compatible = "qcom,msm-dai-q6-hdmi"; | |
| }; | |
| qcom,irqrouter@fda00000 { | |
| reg-names = "irqrouter"; | |
| cell-index = <0x00>; | |
| compatible = "qcom,irqrouter"; | |
| reg = <0xfda00000 0x100>; | |
| }; | |
| qcom,smp2pgpio-rdbg-1-in { | |
| gpio-controller; | |
| #interrupt-cells = <0x02>; | |
| qcom,is-inbound; | |
| #gpio-cells = <0x02>; | |
| qcom,entry-name = "rdbg"; | |
| compatible = "qcom,smp2pgpio"; | |
| interrupt-controller; | |
| qcom,remote-pid = <0x01>; | |
| phandle = <0x36>; | |
| linux,phandle = <0x36>; | |
| }; | |
| qcom,gdsc@fd8c1404 { | |
| regulator-name = "gdsc_vpu"; | |
| status = "disabled"; | |
| compatible = "qcom,gdsc"; | |
| reg = <0xfd8c1404 0x04>; | |
| }; | |
| qcom,msm-dai-fe { | |
| compatible = "qcom,msm-dai-fe"; | |
| }; | |
| msm-periph-noc@fc468000 { | |
| qcom,hw-sel = "NoC"; | |
| qcom,fabclk-dual = "bus_clk"; | |
| qcom,rpm-en; | |
| cell-id = <0x1000>; | |
| qcom,ntieredslaves = <0x00>; | |
| qcom,fabclk-active = "bus_a_clk"; | |
| label = "msm_periph_noc"; | |
| compatible = "msm-bus-fabric"; | |
| reg = <0xfc468000 0x4000>; | |
| mas-sdcc-2 { | |
| qcom,masterp = <0x02>; | |
| qcom,buswidth = <0x08>; | |
| qcom,mas-hw-id = <0x23>; | |
| cell-id = <0x51>; | |
| label = "mas-sdcc-2"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-bam-dma { | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x03>; | |
| qcom,slv-hw-id = <0x24>; | |
| cell-id = <0x262>; | |
| label = "slv-bam-dma"; | |
| qcom,tier = <0x02>; | |
| }; | |
| mas-sdcc-1 { | |
| qcom,masterp = <0x00>; | |
| qcom,buswidth = <0x08>; | |
| qcom,mas-hw-id = <0x21>; | |
| cell-id = <0x4e>; | |
| label = "mas-sdcc-1"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-prng { | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x0a>; | |
| qcom,slv-hw-id = <0x2c>; | |
| cell-id = <0x26a>; | |
| label = "slv-prng"; | |
| qcom,tier = <0x02>; | |
| }; | |
| mas-usb-hsic { | |
| qcom,masterp = <0x04>; | |
| qcom,buswidth = <0x08>; | |
| qcom,mas-hw-id = <0x28>; | |
| cell-id = <0x55>; | |
| label = "mas-usb-hsic"; | |
| qcom,tier = <0x02>; | |
| }; | |
| mas-usb-hs { | |
| qcom,masterp = <0x06>; | |
| qcom,buswidth = <0x08>; | |
| qcom,mas-hw-id = <0x2a>; | |
| cell-id = <0x57>; | |
| label = "mas-usb-hs"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-blsp-1 { | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x05>; | |
| qcom,slv-hw-id = <0x27>; | |
| cell-id = <0x265>; | |
| label = "slv-blsp-1"; | |
| qcom,tier = <0x02>; | |
| }; | |
| mas-blsp-1 { | |
| qcom,masterp = <0x05>; | |
| qcom,buswidth = <0x08>; | |
| qcom,mas-hw-id = <0x29>; | |
| cell-id = <0x56>; | |
| label = "mas-blsp-1"; | |
| qcom,tier = <0x02>; | |
| }; | |
| mas-pnoc-cfg { | |
| qcom,masterp = <0x07>; | |
| qcom,buswidth = <0x08>; | |
| qcom,mas-hw-id = <0x2b>; | |
| cell-id = <0x58>; | |
| label = "mas-pnoc-cfg"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-sdcc-3 { | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x01>; | |
| qcom,slv-hw-id = <0x20>; | |
| cell-id = <0x25f>; | |
| label = "slv-sdcc-3"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-usb-hs { | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x06>; | |
| qcom,slv-hw-id = <0x28>; | |
| cell-id = <0x266>; | |
| label = "slv-usb-hs"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-sdcc-2 { | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x02>; | |
| qcom,slv-hw-id = <0x21>; | |
| cell-id = <0x260>; | |
| label = "slv-sdcc-2"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-sdcc-1 { | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x00>; | |
| qcom,slv-hw-id = <0x1f>; | |
| cell-id = <0x25e>; | |
| label = "slv-sdcc-1"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-periph-apu-cfg { | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x08>; | |
| qcom,slv-hw-id = <0x2a>; | |
| cell-id = <0x268>; | |
| label = "slv-periph-apu-cfg"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-pdm { | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x07>; | |
| qcom,slv-hw-id = <0x29>; | |
| cell-id = <0x267>; | |
| label = "slv-pdm"; | |
| qcom,tier = <0x02>; | |
| }; | |
| mas-sdcc-3 { | |
| qcom,masterp = <0x01>; | |
| qcom,buswidth = <0x08>; | |
| qcom,mas-hw-id = <0x22>; | |
| cell-id = <0x4f>; | |
| label = "mas-sdcc-3"; | |
| qcom,tier = <0x02>; | |
| }; | |
| mas-bam-dma { | |
| qcom,masterp = <0x03>; | |
| qcom,buswidth = <0x08>; | |
| qcom,mas-hw-id = <0x26>; | |
| cell-id = <0x53>; | |
| label = "mas-bam-dma"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-pnoc-mpu-cfg { | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x09>; | |
| qcom,slv-hw-id = <0x2b>; | |
| cell-id = <0x269>; | |
| label = "slv-pnoc-mpu-cfg"; | |
| qcom,tier = <0x02>; | |
| }; | |
| fab-snoc { | |
| qcom,masterp = <0x08>; | |
| qcom,gateway; | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x0c>; | |
| qcom,slv-hw-id = <0x2d>; | |
| qcom,mas-hw-id = <0x2c>; | |
| cell-id = <0x400>; | |
| label = "fab-snoc"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-usb-hsic { | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x04>; | |
| qcom,slv-hw-id = <0x26>; | |
| cell-id = <0x264>; | |
| label = "slv-usb-hsic"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-service-pnoc { | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x0c>; | |
| qcom,slv-hw-id = <0x2e>; | |
| cell-id = <0x26b>; | |
| label = "slv-service-pnoc"; | |
| qcom,tier = <0x02>; | |
| }; | |
| }; | |
| cti@fc354000 { | |
| reg-names = "cti-base"; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x24>; | |
| compatible = "arm,coresight-cti"; | |
| reg = <0xfc354000 0x1000>; | |
| coresight-name = "coresight-cti-audio-cpu0"; | |
| }; | |
| qcom,smp2pgpio_client_rdbg_1_in { | |
| gpios = <0x36 0x00 0x00>; | |
| compatible = "qcom,smp2pgpio_client_rdbg_1_in"; | |
| }; | |
| qcom,msm-rng@f9bff000 { | |
| qcom,msm-bus,vectors-KBps = <0x36 0x26a 0x00 0x00 0x36 0x26a 0x00 0x320>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-rng-iface-clk; | |
| compatible = "qcom,msm-rng"; | |
| reg = <0xf9bff000 0x200>; | |
| qcom,msm-bus,name = "msm-rng-noc"; | |
| }; | |
| qcom,msm-efuse { | |
| qcom,memory-reservation-size = <0x1000>; | |
| qcom,memory-reservation-type = "EBI1"; | |
| compatible = "qcom,msm-efuse"; | |
| }; | |
| stm@fc321000 { | |
| reg-names = "stm-base\0stm-data-base"; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x09>; | |
| coresight-child-list = <0x2f>; | |
| coresight-outports = <0x00>; | |
| coresight-child-ports = <0x07>; | |
| compatible = "arm,coresight-stm"; | |
| reg = <0xfc321000 0x1000 0xfa280000 0x180000>; | |
| coresight-name = "coresight-stm"; | |
| }; | |
| qcom,smp2pgpio-smp2p-4-out { | |
| gpio-controller; | |
| #interrupt-cells = <0x02>; | |
| #gpio-cells = <0x02>; | |
| qcom,entry-name = "smp2p"; | |
| compatible = "qcom,smp2pgpio"; | |
| interrupt-controller; | |
| qcom,remote-pid = <0x04>; | |
| phandle = <0x1a>; | |
| linux,phandle = <0x1a>; | |
| }; | |
| qcom,iommu@fdc84000 { | |
| qcom,iommu-pmu-event-classes = <0x00 0x01 0x08 0x09 0x0a 0x10 0x11 0x12 0x80 0x81 0x82 0x83 0x90 0x91 0x92 0xb0 0xb1>; | |
| qcom,iommu-secure-id = <0x00>; | |
| qcom,msm-bus,vectors-KBps = <0x3f 0x200 0x00 0x00 0x3f 0x200 0x00 0x3e8>; | |
| qcom,iommu-pmu-ngroups = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| vdd-supply = <0x10>; | |
| qcom,iommu-bfb-data = <0xffffffff 0xffffffff 0x04 0x08 0x00 0x00 0x94 0xb4 0x00 0x94 0x114 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; | |
| qcom,needs-alt-core-clk; | |
| reg-names = "iommu_base\0clk_base"; | |
| interrupts = <0x00 0x2d 0x00>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| ranges; | |
| status = "ok"; | |
| #address-cells = <0x01>; | |
| qcom,iommu-bfb-regs = <0x204c 0x2050 0x2514 0x2540 0x256c 0x20ac 0x215c 0x220c 0x2314 0x2394 0x2414 0x2008 0x200c 0x2010 0x2014 0x2018 0x201c 0x2020 0x2024 0x2028 0x202c 0x2030 0x2034 0x2038>; | |
| #size-cells = <0x01>; | |
| label = "venus_iommu"; | |
| compatible = "qcom,msm-smmu-v1"; | |
| qcom,iommu-pmu-ncounters = <0x08>; | |
| reg = <0xfdc84000 0x10000 0xfdce0004 0x04>; | |
| qcom,msm-bus,name = "venus_ebi"; | |
| qcom,iommu-enable-halt; | |
| qcom,iommu-ctx@fdc8d000 { | |
| interrupts = <0x00 0x2a 0x00 0x00 0x2b 0x00>; | |
| qcom,secure-context; | |
| qcom,iommu-ctx-sids = <0x80 0x81 0x82 0x83 0x84>; | |
| label = "venus_cp"; | |
| compatible = "qcom,msm-smmu-v1-ctx"; | |
| phandle = <0x33>; | |
| reg = <0xfdc8d000 0x1000>; | |
| linux,phandle = <0x33>; | |
| }; | |
| qcom,iommu-ctx@fdc8c000 { | |
| interrupts = <0x00 0x2a 0x00>; | |
| qcom,iommu-ctx-sids = <0x00 0x01 0x02 0x03 0x04 0x05 0x07>; | |
| label = "venus_ns"; | |
| compatible = "qcom,msm-smmu-v1-ctx"; | |
| phandle = <0x32>; | |
| reg = <0xfdc8c000 0x1000>; | |
| linux,phandle = <0x32>; | |
| }; | |
| qcom,iommu-ctx@fdc8e000 { | |
| interrupts = <0x00 0x2a 0x00 0x00 0x2b 0x00>; | |
| qcom,secure-context; | |
| qcom,iommu-ctx-sids = <0xc0 0xc6>; | |
| label = "venus_fw"; | |
| compatible = "qcom,msm-smmu-v1-ctx"; | |
| reg = <0xfdc8e000 0x1000>; | |
| }; | |
| }; | |
| qcom,iommu@fdee4000 { | |
| qcom,iommu-pmu-event-classes = <0x00 0x01 0x08 0x09 0x0a 0x10 0x11 0x12 0x80 0x81 0x82 0x83 0x90 0x91 0x92 0xb0 0xb1>; | |
| qcom,msm-bus,vectors-KBps = <0x5d 0x200 0x00 0x00 0x5d 0x200 0x00 0x3e8>; | |
| qcom,iommu-pmu-ngroups = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| qcom,iommu-bfb-data = <0xffff 0x04 0x10 0x00 0x00 0x0f 0x4b 0x00 0x1e00 0x1e00 0x5a0f 0x00 0x00 0x00 0x00 0x00>; | |
| reg-names = "iommu_base"; | |
| interrupts = <0x00 0x93 0x00>; | |
| qcom,iommu-lpae-bfb-regs = <0x204c 0x2514 0x2540 0x256c 0x2314 0x2394 0x2414 0x2494 0x20ac 0x215c 0x220c 0x22bc 0x2008 0x200c 0x2010 0x2014>; | |
| qcom,iommu-lpae-bfb-data = <0xffff 0x00 0x04 0x10 0x00 0x00 0x0f 0x4b 0x1e00 0x5a2d 0x1e00 0x5a0f 0x00 0x00 0x00 0x00>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| ranges; | |
| status = "disabled"; | |
| #address-cells = <0x01>; | |
| qcom,iommu-bfb-regs = <0x204c 0x2514 0x2540 0x256c 0x2314 0x2394 0x2414 0x2494 0x20ac 0x215c 0x220c 0x22bc 0x2008 0x200c 0x2010 0x2014>; | |
| #size-cells = <0x01>; | |
| label = "vpu_iommu"; | |
| compatible = "qcom,msm-smmu-v1"; | |
| qcom,iommu-pmu-ncounters = <0x08>; | |
| reg = <0xfdee4000 0x10000>; | |
| qcom,msm-bus,name = "vpu_ebi"; | |
| qcom,iommu-ctx@fdeed000 { | |
| interrupts = <0x00 0x91 0x00>; | |
| qcom,iommu-ctx-sids = <0x08 0x09>; | |
| label = "vpu_cb_1"; | |
| compatible = "qcom,msm-smmu-v1-ctx"; | |
| reg = <0xfdeed000 0x1000>; | |
| }; | |
| qcom,iommu-ctx@fdeec000 { | |
| interrupts = <0x00 0x91 0x00>; | |
| qcom,iommu-ctx-sids = <0x00 0x01 0x03>; | |
| label = "vpu_cb_0"; | |
| compatible = "qcom,msm-smmu-v1-ctx"; | |
| reg = <0xfdeec000 0x1000>; | |
| }; | |
| qcom,iommu-ctx@fdeee000 { | |
| interrupts = <0x00 0x91 0x00>; | |
| qcom,iommu-ctx-sids = <0x05 0x07 0x0f>; | |
| label = "vpu_cb_2"; | |
| compatible = "qcom,msm-smmu-v1-ctx"; | |
| reg = <0xfdeee000 0x1000>; | |
| }; | |
| }; | |
| gpio_keys { | |
| input-name = "gpio-keys"; | |
| compatible = "gpio-keys"; | |
| vol_up { | |
| gpios = <0x08 0x6a 0x01>; | |
| linux,input-type = <0x01>; | |
| gpio-key,wakeup; | |
| debounce-interval = <0x0f>; | |
| linux,code = <0x73>; | |
| label = "volume_up"; | |
| }; | |
| lid-sw { | |
| gpios = <0x08 0x33 0x01>; | |
| linux,input-type = <0x05>; | |
| gpio-key,wakeup; | |
| debounce-interval = <0x0f>; | |
| linux,code = <0x00>; | |
| label = "lid-switch"; | |
| }; | |
| }; | |
| funnel@fc345000 { | |
| reg-names = "funnel-base"; | |
| coresight-nr-inports = <0x04>; | |
| coresight-id = <0x07>; | |
| coresight-child-list = <0x2f>; | |
| coresight-outports = <0x00>; | |
| coresight-child-ports = <0x05>; | |
| compatible = "arm,coresight-funnel"; | |
| phandle = <0x30>; | |
| reg = <0xfc345000 0x1000>; | |
| linux,phandle = <0x30>; | |
| coresight-name = "coresight-funnel-a7ss"; | |
| }; | |
| qcom,smp2pgpio-rdbg-1-out { | |
| gpio-controller; | |
| #interrupt-cells = <0x02>; | |
| #gpio-cells = <0x02>; | |
| qcom,entry-name = "rdbg"; | |
| compatible = "qcom,smp2pgpio"; | |
| interrupt-controller; | |
| qcom,remote-pid = <0x01>; | |
| phandle = <0x37>; | |
| linux,phandle = <0x37>; | |
| }; | |
| qcom,smp2pgpio_client_rdbg_1_out { | |
| gpios = <0x37 0x00 0x00>; | |
| compatible = "qcom,smp2pgpio_client_rdbg_1_out"; | |
| }; | |
| qcom,smp2pgpio_test_smp2p_7_in { | |
| gpios = <0x13 0x00 0x00>; | |
| compatible = "qcom,smp2pgpio_test_smp2p_7_in"; | |
| }; | |
| sdhci@f98a4900 { | |
| qcom,bus-width = <0x04>; | |
| qcom,msm-bus,vectors-KBps = <0x51 0x200 0x00 0x00 0x51 0x200 0x640 0xc80 0x51 0x200 0x13880 0x27100 0x51 0x200 0x186a0 0x30d40 0x51 0x200 0x30d40 0x61a80 0x51 0x200 0x61a80 0xc3500 0x51 0x200 0x61a80 0xc3500 0x51 0x200 0x1f4000 0x3e8000>; | |
| qcom,msm-bus,num-cases = <0x08>; | |
| reg-names = "hc_mem\0core_mem"; | |
| interrupts = <0x00 0x7d 0x00 0x00 0xdd 0x00>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,bus-bw-vectors-bps = <0x00 0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100 0xbebc200 0xffffffff>; | |
| status = "disabled"; | |
| compatible = "qcom,sdhci-msm"; | |
| reg = <0xf98a4900 0x11c 0xf98a4000 0x800>; | |
| qcom,msm-bus,name = "sdhc2"; | |
| interrupt-names = "hc_irq\0pwr_irq"; | |
| }; | |
| qcom,rpm-log@fc19dc00 { | |
| qcom,offset-log-len-mask = <0x2c>; | |
| qcom,offset-page-buffer-addr = <0x24>; | |
| qcom,offset-log-len = <0x28>; | |
| qcom,rpm-addr-phys = <0xfc000000>; | |
| compatible = "qcom,rpm-log"; | |
| qcom,offset-version = <0x04>; | |
| reg = <0xfc19dc00 0x4000>; | |
| qcom,offset-page-indices = <0x38>; | |
| }; | |
| hwevent@fd828018 { | |
| reg-names = "mmss-mux\0apcs-mux\0ppss-mux\0gcc-mux"; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x26>; | |
| compatible = "qcom,coresight-hwevent"; | |
| qcom,hwevent-clks = "core_mmss_clk"; | |
| reg = <0xfd828018 0x80 0xf9011080 0x80 0xfd4ab160 0x80 0xfc401600 0x80>; | |
| coresight-name = "coresight-hwevent"; | |
| }; | |
| qcom,msm-pcm-routing { | |
| compatible = "qcom,msm-pcm-routing"; | |
| }; | |
| qcom,smp2pgpio-smp2p-4-in { | |
| gpio-controller; | |
| #interrupt-cells = <0x02>; | |
| qcom,is-inbound; | |
| #gpio-cells = <0x02>; | |
| qcom,entry-name = "smp2p"; | |
| compatible = "qcom,smp2pgpio"; | |
| interrupt-controller; | |
| qcom,remote-pid = <0x04>; | |
| phandle = <0x19>; | |
| linux,phandle = <0x19>; | |
| }; | |
| qcom,wdt@f9017000 { | |
| qcom,pet-time = <0x2710>; | |
| qcom,bark-time = <0x55f0>; | |
| interrupts = <0x00 0x03 0x00 0x00 0x04 0x00>; | |
| qcom,memory-reservation-size = <0xb000>; | |
| qcom,memory-reservation-type = "EBI1"; | |
| compatible = "qcom,msm-watchdog"; | |
| reg = <0xf9017000 0x1000>; | |
| qcom,ipi-ping; | |
| }; | |
| qcom,gdsc@fd8c1044 { | |
| regulator-name = "gdsc_venus_core1"; | |
| status = "disabled"; | |
| compatible = "qcom,gdsc"; | |
| reg = <0xfd8c1044 0x04>; | |
| }; | |
| sdhci@f9864900 { | |
| qcom,bus-width = <0x04>; | |
| qcom,gpio-names = "CLK\0CMD\0DAT0\0DAT1\0DAT2\0DAT3"; | |
| qcom,msm-bus,vectors-KBps = <0x4f 0x200 0x00 0x00 0x4f 0x200 0x640 0xc80 0x4f 0x200 0x13880 0x27100 0x4f 0x200 0x186a0 0x30d40 0x4f 0x200 0x30d40 0x61a80 0x4f 0x200 0x61a80 0xc3500 0x4f 0x200 0x61a80 0xc3500 0x4f 0x200 0x1f4000 0x3e8000>; | |
| gpios = <0x08 0x2c 0x00 0x08 0x2b 0x00 0x08 0x2a 0x00 0x08 0x29 0x00 0x08 0x28 0x00 0x08 0x27 0x00>; | |
| qcom,msm-bus,num-cases = <0x08>; | |
| #interrupt-cells = <0x01>; | |
| qcom,clk-rates = <0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100>; | |
| reg-names = "hc_mem\0core_mem"; | |
| interrupts = <0x00 0x01 0x02>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,bus-bw-vectors-bps = <0x00 0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100 0xbebc200 0xffffffff>; | |
| interrupt-map = <0x00 0x01 0x00 0x7f 0x00 0x01 0x01 0x00 0xe0 0x00 0x02 0x08 0x29 0x08>; | |
| interrupt-parent = <0x4b>; | |
| status = "disabled"; | |
| #address-cells = <0x00>; | |
| interrupt-map-mask = <0xffffffff>; | |
| compatible = "qcom,sdhci-msm"; | |
| phandle = <0x4b>; | |
| reg = <0xf9864900 0x11c 0xf9864000 0x800>; | |
| qcom,msm-bus,name = "sdhc3"; | |
| interrupt-names = "hc_irq\0pwr_irq\0sdiowakeup_irq"; | |
| linux,phandle = <0x4b>; | |
| }; | |
| qcom,iommu-domains { | |
| compatible = "qcom,iommu-domains"; | |
| qcom,iommu-domain1 { | |
| qcom,iommu-contexts = <0x32>; | |
| qcom,virtual-addr-pool = <0x40000000 0x3f000000 0x7f000000 0x1000000>; | |
| label = "venus_ns"; | |
| phandle = <0x38>; | |
| linux,phandle = <0x38>; | |
| }; | |
| qcom,iommu-domain2 { | |
| qcom,secure-domain; | |
| qcom,iommu-contexts = <0x33>; | |
| qcom,virtual-addr-pool = <0x1000000 0x1f800000 0x20800000 0x1f800000>; | |
| label = "venus_cp"; | |
| phandle = <0x39>; | |
| linux,phandle = <0x39>; | |
| }; | |
| }; | |
| cti@fc309000 { | |
| reg-names = "cti-base"; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x14>; | |
| compatible = "arm,coresight-cti"; | |
| reg = <0xfc309000 0x1000>; | |
| coresight-name = "coresight-cti1"; | |
| }; | |
| cpu-pmu { | |
| qcom,irq-is-percpu; | |
| interrupts = <0x01 0x07 0xf00>; | |
| compatible = "arm,cortex-a7-pmu"; | |
| }; | |
| factory_support { | |
| gpios = <0x08 0x05 0x02>; | |
| gpio-names = "factory_kill_disable"; | |
| compatible = "mmi,factory-support-msm8960"; | |
| }; | |
| qcom,cpu-sleep-status@f9088008 { | |
| compatible = "qcom,cpu-sleep-status"; | |
| qcom,cpu-alias-addr = <0x10000>; | |
| reg = <0xf9088008 0x100>; | |
| qcom,sleep-status-mask = <0x80000>; | |
| }; | |
| cti@fc350000 { | |
| reg-names = "cti-base"; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x23>; | |
| compatible = "arm,coresight-cti"; | |
| reg = <0xfc350000 0x1000>; | |
| coresight-name = "coresight-cti-modem-cpu0"; | |
| }; | |
| sound { | |
| qcom,cdc-mclk-gpios = <0x43 0x01 0x00>; | |
| qcom,prim-auxpcm-gpio-set = "prim-gpio-prim"; | |
| qcom,prim-auxpcm-gpio-clk = <0x08 0x3f 0x00>; | |
| qcom,prim-auxpcm-gpio-sync = <0x08 0x40 0x00>; | |
| qcom,model = "msm8226-tapan-snd-card"; | |
| qcom,audio-routing = "RX_BIAS\0MCLK\0LDO_H\0MCLK\0SPK_OUT\0MCLK\0SPK_OUT\0EXT_VDD_SPKR\0AMIC1\0MIC BIAS1 External\0MIC BIAS1 External\0Handset Mic\0AMIC2\0MIC BIAS2 External\0MIC BIAS2 External\0Headset Mic\0AMIC3\0MIC BIAS1 External\0MIC BIAS1 External\0ANCRight Headset Mic\0AMIC4\0MIC BIAS2 External\0MIC BIAS2 External\0ANCLeft Headset Mic"; | |
| compatible = "qcom,msm8226-audio-tapan"; | |
| qcom,cdc-vdd-spkr-gpios = <0x43 0x02 0x00>; | |
| qcom,tapan-mclk-clk-freq = <0x927c00>; | |
| qcom,prim-auxpcm-gpio-din = <0x08 0x41 0x00>; | |
| qcom,prim-auxpcm-gpio-dout = <0x08 0x42 0x00>; | |
| }; | |
| qcom,gdsc@fd8c36a4 { | |
| regulator-name = "gdsc_vfe"; | |
| status = "ok"; | |
| compatible = "qcom,gdsc"; | |
| phandle = <0x06>; | |
| qcom,clock-names = "core_clk\0csi_clk\0cpp_clk"; | |
| reg = <0xfd8c36a4 0x04>; | |
| linux,phandle = <0x06>; | |
| }; | |
| tmc@fc322000 { | |
| coresight-ctis = <0x26 0x27>; | |
| qcom,memory-size = <0x100000>; | |
| reg-names = "tmc-base\0bam-base"; | |
| interrupts = <0x00 0xa6 0x00>; | |
| coresight-nr-inports = <0x01>; | |
| coresight-id = <0x00>; | |
| compatible = "arm,coresight-tmc"; | |
| phandle = <0x2a>; | |
| reg = <0xfc322000 0x1000 0xfc37c000 0x3000>; | |
| interrupt-names = "byte-cntr-irq"; | |
| linux,phandle = <0x2a>; | |
| coresight-name = "coresight-tmc-etr"; | |
| }; | |
| qti,msm-pcm-low-latency { | |
| qti,latency-level = "regular"; | |
| qti,msm-pcm-low-latency; | |
| compatible = "qti,msm-pcm-dsp"; | |
| qti,msm-pcm-dsp-id = <0x01>; | |
| }; | |
| qcom,bcl { | |
| compatible = "qcom,bcl"; | |
| }; | |
| qcom,wcnss-wlan@fb000000 { | |
| gpios = <0x08 0x28 0x00 0x08 0x29 0x00 0x08 0x2a 0x00 0x08 0x2b 0x00 0x08 0x2c 0x00>; | |
| qcom,has-autodetect-xo; | |
| qcom,iris-vddrfa-supply = <0x46>; | |
| qcom,wcnss-adc_tm = <0x48>; | |
| reg-names = "wcnss_mmio\0wcnss_fiq"; | |
| interrupts = <0x00 0x91 0x00 0x00 0x92 0x00>; | |
| qcom,pronto-vddpx-supply = <0x0b>; | |
| qcom,iris-vdddig-supply = <0x46>; | |
| qcom,pronto-vddmx-supply = <0x44>; | |
| qcom,pronto-vddcx-supply = <0x45>; | |
| qcom,iris-vddpa-supply = <0x47>; | |
| compatible = "qcom,wcnss_wlan"; | |
| qcom,iris-vddxo-supply = <0x3a>; | |
| reg = <0xfb000000 0x280000 0xf9011008 0x04>; | |
| qcom,has-pronto-hw; | |
| interrupt-names = "wcnss_wlantx_irq\0wcnss_wlanrx_irq"; | |
| }; | |
| qcom,msm-cam@fd8c0000 { | |
| reg-names = "msm-cam"; | |
| compatible = "qcom,msm-cam"; | |
| reg = <0xfd8c0000 0x10000>; | |
| }; | |
| qcom,msm-pcm-lpa { | |
| compatible = "qcom,msm-pcm-lpa"; | |
| }; | |
| msm-ocmem-vnoc@6144 { | |
| qcom,hw-sel = "NoC"; | |
| qcom,rpm-en; | |
| qcom,virt; | |
| cell-id = <0x1800>; | |
| qcom,ntieredslaves = <0x00>; | |
| label = "msm-ocmem-vnoc"; | |
| compatible = "msm-bus-fabric"; | |
| reg = <0x6144 0x02>; | |
| mas-v-ocmem-gfx3d { | |
| qcom,buswidth = <0x08>; | |
| qcom,mas-hw-id = <0x37>; | |
| cell-id = <0x59>; | |
| label = "mas-v-ocmem-gfx3d"; | |
| qcom,tier = <0x02>; | |
| }; | |
| fab-onoc { | |
| qcom,gateway; | |
| qcom,buswidth = <0x10>; | |
| qcom,ws = <0x2710>; | |
| qcom,slv-hw-id = <0x4f>; | |
| qcom,mas-hw-id = <0x38>; | |
| cell-id = <0xc00>; | |
| label = "fab-onoc"; | |
| }; | |
| slv-ocmem { | |
| qcom,buswidth = <0x10>; | |
| qcom,slavep = <0x00 0x01>; | |
| qcom,slv-hw-id = <0x12>; | |
| qcom,slaveclk-active = "ocmem_a_clk"; | |
| cell-id = <0x25c>; | |
| qcom,slaveclk-dual = "ocmem_clk"; | |
| label = "slv-ocmem"; | |
| qcom,tier = <0x02>; | |
| }; | |
| fab-snoc { | |
| qcom,gateway; | |
| qcom,buswidth = <0x20>; | |
| qcom,ws = <0x2710>; | |
| qcom,slv-hw-id = <0x50>; | |
| qcom,mas-hw-id = <0x39>; | |
| cell-id = <0x400>; | |
| label = "fab-snoc"; | |
| }; | |
| }; | |
| qcom,battery-data { | |
| qcom,rpull-up-kohm = <0x64>; | |
| qcom,vref-batt-therm-uv = <0x1b7740>; | |
| phandle = <0x4f>; | |
| linux,phandle = <0x4f>; | |
| mmi,ed30-temp-batterydata { | |
| qcom,flat-ocv-threshold-uv = <0x39fbc0>; | |
| qcom,rbatt-capacitive-mohm = <0x00>; | |
| qcom,v-cutoff-uv = <0x30d400>; | |
| qcom,default-rbatt-mohm = <0xc1>; | |
| qcom,batt-id-range = <0x35b68 0x3adce>; | |
| qcom,chg-term-ua = <0x26d18>; | |
| qcom,max-voltage-uv = <0x401640>; | |
| qcom,batt-id-kohm = <0x0a>; | |
| qcom,fcc-mah = <0x79e>; | |
| qcom,fcc-temp-lut { | |
| qcom,lut-col-legend = <0xfffffff6 0x00 0x17 0x3c>; | |
| qcom,lut-data = <0x79e 0x79e 0x79e 0x79e>; | |
| }; | |
| qcom,pc-temp-ocv-lut { | |
| qcom,lut-row-legend = <0x64 0x5f 0x5a 0x55 0x50 0x4b 0x46 0x41 0x3c 0x37 0x32 0x2d 0x28 0x23 0x1e 0x19 0x14 0x0f 0x0a 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00>; | |
| qcom,lut-col-legend = <0xfffffff6 0x17 0x3c>; | |
| qcom,lut-data = <0x1065 0x105e 0x1051 0x102d 0x1026 0x101f 0x1001 0xff8 0xff1 0xfd4 0xfce 0xfc7 0xfa0 0xfa0 0xfa0 0xf7b 0xf7e 0xf7d 0xf5c 0xf61 0xf5d 0xf3c 0xf45 0xf40 0xf1c 0xf2c 0xf27 0xf01 0xf05 0xeff 0xeeb 0xee7 0xee6 0xeda 0xed6 0xed5 0xed0 0xecb 0xec7 0xeca 0xec3 0xebe 0xec3 0xebf 0xeac 0xeb8 0xeb8 0xe9a 0xea3 0xe9e 0xe84 0xe87 0xe72 0xe60 0xe74 0xe66 0xe53 0xe72 0xe64 0xe52 0xe6f 0xe62 0xe4f 0xe6b 0xe5f 0xe49 0xe62 0xe55 0xe3c 0xe4b 0xe3c 0xe22 0xe21 0xe14 0xdf8 0xdec 0xde0 0xdc2 0xda4 0xd96 0xd7b 0xd3d 0xd2d 0xd14 0xc80 0xc80 0xc80>; | |
| }; | |
| qcom,rbatt-sf-lut { | |
| qcom,lut-row-legend = <0x64 0x5f 0x5a 0x55 0x50 0x4b 0x46 0x41 0x3c 0x37 0x32 0x2d 0x28 0x23 0x1e 0x19 0x14 0x0f 0x0a 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00>; | |
| qcom,lut-col-legend = <0xfffffff6 0x17 0x3c>; | |
| qcom,lut-data = <0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64>; | |
| }; | |
| }; | |
| mmi,ed30-lg-batterydata { | |
| qcom,flat-ocv-threshold-uv = <0x39fbc0>; | |
| qcom,rbatt-capacitive-mohm = <0x00>; | |
| qcom,v-cutoff-uv = <0x30d400>; | |
| qcom,default-rbatt-mohm = <0xde>; | |
| qcom,batt-id-range = <0x1171e8 0x125639>; | |
| qcom,chg-term-ua = <0x26d18>; | |
| qcom,max-voltage-uv = <0x426030>; | |
| qcom,batt-id-kohm = <0x82>; | |
| qcom,fcc-mah = <0x7e6>; | |
| qcom,fcc-temp-lut { | |
| qcom,lut-col-legend = <0xfffffff6 0x00 0x17 0x3c>; | |
| qcom,lut-data = <0x5b6 0x726 0x7e6 0x7c8>; | |
| }; | |
| qcom,pc-temp-ocv-lut { | |
| qcom,lut-row-legend = <0x64 0x5f 0x5a 0x55 0x50 0x4b 0x46 0x41 0x3c 0x37 0x32 0x2d 0x28 0x23 0x1e 0x19 0x14 0x0f 0x0a 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00>; | |
| qcom,lut-col-legend = <0xfffffff6 0x17 0x3c>; | |
| qcom,lut-data = <0x10cc 0x10cc 0x10cc 0x10a3 0x109c 0x1092 0x106a 0x1066 0x105b 0x1035 0x1031 0x1026 0x1003 0xfff 0xff3 0xfcd 0xfd1 0xfc4 0xf93 0xfa0 0xf99 0xf66 0xf7b 0xf72 0xf41 0xf57 0xf4f 0xf1d 0xf24 0xf1f 0xf00 0xf03 0xefe 0xee9 0xeed 0xee7 0xed8 0xedc 0xed5 0xecd 0xece 0xec6 0xec4 0xec4 0xeb1 0xeb8 0xeb9 0xe9d 0xea3 0xe9e 0xe87 0xe83 0xe7b 0xe64 0xe72 0xe68 0xe54 0xe70 0xe67 0xe52 0xe6e 0xe65 0xe4f 0xe69 0xe62 0xe4a 0xe5f 0xe59 0xe3c 0xe44 0xe42 0xe23 0xe18 0xe1c 0xdfc 0xde0 0xdea 0xdc7 0xd98 0xda3 0xd80 0xd33 0xd3e 0xd1e 0xc80 0xc80 0xc80>; | |
| }; | |
| qcom,rbatt-sf-lut { | |
| qcom,lut-row-legend = <0x64 0x5f 0x5a 0x55 0x50 0x4b 0x46 0x41 0x3c 0x37 0x32 0x2d 0x28 0x23 0x1e 0x19 0x14 0x0f 0x0a 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00>; | |
| qcom,lut-col-legend = <0xfffffff6 0x00 0x17 0x3c>; | |
| qcom,lut-data = <0x24a 0x11c 0x64 0x34 0x25e 0x129 0x67 0x37 0x273 0x136 0x6a 0x39 0x27d 0x142 0x6f 0x3c 0x28d 0x14e 0x75 0x3e 0x2a6 0x164 0x7f 0x40 0x2a3 0x16f 0x88 0x44 0x299 0x16a 0x94 0x4a 0x29d 0x153 0x87 0x43 0x2aa 0x14c 0x6e 0x3c 0x2bf 0x156 0x72 0x3d 0x2dd 0x169 0x79 0x41 0x2ff 0x181 0x81 0x45 0x32c 0x19c 0x8b 0x4a 0x366 0x1c0 0x90 0x40 0x3a1 0x1e8 0x89 0x40 0x3dc 0x200 0x85 0x42 0x409 0x220 0x88 0x42 0x432 0x23c 0x9b 0x45 0x44c 0x24b 0xa2 0x43 0x468 0x25c 0xa8 0x43 0x484 0x26d 0xaa 0x46 0x49b 0x273 0xac 0x4e 0x4ab 0x275 0xae 0x51 0x4c3 0x289 0xba 0x4c 0x4ed 0x2a4 0xc8 0x4a 0x526 0x2c9 0xda 0x4e 0x57c 0x30a 0xf6 0x55 0x734 0x4b9 0x196 0x85>; | |
| }; | |
| }; | |
| mmi,ed30-lishen-batterydata { | |
| qcom,flat-ocv-threshold-uv = <0x39fbc0>; | |
| qcom,rbatt-capacitive-mohm = <0x00>; | |
| qcom,v-cutoff-uv = <0x30d400>; | |
| qcom,default-rbatt-mohm = <0xdc>; | |
| qcom,batt-id-range = <0xcc90a 0xdbc29>; | |
| qcom,chg-term-ua = <0x26d18>; | |
| qcom,max-voltage-uv = <0x426030>; | |
| qcom,batt-id-kohm = <0x41>; | |
| qcom,fcc-mah = <0x80b>; | |
| qcom,fcc-temp-lut { | |
| qcom,lut-col-legend = <0xfffffff6 0x00 0x17 0x3c>; | |
| qcom,lut-data = <0x565 0x78d 0x80b 0x80f>; | |
| }; | |
| qcom,pc-temp-ocv-lut { | |
| qcom,lut-row-legend = <0x64 0x5f 0x5a 0x55 0x50 0x4b 0x46 0x41 0x3c 0x37 0x32 0x2d 0x28 0x23 0x1e 0x19 0x14 0x0f 0x0a 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00>; | |
| qcom,lut-col-legend = <0xfffffff6 0x17 0x3c>; | |
| qcom,lut-data = <0x10cc 0x10cc 0x10cc 0x10a4 0x109e 0x1092 0x1069 0x1065 0x1059 0x1033 0x102f 0x1024 0xfff 0xffb 0xff0 0xfc9 0xfcb 0xfc1 0xf93 0xf9f 0xf95 0xf65 0xf78 0xf6e 0xf3c 0xf4f 0xf44 0xf18 0xf1d 0xf15 0xefd 0xefe 0xef9 0xee7 0xee9 0xee4 0xed6 0xed8 0xed2 0xecb 0xecb 0xec3 0xec2 0xec0 0xeae 0xeb6 0xeb3 0xe96 0xea2 0xe9d 0xe83 0xe89 0xe80 0xe66 0xe71 0xe67 0xe51 0xe6e 0xe65 0xe4f 0xe6c 0xe63 0xe4c 0xe68 0xe61 0xe48 0xe61 0xe5b 0xe3f 0xe4e 0xe4a 0xe29 0xe29 0xe26 0xe01 0xdf3 0xdf2 0xdcc 0xdad 0xdab 0xd86 0xd4c 0xd45 0xd24 0xc80 0xc80 0xc80>; | |
| }; | |
| qcom,rbatt-sf-lut { | |
| qcom,lut-row-legend = <0x64 0x5f 0x5a 0x55 0x50 0x4b 0x46 0x41 0x3c 0x37 0x32 0x2d 0x28 0x23 0x1e 0x19 0x14 0x0f 0x0a 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00>; | |
| qcom,lut-col-legend = <0xfffffff6 0x17 0x3c>; | |
| qcom,lut-data = <0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64>; | |
| }; | |
| }; | |
| }; | |
| qcom,lpm-levels { | |
| qcom,default-l2-state = "l2_cache_active"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,lpm-levels"; | |
| phandle = <0x5b>; | |
| linux,phandle = <0x5b>; | |
| qcm,cpu-modes { | |
| compatible = "qcom,cpu-modes"; | |
| qcom,cpu-modes@1 { | |
| qcom,time-overhead = <0x4b0>; | |
| qcom,ss-power = <0x19a>; | |
| qcom,latency-us = <0x1f4>; | |
| qcom,mode = "standalone_pc"; | |
| qcom,energy-overhead = <0x93508>; | |
| qcom,use-broadcast-timer; | |
| }; | |
| qcom,cpu-modes@0 { | |
| qcom,time-overhead = <0x64>; | |
| qcom,ss-power = <0x212>; | |
| qcom,latency-us = <0x01>; | |
| qcom,mode = "wfi"; | |
| qcom,energy-overhead = <0xce40>; | |
| }; | |
| qcom,cpu-modes@2 { | |
| qcom,time-overhead = <0x582>; | |
| qcom,ss-power = <0x174>; | |
| qcom,latency-us = <0x226>; | |
| qcom,mode = "pc"; | |
| qcom,energy-overhead = <0xaae60>; | |
| qcom,use-broadcast-timer; | |
| }; | |
| }; | |
| qcom,system-modes { | |
| compatible = "qcom,system-modes"; | |
| qcom,system-modes@2 { | |
| qcom,time-overhead = <0x960>; | |
| qcom,l2 = "l2_cache_pc"; | |
| qcom,ss-power = <0x13b>; | |
| qcom,sync-cpus; | |
| qcom,latency-us = <0x319c>; | |
| qcom,min-cpu-mode = "pc"; | |
| qcom,energy-overhead = <0xfac4e>; | |
| }; | |
| qcom,system-modes@0 { | |
| qcom,time-overhead = <0x582>; | |
| qcom,l2 = "l2_cache_gdhs"; | |
| qcom,ss-power = <0x174>; | |
| qcom,sync-cpus; | |
| qcom,latency-us = <0x29cc>; | |
| qcom,min-cpu-mode = "pc"; | |
| qcom,energy-overhead = <0xb45be>; | |
| }; | |
| qcom,system-modes@1 { | |
| qcom,time-overhead = <0x960>; | |
| qcom,l2 = "l2_cache_pc_no_rpm"; | |
| qcom,ss-power = <0x13b>; | |
| qcom,sync-cpus; | |
| qcom,latency-us = <0x3e8>; | |
| qcom,min-cpu-mode = "standalone_pc"; | |
| qcom,energy-overhead = <0xfac4e>; | |
| }; | |
| }; | |
| }; | |
| qcom,msm-lsm-client { | |
| compatible = "qcom,msm-lsm-client"; | |
| }; | |
| qcom,mdss_mdp@fd900000 { | |
| qcom,max-bandwidth-high-kbps = <0x195460>; | |
| qcom,mdss-mixer-intf-off = <0x3200>; | |
| qcom,mdss-smp-mb-per-pipe = <0x04>; | |
| qcom,msm-bus,vectors-KBps = <0x16 0x200 0x00 0x00 0x16 0x200 0x00 0x61a800 0x16 0x200 0x00 0x61a800>; | |
| qcom,vbif-settings = <0x04 0x01 0xd8 0x707 0x124 0x03>; | |
| qcom,max-bandwidth-low-kbps = <0x195460>; | |
| qcom,msm-bus,num-cases = <0x03>; | |
| vdd-supply = <0x0f>; | |
| qcom,mdss-ctl-off = <0x600 0x700>; | |
| qcom,mdss-pipe-rgb-fetch-id = <0x07>; | |
| qcom,mdss-pipe-rgb-xin-id = <0x01>; | |
| reg-names = "mdp_phys\0vbif_phys"; | |
| interrupts = <0x00 0x48 0x00>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,max-clk-rate = <0xbebc200>; | |
| vdd-cx-supply = <0x1c>; | |
| qcom,mdss-mixer-wb-off = <0x3e00>; | |
| qcom,mdss-wb-off = <0x11100 0x13100>; | |
| qcom,mdss-pipe-dma-xin-id = <0x02>; | |
| qcom,mdss-pipe-vig-off = <0x1200>; | |
| qcom,mdss-intf-off = <0x00 0x21300>; | |
| qcom,mdss-pipe-rgb-off = <0x1e00>; | |
| qcom,mdss-pref-prim-intf = "dsi"; | |
| qcom,mdss-dspp-off = <0x4600>; | |
| qcom,mdss-pingpong-off = <0x21b00>; | |
| compatible = "qcom,mdss_mdp"; | |
| qcom,mdss-rot-block-size = <0x40>; | |
| qcom,mdss-pipe-dma-fetch-id = <0x04>; | |
| phandle = <0x1f>; | |
| qcom,mdss-pipe-vig-xin-id = <0x00>; | |
| qcom,mdp-settings = <0x2e0 0xa5 0x2e4 0x55>; | |
| reg = <0xfd900000 0x22100 0xfd924000 0x1000>; | |
| qcom,mdss-pipe-vig-fetch-id = <0x01>; | |
| qcom,msm-bus,name = "mdss_mdp"; | |
| linux,phandle = <0x1f>; | |
| qcom,mdss-smp-data = <0x07 0x1000>; | |
| qcom,mdss-pipe-dma-off = <0x2a00>; | |
| qcom,mdss_dsi_nt35521_720p_video { | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-pixel-packing = "tight"; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-panel-name = "nt35521 720p video mode dsi panel"; | |
| qcom,mdss-dsi-panel-height = <0x500>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-panel-controller = <0x1d>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-panel-timings = <0x931f1700 0x2f2e1c21 0x26030400>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-h-back-porch = <0x37>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-bl-max-level = <0xff>; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-v-front-porch = <0x0e>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-t-clk-post = <0x20>; | |
| qcom,mdss-dsi-h-front-porch = <0x2c>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x14 0x00 0x01 0x01 0x14>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 05 01 00 00 00 00 02 10 00]; | |
| qcom,mdss-dsi-t-clk-pre = <0x2d>; | |
| qcom,mdss-dsi-panel-destination = "display_1"; | |
| qcom,mdss-dsi-h-sync-pulse = <0x01>; | |
| qcom,mdss-dsi-v-back-porch = <0x0f>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-h-pulse-width = <0x0b>; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-on-command = [29 01 00 00 00 00 06 f0 55 aa 52 08 00 29 01 00 00 00 00 03 b1 68 21 23 01 00 00 00 00 02 b5 c8 29 01 00 00 00 00 02 b6 0f 29 01 00 00 00 00 05 b8 00 00 0a 00 23 01 00 00 00 00 02 b9 00 23 01 00 00 00 00 02 ba 02 29 01 00 00 00 00 03 bb 63 63 29 01 00 00 00 00 03 bc 00 00 29 01 00 00 00 00 06 bd 02 7f 0d 0b 00 29 01 00 00 00 00 11 cc 41 36 87 54 46 65 10 12 14 10 12 14 40 08 15 05 23 01 00 00 00 00 02 d0 00 29 01 00 00 00 00 11 d1 00 04 08 0c 10 14 18 1c 20 24 28 2c 30 34 38 3c 23 01 00 00 00 00 02 d3 00 29 01 00 00 00 00 03 d6 44 44 29 01 00 00 00 00 0d d7 00 00 00 00 00 00 00 00 00 00 00 00 29 01 00 00 00 00 0e d8 00 00 00 00 00 00 00 00 00 00 00 00 00 29 01 00 00 00 00 03 d9 03 06 29 01 00 00 00 00 03 e5 00 ff 29 01 00 00 00 00 05 e6 f3 ec e7 df 29 01 00 00 00 00 0b e7 f3 d9 cc cd b3 a6 99 99 99 95 29 01 00 00 00 00 0b e8 f3 d9 cc cd b3 a6 99 99 99 95 29 01 00 00 00 00 03 e9 00 04 23 01 00 00 00 00 02 ea 00 29 01 00 00 00 00 05 ee 87 78 00 00 29 01 00 00 00 00 03 ef 07 ff 29 01 00 00 00 00 06 f0 55 aa 52 08 01 29 01 00 00 00 00 03 b0 0d 0d 29 01 00 00 00 00 03 b1 0d 0d 29 01 00 00 00 00 03 b3 2d 2d 29 01 00 00 00 00 03 b4 19 19 29 01 00 00 00 00 03 b5 06 06 29 01 00 00 00 00 03 b6 05 05 29 01 00 00 00 00 03 b7 05 05 29 01 00 00 00 00 03 b8 05 05 29 01 00 00 00 00 03 b9 44 44 29 01 00 00 00 00 03 ba 36 36 29 01 00 00 00 00 03 bc 50 00 29 01 00 00 00 00 03 bd 50 00 23 01 00 00 00 00 02 be 39 23 01 00 00 00 00 02 bf 39 23 01 00 00 00 00 02 c0 0c 23 01 00 00 00 00 02 c1 00 29 01 00 00 00 00 03 c2 19 19 29 01 00 00 00 00 03 c3 0a 0a 29 01 00 00 00 00 03 c4 23 23 29 01 00 00 00 00 04 c7 00 80 00 29 01 00 00 00 00 07 c9 00 00 00 00 00 00 23 01 00 00 00 00 02 ca 01 29 01 00 00 00 00 03 cb 0b 53 23 01 00 00 00 00 02 cc 00 29 01 00 00 00 00 04 cd 0b 52 53 23 01 00 00 00 00 02 ce 44 29 01 00 00 00 00 04 cf 00 50 50 29 01 00 00 00 00 03 d0 50 50 29 01 00 00 00 00 03 d1 50 50 23 01 00 00 00 00 02 d2 39 23 01 00 00 00 00 02 d3 39 29 01 00 00 00 00 06 f0 55 aa 52 08 02 29 01 00 00 00 00 11 b0 00 ac 00 ba 00 d9 00 ed 01 01 01 1e 01 3a 01 62 29 01 00 00 00 00 11 b1 01 85 01 b8 01 e4 02 27 02 5b 02 5d 02 8c 02 be 29 01 00 00 00 00 11 b2 02 df 03 0c 03 2a 03 51 03 6d 03 8d 03 a4 03 be 29 01 00 00 00 00 05 b3 03 cc 03 cc 29 01 00 00 00 00 11 b4 00 ac 00 ba 00 d9 00 ed 01 01 01 1e 01 3a 01 62 29 01 00 00 00 00 11 b5 01 85 01 b8 01 e4 02 27 02 5b 02 5d 02 8c 02 be 29 01 00 00 00 00 11 b6 02 df 03 0c 03 2a 03 51 03 6d 03 8d 03 a4 03 be 29 01 00 00 00 00 05 b7 03 cc 03 cc 29 01 00 00 00 00 11 b8 00 ac 00 ba 00 d9 00 ed 01 01 01 1e 01 3a 01 62 29 01 00 00 00 00 11 b9 01 85 01 b8 01 e4 02 27 02 5b 02 5d 02 8c 02 be 29 01 00 00 00 00 11 ba 02 df 03 0c 03 2a 03 51 03 6d 03 8d 03 a4 03 be 29 01 00 00 00 00 05 bb 03 cc 03 cc 29 01 00 00 00 00 11 bc 00 ac 00 ba 00 d9 00 ed 01 01 01 1e 01 3a 01 62 29 01 00 00 00 00 11 bd 01 85 01 b8 01 e4 02 27 02 5b 02 5d 02 8c 02 be 29 01 00 00 00 00 11 be 02 df 03 0c 03 2a 03 51 03 6d 03 8d 03 a4 03 be 29 01 00 00 00 00 05 bf 03 cc 03 cc 29 01 00 00 00 00 11 c0 00 ac 00 ba 00 d9 00 ed 01 01 01 1e 01 3a 01 62 29 01 00 00 00 00 11 c1 01 85 01 b8 01 e4 02 27 02 5b 02 5d 02 8c 02 be 29 01 00 00 00 00 11 c2 02 df 03 0c 03 2a 03 51 03 6d 03 8d 03 a4 03 be 29 01 00 00 00 00 05 c3 03 cc 03 cc 29 01 00 00 00 00 11 c4 00 ac 00 ba 00 d9 00 ed 01 01 01 1e 01 3a 01 62 29 01 00 00 00 00 11 c5 01 85 01 b8 01 e4 02 27 02 5b 02 5d 02 8c 02 be 29 01 00 00 00 00 11 c6 02 df 03 0c 03 2a 03 51 03 6d 03 8d 03 a4 03 be 29 01 00 00 00 00 05 c7 03 cc 03 cc 23 01 00 00 00 00 02 ee 00 29 01 00 00 00 00 06 f0 55 aa 52 08 03 29 01 00 00 00 00 03 b0 00 00 29 01 00 00 00 00 03 b1 00 00 29 01 00 00 00 00 06 b2 03 00 00 00 00 29 01 00 00 00 00 06 b3 03 00 00 00 00 29 01 00 00 00 00 06 b4 03 00 00 00 00 29 01 00 00 00 00 06 b5 03 00 00 00 00 29 01 00 00 00 00 06 b6 03 00 00 00 00 29 01 00 00 00 00 06 b7 03 00 00 00 00 29 01 00 00 00 00 06 b8 03 00 00 00 00 29 01 00 00 00 00 06 b9 03 00 00 00 00 29 01 00 00 00 00 06 ba 35 10 00 00 00 29 01 00 00 00 00 06 bb 35 10 00 00 00 29 01 00 00 00 00 06 bc 35 10 00 00 00 29 01 00 00 00 00 06 bd 35 10 00 00 00 29 01 00 00 00 00 05 c0 00 34 00 00 29 01 00 00 00 00 05 c1 00 34 00 00 29 01 00 00 00 00 05 c2 00 34 00 00 29 01 00 00 00 00 05 c3 00 34 00 00 23 01 00 00 00 00 02 c4 40 23 01 00 00 00 00 02 c5 40 23 01 00 00 00 00 02 c6 40 23 01 00 00 00 00 02 c7 40 23 01 00 00 00 00 02 ef 00 29 01 00 00 00 00 06 f0 55 aa 52 08 05 29 01 00 00 00 00 03 b0 1b 10 29 01 00 00 00 00 03 b1 1b 10 29 01 00 00 00 00 03 b2 1b 10 29 01 00 00 00 00 03 b3 1b 10 29 01 00 00 00 00 03 b4 1b 10 29 01 00 00 00 00 03 b5 1b 10 29 01 00 00 00 00 03 b6 1b 10 29 01 00 00 00 00 03 b7 1b 10 23 01 00 00 00 00 02 b8 00 23 01 00 00 00 00 02 b9 00 23 01 00 00 00 00 02 ba 00 23 01 00 00 00 00 02 bb 00 23 01 00 00 00 00 02 bc 00 29 01 00 00 00 00 06 bd 03 03 03 00 01 23 01 00 00 00 00 02 c0 03 23 01 00 00 00 00 02 c1 05 23 01 00 00 00 00 02 c2 03 23 01 00 00 00 00 02 c3 05 23 01 00 00 00 00 02 c4 80 23 01 00 00 00 00 02 c5 a2 23 01 00 00 00 00 02 c6 80 23 01 00 00 00 00 02 c7 a2 29 01 00 00 00 00 03 c8 01 20 29 01 00 00 00 00 03 c9 00 20 29 01 00 00 00 00 03 ca 01 00 29 01 00 00 00 00 03 cb 00 00 29 01 00 00 00 00 04 cc 00 00 01 29 01 00 00 00 00 04 cd 00 00 01 29 01 00 00 00 00 04 ce 00 00 01 29 01 00 00 00 00 04 cf 00 00 01 23 01 00 00 00 00 02 d0 00 29 01 00 00 00 00 06 d1 03 00 00 07 10 29 01 00 00 00 00 06 d2 13 00 00 07 11 29 01 00 00 00 00 06 d3 23 00 00 07 10 29 01 00 00 00 00 06 d4 33 00 00 07 11 23 01 00 00 00 00 02 e5 06 23 01 00 00 00 00 02 e6 06 23 01 00 00 00 00 02 e7 06 23 01 00 00 00 00 02 e8 06 23 01 00 00 00 00 02 e9 06 23 01 00 00 00 00 02 ea 06 23 01 00 00 00 00 02 eb 06 23 01 00 00 00 00 02 ec 06 23 01 00 00 00 00 02 ed 31 29 01 00 00 00 00 06 f0 55 aa 52 08 06 29 01 00 00 00 00 03 b0 10 11 29 01 00 00 00 00 03 b1 12 13 29 01 00 00 00 00 03 b2 08 00 29 01 00 00 00 00 03 b3 2d 2d 29 01 00 00 00 00 03 b4 2d 34 29 01 00 00 00 00 03 b5 34 2d 29 01 00 00 00 00 03 b6 2d 34 29 01 00 00 00 00 03 b7 34 34 29 01 00 00 00 00 03 b8 02 0a 29 01 00 00 00 00 03 b9 00 08 29 01 00 00 00 00 03 ba 09 01 29 01 00 00 00 00 03 bb 0b 03 29 01 00 00 00 00 03 bc 34 34 29 01 00 00 00 00 03 bd 34 2d 29 01 00 00 00 00 03 be 2d 34 29 01 00 00 00 00 03 bf 34 2d 29 01 00 00 00 00 03 c0 2d 2d 29 01 00 00 00 00 03 c1 01 09 29 01 00 00 00 00 03 c2 19 18 29 01 00 00 00 00 03 c3 17 16 29 01 00 00 00 00 03 c4 19 18 29 01 00 00 00 00 03 c5 17 16 29 01 00 00 00 00 03 c6 01 09 29 01 00 00 00 00 03 c7 2d 2d 29 01 00 00 00 00 03 c8 2d 34 29 01 00 00 00 00 03 c9 34 2d 29 01 00 00 00 00 03 ca 2d 34 29 01 00 00 00 00 03 cb 34 34 29 01 00 00 00 00 03 cc 0b 03 29 01 00 00 00 00 03 cd 09 01 29 01 00 00 00 00 03 ce 00 08 29 01 00 00 00 00 03 cf 02 0a 29 01 00 00 00 00 03 d0 34 34 29 01 00 00 00 00 03 d1 34 2d 29 01 00 00 00 00 03 d2 2d 34 29 01 00 00 00 00 03 d3 34 2d 29 01 00 00 00 00 03 d4 2d 2d 29 01 00 00 00 00 03 d5 08 00 29 01 00 00 00 00 03 d6 10 11 29 01 00 00 00 00 03 d7 12 13 29 01 00 00 00 00 06 d8 55 55 55 55 55 29 01 00 00 00 00 06 d9 55 55 55 55 55 29 01 00 00 00 00 03 e5 34 34 29 01 00 00 00 00 03 e6 34 34 23 01 00 00 00 00 02 e7 05 29 01 00 00 00 00 06 f0 55 aa 52 00 00 05 01 00 00 00 00 02 11 00 05 01 00 00 14 00 02 29 00 29 01 00 00 00 00 06 f0 55 aa 52 08 01 29 01 00 00 00 00 06 f0 55 aa 52 00 00 29 01 00 00 00 00 02 53 2c]; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| }; | |
| qcom,mdss_dsi_jdi_1080p_video { | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-panel-name = "jdi 1080p video mode dsi panel"; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-panel-controller = <0x1d>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-panel-timings = <0xe1372500 0x676b2a3a 0x59030400>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-h-back-porch = <0x40>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-v-front-porch = <0x03>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-t-clk-post = <0x04>; | |
| qcom,mdss-dsi-h-front-porch = <0x60>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x14 0x00 0xc8 0x01 0x14>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 02 00 02 28 00 05 01 00 00 79 00 02 10 00]; | |
| qcom,mdss-dsi-t-clk-pre = <0x1b>; | |
| qcom,mdss-dsi-panel-destination = "display_1"; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-v-back-porch = <0x04>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 55 00 15 01 00 00 00 00 02 53 2c 15 01 00 00 00 00 02 35 00 05 01 00 00 78 00 02 29 00 05 01 00 00 78 00 02 11 00]; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| }; | |
| qcom,mdss_dsi_ssd2080m_720p_video { | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-pixel-packing = "tight"; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-panel-name = "ssd2080m 720p video mode dsi panel"; | |
| qcom,mdss-dsi-panel-height = <0x500>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-panel-controller = <0x1d>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-panel-timings = <0x681d1500 0x2e2d191f 0x24030400>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-h-back-porch = <0x18>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-lane-map = "lane_map_0123"; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-v-front-porch = <0x19>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-t-clk-post = <0x20>; | |
| qcom,mdss-dsi-h-front-porch = <0x50>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x14 0x00 0x02 0x01 0x14>; | |
| qcom,mdss-dsi-off-command = <0x5010000 0x32000210 0x390100 0x200002 0x53003901 0x2000 0x2c20039 0x1000000 0x2cf40 0x39010000 0x200003de 0x84003901 0x00 0x2cb2239 0x1000000 0x2c300>; | |
| qcom,mdss-dsi-t-clk-pre = <0x2f>; | |
| qcom,mdss-dsi-panel-destination = "display_1"; | |
| qcom,mdss-dsi-h-sync-pulse = <0x01>; | |
| qcom,mdss-dsi-v-back-porch = <0x0e>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-h-pulse-width = <0x0e>; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 01 29 01 00 00 00 00 02 53 00 29 01 00 00 00 00 05 c6 63 00 81 31 29 01 00 00 00 00 05 cb e7 80 73 33 29 01 00 00 00 00 02 ec d2 29 01 00 00 00 00 03 b3 04 9f 29 01 00 00 00 00 04 b2 16 26 10 29 01 00 00 00 00 02 b4 00 29 01 00 00 00 00 02 c1 04 29 01 00 00 00 00 04 c2 be 00 58 29 01 00 00 00 00 09 c3 01 22 11 21 0e 80 80 24 29 01 00 00 00 00 08 b6 09 16 42 01 13 00 00 29 01 00 00 00 00 04 b7 24 26 43 29 01 00 00 00 00 06 b8 16 08 25 44 08 29 01 00 00 00 00 09 b9 06 08 07 09 00 00 00 00 29 01 00 00 00 00 09 ba 0e 10 0a 0c 16 05 00 00 29 01 00 00 00 00 09 bb a1 a1 a1 a1 00 00 00 00 29 01 00 00 00 00 09 bc 0f 11 0b 0d 16 05 00 00 29 01 00 00 00 00 09 bd a1 a1 a1 a1 00 00 00 00 29 01 00 00 00 00 04 e6 ff ff 0f 29 01 00 00 00 00 02 c7 3f 29 01 00 00 00 00 07 b5 47 00 00 08 00 01 29 01 00 00 00 00 08 c4 df c2 0c 0c 63 e3 99 29 01 00 00 00 00 07 d0 0a 00 06 09 10 20 29 01 00 00 00 00 06 d1 1d 32 1b 00 00 29 01 00 00 00 00 07 d2 0a 00 06 09 10 20 29 01 00 00 00 00 06 d3 1d 32 1b 00 00 29 01 00 00 00 00 07 d4 0a 00 06 09 10 20 29 01 00 00 00 00 06 d5 1d 32 1b 00 00 29 01 00 00 00 00 07 d6 0a 00 06 09 10 20 29 01 00 00 00 00 06 d7 1d 32 1b 00 00 29 01 00 00 00 00 07 d8 0a 00 06 09 10 20 29 01 00 00 00 00 06 d9 1d 32 1b 00 00 29 01 00 00 00 00 07 da 0a 00 06 09 10 20 29 01 00 00 00 00 06 db 1d 32 1b 00 00 29 01 00 00 00 00 03 cc 10 00 29 01 00 00 00 00 04 ce 4e 55 a5 29 01 00 00 00 00 04 e0 01 02 02 29 01 00 00 00 00 05 f6 00 00 00 00 29 01 00 00 00 00 05 f7 00 00 00 00 29 01 00 00 00 00 03 e1 90 00 29 01 00 00 00 00 07 de 95 cf e2 ce 11 15 29 01 00 00 00 00 02 cf 46 29 01 00 00 00 00 02 c5 66 29 01 00 00 00 00 03 ed 00 20 15 01 00 00 00 00 02 53 2c 05 01 00 00 20 00 02 11 00 05 01 00 00 20 00 02 29 00]; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| }; | |
| qcom,mdss_dsi_mot_lgd_720p_video_v0 { | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-panel-name = "mipi_mot_video_lgd_hd_450 v0"; | |
| qcom,mdss-dsi-panel-height = <0x500>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-panel-controller = <0x1d>; | |
| qcom,panel-dis-reset-sequence = <0x00 0x02>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-panel-timings = <0xe33e3400 0x55523340 0x29030400>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-pan-physical-width-dimension = <0x38>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,cont-splash-enabled; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-cont-splash-skip-ov-handoff; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-panel-clockrate = <0x2f8a6900>; | |
| qcom,mdss-dsi-h-back-porch = <0x60>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; | |
| status = "ok"; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-pan-physical-height-dimension = <0x63>; | |
| mmi,panel_name = "mipi_mot_video_lgd_hd_450"; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-v-front-porch = <0x43e>; | |
| mmi,panel_ver_min = <0x00 0x00>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-t-clk-post = <0x1e>; | |
| qcom,panel-en-reset-sequence = <0x01 0x0b>; | |
| qcom,mdss-dsi-h-front-porch = <0x60>; | |
| compatible = "qcom,mdss-dsi-panel"; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 01 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-t-clk-pre = <0x34>; | |
| qcom,mdss-dsi-panel-destination = "display_1"; | |
| qcom,mdss-dsi-h-sync-pulse = <0x01>; | |
| qcom,mdss-dsi-v-back-porch = <0x32>; | |
| mmi,panel_ver_max = <0xffffffff 0xffffffff>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-hs-cmds-post-init; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,panel-esd-power-mode-chk = <0x1c>; | |
| qcom,mdss-dsi-on-command = [29 01 00 00 78 00 02 11 00 29 01 00 00 00 00 02 b0 ac 29 01 00 00 00 00 06 b5 47 00 80 ff ff 29 01 00 00 00 00 02 51 ff 29 01 00 00 00 00 02 53 2c 29 01 00 00 00 00 02 55 00 29 01 00 00 00 00 02 29 00]; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,platform-supply-entry1 { | |
| qcom,supply-pre-off-sleep = <0x00>; | |
| qcom,supply-enable-load = <0x186a0>; | |
| qcom,supply-post-on-sleep = <0x00>; | |
| qcom,supply-min-voltage = <0x2f4d60>; | |
| qcom,supply-max-voltage = <0x2f4d60>; | |
| qcom,supply-post-off-sleep = <0x00>; | |
| qcom,supply-name = "vdd_disp"; | |
| qcom,supply-pre-on-sleep = <0x00>; | |
| qcom,supply-disable-load = <0x64>; | |
| }; | |
| qcom,platform-supply-entry2 { | |
| qcom,supply-pre-off-sleep = <0x00>; | |
| qcom,supply-enable-load = <0x186a0>; | |
| qcom,supply-post-on-sleep = <0x02>; | |
| qcom,supply-min-voltage = <0x1b7740>; | |
| qcom,supply-max-voltage = <0x1b7740>; | |
| qcom,supply-post-off-sleep = <0x02>; | |
| qcom,supply-name = "vddio_disp"; | |
| qcom,supply-pre-on-sleep = <0x00>; | |
| qcom,supply-disable-load = <0x64>; | |
| }; | |
| qcom,platform-supply-entry3 { | |
| qcom,supply-pre-off-sleep = <0x00>; | |
| qcom,supply-enable-load = <0x186a0>; | |
| qcom,supply-post-on-sleep = <0x0b>; | |
| qcom,supply-min-voltage = <0x5265c0>; | |
| qcom,supply-max-voltage = <0x5265c0>; | |
| qcom,supply-post-off-sleep = <0x02>; | |
| qcom,supply-name = "lcdbias"; | |
| qcom,supply-pre-on-sleep = <0x00>; | |
| qcom,supply-disable-load = <0x64>; | |
| }; | |
| }; | |
| qcom,mdss_dsi_nt35596_1080p_video { | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-panel-name = "nt35596 1080p video mode dsi panel"; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-panel-controller = <0x1d>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-panel-timings = <0xf93d3400 0x584d363f 0x53030400>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-h-back-porch = <0x20>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-v-front-porch = <0x02>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-t-clk-post = <0x1e>; | |
| qcom,mdss-dsi-h-front-porch = <0x20>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x14 0x00 0x01 0x01 0x14>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-t-clk-pre = <0x38>; | |
| qcom,mdss-dsi-panel-destination = "display_1"; | |
| qcom,mdss-dsi-h-sync-pulse = <0x01>; | |
| qcom,mdss-dsi-v-back-porch = <0x12>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-h-pulse-width = <0x08>; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-on-command = <0x29010000 0x2ff 0xee290100 0x02 0xfb012901 0x00 0x21f4529 0x1000000 0x2244f 0x29010000 0x238 0xc8290100 0x02 0x392c2901 0x00 0x21ebb29 0x1000000 0x21d0f 0x29010000 0x27e 0xb1290100 0x02 0xff002901 0x00 0x2fb0129 0x1000000 0x23501 0x29010000 0x2ba 0x3290100 0x02 0xff012901 0x00 0x2fb0129 0x1000000 0x20001 0x29010000 0x201 0x55290100 0x02 0x2402901 0x00 0x2050029 0x1000000 0x2061b 0x29010000 0x207 0x24290100 0x02 0x80c2901 0x00 0x20b8729 0x1000000 0x20c87 0x29010000 0x20e 0xb0290100 0x02 0xfb32901 0x00 0x2111029 0x1000000 0x21210 0x29010000 0x213 0x5290100 0x02 0x144a2901 0x00 0x2151829 0x1000000 0x21618 0x29010000 0x218 0x290100 0x02 0x19772901 0x00 0x21a5529 0x1000000 0x21b13 0x29010000 0x21c 0x290100 0x02 0x1d002901 0x00 0x21e1329 0x1000000 0x21f00 0x29010000 0x223 0x290100 0x02 0x24002901 0x00 0x2250029 0x1000000 0x22600 0x29010000 0x227 0x290100 0x02 0x28002901 0x00 0x2350029 0x1000000 0x26600 0x29010000 0x258 0x82290100 0x02 0x59022901 0x00 0x25a0229 0x1000000 0x25b02 0x29010000 0x25c 0x82290100 0x02 0x5d822901 0x00 0x25e0229 0x1000000 0x25f02 0x29010000 0x272 0x31290100 0x02 0xff052901 0x00 0x2fb0129 0x1000000 0x20001 0x29010000 0x201 0xb290100 0x02 0x20c2901 0x00 0x2030929 0x1000000 0x2040a 0x29010000 0x205 0x290100 0x02 0x60f2901 0x00 0x2071029 0x1000000 0x20800 0x29010000 0x209 0x290100 0x02 0xa002901 0x00 0x20b0029 0x1000000 0x20c00 0x29010000 0x20d 0x13290100 0x02 0xe152901 0x00 0x20f1729 0x1000000 0x21001 0x29010000 0x211 0xb290100 0x02 0x120c2901 0x00 0x2130929 0x1000000 0x2140a 0x29010000 0x215 0x290100 0x02 0x160f2901 0x00 0x2171029 0x1000000 0x21800 0x29010000 0x219 0x290100 0x02 0x1a002901 0x00 0x21b0029 0x1000000 0x21c00 0x29010000 0x21d 0x13290100 0x02 0x1e152901 0x00 0x21f1729 0x1000000 0x22000 0x29010000 0x221 0x3290100 0x02 0x22012901 0x00 0x2234029 0x1000000 0x22440 0x29010000 0x225 0xed290100 0x02 0x29582901 0x00 0x22a1229 0x1000000 0x22b01 0x29010000 0x24b 0x6290100 0x02 0x4c112901 0x00 0x24d2029 0x1000000 0x24e02 0x29010000 0x24f 0x2290100 0x02 0x50202901 0x00 0x2516129 0x1000000 0x25201 0x29010000 0x253 0x63290100 0x02 0x54772901 0x00 0x255ed29 0x1000000 0x25b00 0x29010000 0x25c 0x290100 0x02 0x5d002901 0x00 0x25e0029 0x1000000 0x25f15 0x29010000 0x260 0x75290100 0x02 0x61002901 0x00 0x2620029 0x1000000 0x26300 0x29010000 0x264 0x290100 0x02 0x65002901 0x00 0x2660029 0x1000000 0x26700 0x29010000 0x268 0x4290100 0x02 0x69002901 0x00 0x26a0029 0x1000000 0x26c40 0x29010000 0x275 0x1290100 0x02 0x76012901 0x00 0x27a8029 0x1000000 0x27bc5 0x29010000 0x27c 0xd8290100 0x02 0x7d602901 0x00 0x27f1029 0x1000000 0x28081 0x29010000 0x283 0x5290100 0x02 0x93082901 0x00 0x2941029 0x1000000 0x28a00 0x29010000 0x29b 0xf290100 0x02 0xeaff2901 0x00 0x2ec0029 0x1000000 0x2ff01 0x29010000 0x2fb 0x1290100 0x02 0x75002901 0x00 0x2768e29 0x1000000 0x27700 0x29010000 0x278 0x90290100 0x02 0x79002901 0x00 0x27ab229 0x1000000 0x27b00 0x29010000 0x27c 0xc7290100 0x02 0x7d002901 0x00 0x27ed729 0x1000000 0x27f00 0x29010000 0x280 0xe9290100 0x02 0x81002901 0x00 0x282f929 0x1000000 0x28301 0x29010000 0x284 0x1290100 0x02 0x85012901 0x00 0x2860b29 0x1000000 0x28701 0x29010000 0x288 0x3a290100 0x02 0x89012901 0x00 0x28a5d29 0x1000000 0x28b01 0x29010000 0x28c 0x94290100 0x02 0x8d012901 0x00 0x28ebc29 0x1000000 0x28f02 0x29010000 0x290 0x290100 0x02 0x91022901 0x00 0x2923929 0x1000000 0x29302 0x29010000 0x294 0x3a290100 0x02 0x95022901 0x00 0x2966b29 0x1000000 0x29702 0x29010000 0x298 0xa2290100 0x02 0x99022901 0x00 0x29ac729 0x1000000 0x29b02 0x29010000 0x29c 0xfb290100 0x02 0x9d032901 0x00 0x29e2029 0x1000000 0x29f03 0x29010000 0x2a0 0x54290100 0x02 0xa2032901 0x00 0x2a36d29 0x1000000 0x2a403 0x29010000 0x2a5 0x80290100 0x02 0xa6032901 0x00 0x2a78129 0x1000000 0x2a903 0x29010000 0x2aa 0xc7290100 0x02 0xab032901 0x00 0x2acf029 0x1000000 0x2ad03 0x29010000 0x2ae 0xf8290100 0x02 0xaf032901 0x00 0x2b0fd29 0x1000000 0x2b103 0x29010000 0x2b2 0xfe290100 0x02 0xb3002901 0x00 0x2b48e29 0x1000000 0x2b500 0x29010000 0x2b6 0x90290100 0x02 0xb7002901 0x00 0x2b8b229 0x1000000 0x2b900 0x29010000 0x2ba 0xc7290100 0x02 0xbb002901 0x00 0x2bcd729 0x1000000 0x2bd00 0x29010000 0x2be 0xe9290100 0x02 0xbf002901 0x00 0x2c0f929 0x1000000 0x2c101 0x29010000 0x2c2 0x1290100 0x02 0xc3012901 0x00 0x2c40b29 0x1000000 0x2c501 0x29010000 0x2c6 0x3a290100 0x02 0xc7012901 0x00 0x2c85d29 0x1000000 0x2c901 0x29010000 0x2ca 0x94290100 0x02 0xcb012901 0x00 0x2ccbc29 0x1000000 0x2cd02 0x29010000 0x2ce 0x290100 0x02 0xcf022901 0x00 0x2d03929 0x1000000 0x2d102 0x29010000 0x2d2 0x3a290100 0x02 0xd3022901 0x00 0x2d46b29 0x1000000 0x2d502 0x29010000 0x2d6 0xa2290100 0x02 0xd7022901 0x00 0x2d8c729 0x1000000 0x2d902 0x29010000 0x2da 0xfb290100 0x02 0xdb032901 0x00 0x2dc2029 0x1000000 0x2dd03 0x29010000 0x2de 0x54290100 0x02 0xdf032901 0x00 0x2e06d29 0x1000000 0x2e103 0x29010000 0x2e2 0x80290100 0x02 0xe3032901 0x00 0x2e48129 0x1000000 0x2e503 0x29010000 0x2e6 0xc7290100 0x02 0xe7032901 0x00 0x2e8f029 0x1000000 0x2e903 0x29010000 0x2ea 0xf8290100 0x02 0xeb032901 0x00 0x2ecfd29 0x1000000 0x2ed03 0x29010000 0x2ee 0xfe290100 0x02 0xef002901 0x00 0x2f00329 0x1000000 0x2f100 0x29010000 0x2f2 0xb290100 0x02 0xf3002901 0x00 0x2f40d29 0x1000000 0x2f500 0x29010000 0x2f6 0x4a290100 0x02 0xf7002901 0x00 0x2f87129 0x1000000 0x2f900 0x29010000 0x2fa 0x8c290100 0x02 0xff022901 0x00 0x2fb0129 0x1000000 0x20000 0x29010000 0x201 0xa1290100 0x02 0x2002901 0x00 0x203b629 0x1000000 0x20400 0x29010000 0x205 0xc9290100 0x02 0x6002901 0x00 0x207fd29 0x1000000 0x20801 0x29010000 0x209 0x29290100 0x02 0xa012901 0x00 0x20b6b29 0x1000000 0x20c01 0x29010000 0x20d 0x9e290100 0x02 0xe012901 0x00 0x20feb29 0x1000000 0x21002 0x29010000 0x211 0x25290100 0x02 0x12022901 0x00 0x2132729 0x1000000 0x21402 0x29010000 0x215 0x5c290100 0x02 0x16022901 0x00 0x2179529 0x1000000 0x21802 0x29010000 0x219 0xba290100 0x02 0x1a022901 0x00 0x21bec29 0x1000000 0x21c03 0x29010000 0x21d 0xc290100 0x02 0x1e032901 0x00 0x21f3429 0x1000000 0x22003 0x29010000 0x221 0x3f290100 0x02 0x22032901 0x00 0x2234829 0x1000000 0x22403 0x29010000 0x225 0x49290100 0x02 0x26032901 0x00 0x2276b29 0x1000000 0x22803 0x29010000 0x229 0x7e290100 0x02 0x2a032901 0x00 0x22b8f29 0x1000000 0x22d03 0x29010000 0x22f 0x9e290100 0x02 0x30032901 0x00 0x231a029 0x1000000 0x23200 0x29010000 0x233 0x3290100 0x02 0x34002901 0x00 0x2350b29 0x1000000 0x23600 0x29010000 0x237 0xd290100 0x02 0x38002901 0x00 0x2394a29 0x1000000 0x23a00 0x29010000 0x23b 0x71290100 0x02 0x3d002901 0x00 0x23f8c29 0x1000000 0x24000 0x29010000 0x241 0xa1290100 0x02 0x42002901 0x00 0x243b629 0x1000000 0x24400 0x29010000 0x245 0xc9290100 0x02 0x46002901 0x00 0x247fd29 0x1000000 0x24801 0x29010000 0x249 0x29290100 0x02 0x4a012901 0x00 0x24b6b29 0x1000000 0x24c01 0x29010000 0x24d 0x9e290100 0x02 0x4e012901 0x00 0x24feb29 0x1000000 0x25002 0x29010000 0x251 0x25290100 0x02 0x52022901 0x00 0x2532729 0x1000000 0x25402 0x29010000 0x255 0x5c290100 0x02 0x56022901 0x00 0x2589529 0x1000000 0x25902 0x29010000 0x25a 0xba290100 0x02 0x5b022901 0x00 0x25cec29 0x1000000 0x25d03 0x29010000 0x25e 0xc290100 0x02 0x5f032901 0x00 0x2603429 0x1000000 0x26103 0x29010000 0x262 0x3f290100 0x02 0x63032901 0x00 0x2644829 0x1000000 0x26503 0x29010000 0x266 0x49290100 0x02 0x67032901 0x00 0x2686b29 0x1000000 0x26903 0x29010000 0x26a 0x7e290100 0x02 0x6b032901 0x00 0x26c8f29 0x1000000 0x26d03 0x29010000 0x26e 0x9e290100 0x02 0x6f032901 0x00 0x270a029 0x1000000 0x27100 0x29010000 0x272 0xfb290100 0x02 0x73002901 0x00 0x274fd29 0x1000000 0x27501 0x29010000 0x276 0x5290100 0x02 0x77012901 0x00 0x2780d29 0x1000000 0x27901 0x29010000 0x27a 0x17290100 0x02 0x7b012901 0x00 0x27c1f29 0x1000000 0x27d01 0x29010000 0x27e 0x28290100 0x02 0x7f012901 0x00 0x2803229 0x1000000 0x28101 0x29010000 0x282 0x38290100 0x02 0x83012901 0x00 0x2845329 0x1000000 0x28501 0x29010000 0x286 0x72290100 0x02 0x87012901 0x00 0x2889b29 0x1000000 0x28901 0x29010000 0x28a 0xc3290100 0x02 0x8b022901 0x00 0x28c0129 0x1000000 0x28d02 0x29010000 0x28e 0x36290100 0x02 0x8f022901 0x00 0x2903729 0x1000000 0x29102 0x29010000 0x292 0x69290100 0x02 0x93022901 0x00 0x294a129 0x1000000 0x29502 0x29010000 0x296 0xc8290100 0x02 0x97022901 0x00 0x298ff29 0x1000000 0x29903 0x29010000 0x29a 0x26290100 0x02 0x9b032901 0x00 0x29c6929 0x1000000 0x29d03 0x29010000 0x29e 0x88290100 0x02 0x9f032901 0x00 0x2a0f829 0x1000000 0x2a203 0x29010000 0x2a3 0xf9290100 0x02 0xa4032901 0x00 0x2a5fe29 0x1000000 0x2a603 0x29010000 0x2a7 0xfe290100 0x02 0xa9032901 0x00 0x2aafe29 0x1000000 0x2ab03 0x29010000 0x2ac 0xfe290100 0x02 0xad032901 0x00 0x2aefe29 0x1000000 0x2af00 0x29010000 0x2b0 0xfb290100 0x02 0xb1002901 0x00 0x2b2fd29 0x1000000 0x2b301 0x29010000 0x2b4 0x5290100 0x02 0xb5012901 0x00 0x2b60d29 0x1000000 0x2b701 0x29010000 0x2b8 0x17290100 0x02 0xb9012901 0x00 0x2ba1f29 0x1000000 0x2bb01 0x29010000 0x2bc 0x28290100 0x02 0xbd012901 0x00 0x2be3229 0x1000000 0x2bf01 0x29010000 0x2c0 0x38290100 0x02 0xc1012901 0x00 0x2c25329 0x1000000 0x2c301 0x29010000 0x2c4 0x72290100 0x02 0xc5012901 0x00 0x2c69b29 0x1000000 0x2c701 0x29010000 0x2c8 0xc3290100 0x02 0xc9022901 0x00 0x2ca0129 0x1000000 0x2cb02 0x29010000 0x2cc 0x36290100 0x02 0xcd022901 0x00 0x2ce3729 0x1000000 0x2cf02 0x29010000 0x2d0 0x69290100 0x02 0xd1022901 0x00 0x2d2a129 0x1000000 0x2d302 0x29010000 0x2d4 0xc8290100 0x02 0xd5022901 0x00 0x2d6ff29 0x1000000 0x2d703 0x29010000 0x2d8 0x26290100 0x02 0xd9032901 0x00 0x2da6929 0x1000000 0x2db03 0x29010000 0x2dc 0x88290100 0x02 0xdd032901 0x00 0x2def829 0x1000000 0x2df03 0x29010000 0x2e0 0xf9290100 0x02 0xe1032901 0x00 0x2e2fe29 0x1000000 0x2e303 0x29010000 0x2e4 0xfe290100 0x02 0xe5032901 0x00 0x2e6fe29 0x1000000 0x2e703 0x29010000 0x2e8 0xfe290100 0x02 0xe9032901 0x00 0x2eafe29 0x1000000 0x2ff01 0x29010000 0x2fb 0x1290100 0x02 0xff022901 0x00 0x2fb0129 0x1000000 0x2ff04 0x29010000 0x2fb 0x1290100 0x02 0xff002901 0x00 0x2d31429 0x1000000 0x2d414 0x29010000 0x96000211 0x290100 0x02 0xff002901 0x00 0x2350029 0x1000078 0x22900>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| }; | |
| qcom,mdss_dsi_nt35590_720p_cmd { | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-panel-name = "nt35590 720p command mode dsi panel"; | |
| qcom,mdss-dsi-panel-height = <0x500>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-panel-controller = <0x1d>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-panel-timings = <0x7d251d00 0x37332227 0x1e030400>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-pan-physical-width-dimension = <0x3b>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-h-back-porch = <0xa4>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-pan-physical-height-dimension = <0x68>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-v-front-porch = <0x06>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-t-clk-post = <0x20>; | |
| qcom,mdss-dsi-h-front-porch = <0x8c>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x14 0x00 0x01 0x01 0x14>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-t-clk-pre = <0x2c>; | |
| qcom,mdss-dsi-panel-destination = "display_1"; | |
| qcom,mdss-dsi-h-sync-pulse = <0x01>; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| qcom,mdss-dsi-v-back-porch = <0x01>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x08>; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-on-command = <0x29010000 0x2ff 0xee290100 0x02 0x26082901 0x00 0x2260029 0x1000010 0x2ff00 0x29010000 0x2ba 0x3290100 0x02 0xc2082901 0x00 0x2ff0129 0x1000000 0x2fb01 0x29010000 0x200 0x4a290100 0x02 0x1332901 0x00 0x2025329 0x1000000 0x20355 0x29010000 0x204 0x55290100 0x02 0x5332901 0x00 0x2062229 0x1000000 0x20856 0x29010000 0x209 0x8f290100 0x02 0x36732901 0x00 0x20b9f29 0x1000000 0x20c9f 0x29010000 0x20d 0x2f290100 0x02 0xe242901 0x00 0x2118329 0x1000000 0x21203 0x29010000 0x271 0x2c290100 0x02 0x6f032901 0x00 0x20f0a29 0x1000000 0x2ff05 0x29010000 0x2fb 0x1290100 0x02 0x1002901 0x00 0x2028b29 0x1000000 0x20382 0x29010000 0x204 0x82290100 0x02 0x5302901 0x00 0x2063329 0x1000000 0x20701 0x29010000 0x208 0x290100 0x02 0x9462901 0x00 0x20a4629 0x1000000 0x20d0b 0x29010000 0x20e 0x1d290100 0x02 0xf082901 0x00 0x2105329 0x1000000 0x21100 0x29010000 0x212 0x290100 0x02 0x14012901 0x00 0x2150029 0x1000000 0x21605 0x29010000 0x217 0x290100 0x02 0x197f2901 0x00 0x21aff29 0x1000000 0x21b0f 0x29010000 0x21c 0x290100 0x02 0x1d002901 0x00 0x21e0029 0x1000000 0x21f07 0x29010000 0x220 0x290100 0x02 0x21062901 0x00 0x2225529 0x1000000 0x2234d 0x29010000 0x22d 0x2290100 0x02 0x28012901 0x00 0x22f0229 0x1000000 0x28301 0x29010000 0x29e 0x58290100 0x02 0x9f6a2901 0x00 0x2a00129 0x1000000 0x2a210 0x29010000 0x2bb 0xa290100 0x02 0xbc0a2901 0x00 0x2320829 0x1000000 0x233b8 0x29010000 0x236 0x1290100 0x02 0x37002901 0x00 0x2430029 0x1000000 0x24b21 0x29010000 0x24c 0x3290100 0x02 0x50212901 0x00 0x2510329 0x1000000 0x25821 0x29010000 0x259 0x3290100 0x02 0x5d212901 0x00 0x25e0329 0x1000000 0x26c00 0x29010000 0x26d 0x290100 0x02 0xfb012901 0x00 0x2ff0129 0x1000000 0x2fb01 0x29010000 0x275 0x290100 0x02 0x767d2901 0x00 0x2770029 0x1000000 0x2788a 0x29010000 0x279 0x290100 0x02 0x7a9c2901 0x00 0x27b0029 0x1000000 0x27cb1 0x29010000 0x27d 0x290100 0x02 0x7ebf2901 0x00 0x27f0029 0x1000000 0x280cf 0x29010000 0x281 0x290100 0x02 0x82dd2901 0x00 0x2830029 0x1000000 0x284e8 0x29010000 0x285 0x290100 0x02 0x86f22901 0x00 0x2870129 0x1000000 0x2881f 0x29010000 0x289 0x1290100 0x02 0x8a412901 0x00 0x28b0129 0x1000000 0x28c78 0x29010000 0x28d 0x1290100 0x02 0x8ea52901 0x00 0x28f0129 0x1000000 0x290ee 0x29010000 0x291 0x2290100 0x02 0x92292901 0x00 0x2930229 0x1000000 0x2942a 0x29010000 0x295 0x2290100 0x02 0x965d2901 0x00 0x2970229 0x1000000 0x29893 0x29010000 0x299 0x2290100 0x02 0x9ab82901 0x00 0x29b0229 0x1000000 0x29ce7 0x29010000 0x29d 0x3290100 0x02 0x9e072901 0x00 0x29f0329 0x1000000 0x2a037 0x29010000 0x2a2 0x3290100 0x02 0xa3462901 0x00 0x2a40329 0x1000000 0x2a556 0x29010000 0x2a6 0x3290100 0x02 0xa7662901 0x00 0x2a90329 0x1000000 0x2aa7a 0x29010000 0x2ab 0x3290100 0x02 0xac932901 0x00 0x2ad0329 0x1000000 0x2aea3 0x29010000 0x2af 0x3290100 0x02 0xb0b42901 0x00 0x2b10329 0x1000000 0x2b2cb 0x29010000 0x2b3 0x290100 0x02 0xb47d2901 0x00 0x2b50029 0x1000000 0x2b68a 0x29010000 0x2b7 0x290100 0x02 0xb89c2901 0x00 0x2b90029 0x1000000 0x2bab1 0x29010000 0x2bb 0x290100 0x02 0xbcbf2901 0x00 0x2bd0029 0x1000000 0x2becf 0x29010000 0x2bf 0x290100 0x02 0xc0dd2901 0x00 0x2c10029 0x1000000 0x2c2e8 0x29010000 0x2c3 0x290100 0x02 0xc4f22901 0x00 0x2c50129 0x1000000 0x2c61f 0x29010000 0x2c7 0x1290100 0x02 0xc8412901 0x00 0x2c90129 0x1000000 0x2ca78 0x29010000 0x2cb 0x1290100 0x02 0xcca52901 0x00 0x2cd0129 0x1000000 0x2ceee 0x29010000 0x2cf 0x2290100 0x02 0xd0292901 0x00 0x2d10229 0x1000000 0x2d22a 0x29010000 0x2d3 0x2290100 0x02 0xd45d2901 0x00 0x2d50229 0x1000000 0x2d693 0x29010000 0x2d7 0x2290100 0x02 0xd8b82901 0x00 0x2d90229 0x1000000 0x2dae7 0x29010000 0x2db 0x3290100 0x02 0xdc072901 0x00 0x2dd0329 0x1000000 0x2de37 0x29010000 0x2df 0x3290100 0x02 0xe0462901 0x00 0x2e10329 0x1000000 0x2e256 0x29010000 0x2e3 0x3290100 0x02 0xe4662901 0x00 0x2e50329 0x1000000 0x2e67a 0x29010000 0x2e7 0x3290100 0x02 0xe8932901 0x00 0x2e90329 0x1000000 0x2eaa3 0x29010000 0x2eb 0x3290100 0x02 0xecb42901 0x00 0x2ed0329 0x1000000 0x2eecb 0x29010000 0x2ef 0x290100 0x02 0xf0ed2901 0x00 0x2f10029 0x1000000 0x2f2f3 0x29010000 0x2f3 0x290100 0x02 0xf4fe2901 0x00 0x2f50129 0x1000000 0x2f609 0x29010000 0x2f7 0x1290100 0x02 0xf8132901 0x00 0x2f90129 0x1000000 0x2fa1d 0x29010000 0x2ff 0x2290100 0x02 0xfb012901 0x00 0x2000129 0x1000000 0x20126 0x29010000 0x202 0x1290100 0x02 0x32f2901 0x00 0x2040129 0x1000000 0x20537 0x29010000 0x206 0x1290100 0x02 0x7562901 0x00 0x2080129 0x1000000 0x20970 0x29010000 0x20a 0x1290100 0x02 0xb9d2901 0x00 0x20c0129 0x1000000 0x20dc2 0x29010000 0x20e 0x1290100 0x02 0xfff2901 0x00 0x2100229 0x1000000 0x21131 0x29010000 0x212 0x2290100 0x02 0x13322901 0x00 0x2140229 0x1000000 0x21560 0x29010000 0x216 0x2290100 0x02 0x17942901 0x00 0x2180229 0x1000000 0x219b5 0x29010000 0x21a 0x2290100 0x02 0x1be32901 0x00 0x21c0329 0x1000000 0x21d03 0x29010000 0x21e 0x3290100 0x02 0x1f2d2901 0x00 0x2200329 0x1000000 0x2213a 0x29010000 0x222 0x3290100 0x02 0x23482901 0x00 0x2240329 0x1000000 0x22557 0x29010000 0x226 0x3290100 0x02 0x27682901 0x00 0x2280329 0x1000000 0x2297b 0x29010000 0x22a 0x3290100 0x02 0x2b902901 0x00 0x22d0329 0x1000000 0x22fa0 0x29010000 0x230 0x3290100 0x02 0x31cb2901 0x00 0x2320029 0x1000000 0x233ed 0x29010000 0x234 0x290100 0x02 0x35f32901 0x00 0x2360029 0x1000000 0x237fe 0x29010000 0x238 0x1290100 0x02 0x39092901 0x00 0x23a0129 0x1000000 0x23b13 0x29010000 0x23d 0x1290100 0x02 0x3f1d2901 0x00 0x2400129 0x1000000 0x24126 0x29010000 0x242 0x1290100 0x02 0x432f2901 0x00 0x2440129 0x1000000 0x24537 0x29010000 0x246 0x1290100 0x02 0x47562901 0x00 0x2480129 0x1000000 0x24970 0x29010000 0x24a 0x1290100 0x02 0x4b9d2901 0x00 0x24c0129 0x1000000 0x24dc2 0x29010000 0x24e 0x1290100 0x02 0x4fff2901 0x00 0x2500229 0x1000000 0x25131 0x29010000 0x252 0x2290100 0x02 0x53322901 0x00 0x2540229 0x1000000 0x25560 0x29010000 0x256 0x2290100 0x02 0x58942901 0x00 0x2590229 0x1000000 0x25ab5 0x29010000 0x25b 0x2290100 0x02 0x5ce32901 0x00 0x25d0329 0x1000000 0x25e03 0x29010000 0x25f 0x3290100 0x02 0x602d2901 0x00 0x2610329 0x1000000 0x2623a 0x29010000 0x263 0x3290100 0x02 0x64482901 0x00 0x2650329 0x1000000 0x26657 0x29010000 0x267 0x3290100 0x02 0x68682901 0x00 0x2690329 0x1000000 0x26a7b 0x29010000 0x26b 0x3290100 0x02 0x6c902901 0x00 0x26d0329 0x1000000 0x26ea0 0x29010000 0x26f 0x3290100 0x02 0x70cb2901 0x00 0x2710029 0x1000000 0x27219 0x29010000 0x273 0x290100 0x02 0x74362901 0x00 0x2750029 0x1000000 0x27655 0x29010000 0x277 0x290100 0x02 0x78702901 0x00 0x2790029 0x1000000 0x27a83 0x29010000 0x27b 0x290100 0x02 0x7c992901 0x00 0x27d0029 0x1000000 0x27ea8 0x29010000 0x27f 0x290100 0x02 0x80b72901 0x00 0x2810029 0x1000000 0x282c5 0x29010000 0x283 0x290100 0x02 0x84f72901 0x00 0x2850129 0x1000000 0x2861e 0x29010000 0x287 0x1290100 0x02 0x88602901 0x00 0x2890129 0x1000000 0x28a95 0x29010000 0x28b 0x1290100 0x02 0x8ce12901 0x00 0x28d0229 0x1000000 0x28e20 0x29010000 0x28f 0x2290100 0x02 0x90232901 0x00 0x2910229 0x1000000 0x29259 0x29010000 0x293 0x2290100 0x02 0x94942901 0x00 0x2950229 0x1000000 0x296b4 0x29010000 0x297 0x2290100 0x02 0x98e12901 0x00 0x2990329 0x1000000 0x29a01 0x29010000 0x29b 0x3290100 0x02 0x9c282901 0x00 0x29d0329 0x1000000 0x29e30 0x29010000 0x29f 0x3290100 0x02 0xa0372901 0x00 0x2a20329 0x1000000 0x2a33b 0x29010000 0x2a4 0x3290100 0x02 0xa5402901 0x00 0x2a60329 0x1000000 0x2a750 0x29010000 0x2a9 0x3290100 0x02 0xaa6d2901 0x00 0x2ab0329 0x1000000 0x2ac80 0x29010000 0x2ad 0x3290100 0x02 0xaecb2901 0x00 0x2af0029 0x1000000 0x2b019 0x29010000 0x2b1 0x290100 0x02 0xb2362901 0x00 0x2b30029 0x1000000 0x2b455 0x29010000 0x2b5 0x290100 0x02 0xb6702901 0x00 0x2b70029 0x1000000 0x2b883 0x29010000 0x2b9 0x290100 0x02 0xba992901 0x00 0x2bb0029 0x1000000 0x2bca8 0x29010000 0x2bd 0x290100 0x02 0xbeb72901 0x00 0x2bf0029 0x1000000 0x2c0c5 0x29010000 0x2c1 0x290100 0x02 0xc2f72901 0x00 0x2c30129 0x1000000 0x2c41e 0x29010000 0x2c5 0x1290100 0x02 0xc6602901 0x00 0x2c70129 0x1000000 0x2c895 0x29010000 0x2c9 0x1290100 0x02 0xcae12901 0x00 0x2cb0229 0x1000000 0x2cc20 0x29010000 0x2cd 0x2290100 0x02 0xce232901 0x00 0x2cf0229 0x1000000 0x2d059 0x29010000 0x2d1 0x2290100 0x02 0xd2942901 0x00 0x2d30229 0x1000000 0x2d4b4 0x29010000 0x2d5 0x2290100 0x02 0xd6e12901 0x00 0x2d70329 0x1000000 0x2d801 0x29010000 0x2d9 0x3290100 0x02 0xda282901 0x00 0x2db0329 0x1000000 0x2dc30 0x29010000 0x2dd 0x3290100 0x02 0xde372901 0x00 0x2df0329 0x1000000 0x2e03b 0x29010000 0x2e1 0x3290100 0x02 0xe2402901 0x00 0x2e30329 0x1000000 0x2e450 0x29010000 0x2e5 0x3290100 0x02 0xe66d2901 0x00 0x2e70329 0x1000000 0x2e880 0x29010000 0x2e9 0x3290100 0x02 0xeacb2901 0x00 0x2ff0129 0x1000000 0x2fb01 0x29010000 0x2ff 0x2290100 0x02 0xfb012901 0x00 0x2ff0429 0x1000000 0x2fb01 0x29010000 0x2ff 0x290100 0x640002 0x11002901 0x00 0x2ffee29 0x1000000 0x21250 0x29010000 0x213 0x2290100 0x02 0x6a602901 0x00 0x2ff0029 0x1000078 0x22900>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| }; | |
| qcom,mdss_fb_primary { | |
| qcom,memory-reservation-size = <0x800000>; | |
| qcom,memblock-reserve = <0x3200000 0xfa0000>; | |
| qcom,memory-reservation-type = "EBI1"; | |
| cell-index = <0x00>; | |
| compatible = "qcom,mdss-fb"; | |
| phandle = <0x1e>; | |
| linux,phandle = <0x1e>; | |
| }; | |
| qcom,mdss_dsi_nt35590_720p_video { | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-panel-name = "nt35590 720p video mode dsi panel"; | |
| qcom,mdss-dsi-panel-height = <0x500>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-panel-controller = <0x1d>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-panel-timings = <0x7d251d00 0x37332227 0x1e030400>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-pan-physical-width-dimension = <0x3b>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-h-back-porch = <0xa4>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-pan-physical-height-dimension = <0x68>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-v-front-porch = <0x06>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-t-clk-post = <0x20>; | |
| qcom,mdss-dsi-h-front-porch = <0x8c>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x14 0x00 0x01 0x01 0x14>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-t-clk-pre = <0x2c>; | |
| qcom,mdss-dsi-panel-destination = "display_1"; | |
| qcom,mdss-dsi-h-sync-pulse = <0x01>; | |
| qcom,mdss-dsi-v-back-porch = <0x01>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-h-pulse-width = <0x08>; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-on-command = [29 01 00 00 00 00 02 ff ee 29 01 00 00 00 00 02 26 08 29 01 00 00 00 00 02 26 00 29 01 00 00 10 00 02 ff 00 29 01 00 00 00 00 02 ba 03 29 01 00 00 00 00 02 c2 03 29 01 00 00 00 00 02 ff 01 29 01 00 00 00 00 02 fb 01 29 01 00 00 00 00 02 00 4a 29 01 00 00 00 00 02 01 33 29 01 00 00 00 00 02 02 53 29 01 00 00 00 00 02 03 55 29 01 00 00 00 00 02 04 55 29 01 00 00 00 00 02 05 33 29 01 00 00 00 00 02 06 22 29 01 00 00 00 00 02 08 56 29 01 00 00 00 00 02 09 8f 29 01 00 00 00 00 02 36 73 29 01 00 00 00 00 02 0b 9f 29 01 00 00 00 00 02 0c 9f 29 01 00 00 00 00 02 0d 2f 29 01 00 00 00 00 02 0e 24 29 01 00 00 00 00 02 11 83 29 01 00 00 00 00 02 12 03 29 01 00 00 00 00 02 71 2c 29 01 00 00 00 00 02 6f 03 29 01 00 00 00 00 02 0f 0a 29 01 00 00 00 00 02 ff 05 29 01 00 00 00 00 02 fb 01 29 01 00 00 00 00 02 01 00 29 01 00 00 00 00 02 02 8b 29 01 00 00 00 00 02 03 82 29 01 00 00 00 00 02 04 82 29 01 00 00 00 00 02 05 30 29 01 00 00 00 00 02 06 33 29 01 00 00 00 00 02 07 01 29 01 00 00 00 00 02 08 00 29 01 00 00 00 00 02 09 46 29 01 00 00 00 00 02 0a 46 29 01 00 00 00 00 02 0d 0b 29 01 00 00 00 00 02 0e 1d 29 01 00 00 00 00 02 0f 08 29 01 00 00 00 00 02 10 53 29 01 00 00 00 00 02 11 00 29 01 00 00 00 00 02 12 00 29 01 00 00 00 00 02 14 01 29 01 00 00 00 00 02 15 00 29 01 00 00 00 00 02 16 05 29 01 00 00 00 00 02 17 00 29 01 00 00 00 00 02 19 7f 29 01 00 00 00 00 02 1a ff 29 01 00 00 00 00 02 1b 0f 29 01 00 00 00 00 02 1c 00 29 01 00 00 00 00 02 1d 00 29 01 00 00 00 00 02 1e 00 29 01 00 00 00 00 02 1f 07 29 01 00 00 00 00 02 20 00 29 01 00 00 00 00 02 21 06 29 01 00 00 00 00 02 22 55 29 01 00 00 00 00 02 23 4d 29 01 00 00 00 00 02 2d 02 29 01 00 00 00 00 02 28 01 29 01 00 00 00 00 02 2f 02 29 01 00 00 00 00 02 83 01 29 01 00 00 00 00 02 9e 58 29 01 00 00 00 00 02 9f 6a 29 01 00 00 00 00 02 a0 01 29 01 00 00 00 00 02 a2 10 29 01 00 00 00 00 02 bb 0a 29 01 00 00 00 00 02 bc 0a 29 01 00 00 00 00 02 32 08 29 01 00 00 00 00 02 33 b8 29 01 00 00 00 00 02 36 01 29 01 00 00 00 00 02 37 00 29 01 00 00 00 00 02 43 00 29 01 00 00 00 00 02 4b 21 29 01 00 00 00 00 02 4c 03 29 01 00 00 00 00 02 50 21 29 01 00 00 00 00 02 51 03 29 01 00 00 00 00 02 58 21 29 01 00 00 00 00 02 59 03 29 01 00 00 00 00 02 5d 21 29 01 00 00 00 00 02 5e 03 29 01 00 00 00 00 02 6c 00 29 01 00 00 00 00 02 6d 00 29 01 00 00 00 00 02 fb 01 29 01 00 00 00 00 02 ff 01 29 01 00 00 00 00 02 fb 01 29 01 00 00 00 00 02 75 00 29 01 00 00 00 00 02 76 7d 29 01 00 00 00 00 02 77 00 29 01 00 00 00 00 02 78 8a 29 01 00 00 00 00 02 79 00 29 01 00 00 00 00 02 7a 9c 29 01 00 00 00 00 02 7b 00 29 01 00 00 00 00 02 7c b1 29 01 00 00 00 00 02 7d 00 29 01 00 00 00 00 02 7e bf 29 01 00 00 00 00 02 7f 00 29 01 00 00 00 00 02 80 cf 29 01 00 00 00 00 02 81 00 29 01 00 00 00 00 02 82 dd 29 01 00 00 00 00 02 83 00 29 01 00 00 00 00 02 84 e8 29 01 00 00 00 00 02 85 00 29 01 00 00 00 00 02 86 f2 29 01 00 00 00 00 02 87 01 29 01 00 00 00 00 02 88 1f 29 01 00 00 00 00 02 89 01 29 01 00 00 00 00 02 8a 41 29 01 00 00 00 00 02 8b 01 29 01 00 00 00 00 02 8c 78 29 01 00 00 00 00 02 8d 01 29 01 00 00 00 00 02 8e a5 29 01 00 00 00 00 02 8f 01 29 01 00 00 00 00 02 90 ee 29 01 00 00 00 00 02 91 02 29 01 00 00 00 00 02 92 29 29 01 00 00 00 00 02 93 02 29 01 00 00 00 00 02 94 2a 29 01 00 00 00 00 02 95 02 29 01 00 00 00 00 02 96 5d 29 01 00 00 00 00 02 97 02 29 01 00 00 00 00 02 98 93 29 01 00 00 00 00 02 99 02 29 01 00 00 00 00 02 9a b8 29 01 00 00 00 00 02 9b 02 29 01 00 00 00 00 02 9c e7 29 01 00 00 00 00 02 9d 03 29 01 00 00 00 00 02 9e 07 29 01 00 00 00 00 02 9f 03 29 01 00 00 00 00 02 a0 37 29 01 00 00 00 00 02 a2 03 29 01 00 00 00 00 02 a3 46 29 01 00 00 00 00 02 a4 03 29 01 00 00 00 00 02 a5 56 29 01 00 00 00 00 02 a6 03 29 01 00 00 00 00 02 a7 66 29 01 00 00 00 00 02 a9 03 29 01 00 00 00 00 02 aa 7a 29 01 00 00 00 00 02 ab 03 29 01 00 00 00 00 02 ac 93 29 01 00 00 00 00 02 ad 03 29 01 00 00 00 00 02 ae a3 29 01 00 00 00 00 02 af 03 29 01 00 00 00 00 02 b0 b4 29 01 00 00 00 00 02 b1 03 29 01 00 00 00 00 02 b2 cb 29 01 00 00 00 00 02 b3 00 29 01 00 00 00 00 02 b4 7d 29 01 00 00 00 00 02 b5 00 29 01 00 00 00 00 02 b6 8a 29 01 00 00 00 00 02 b7 00 29 01 00 00 00 00 02 b8 9c 29 01 00 00 00 00 02 b9 00 29 01 00 00 00 00 02 ba b1 29 01 00 00 00 00 02 bb 00 29 01 00 00 00 00 02 bc bf 29 01 00 00 00 00 02 bd 00 29 01 00 00 00 00 02 be cf 29 01 00 00 00 00 02 bf 00 29 01 00 00 00 00 02 c0 dd 29 01 00 00 00 00 02 c1 00 29 01 00 00 00 00 02 c2 e8 29 01 00 00 00 00 02 c3 00 29 01 00 00 00 00 02 c4 f2 29 01 00 00 00 00 02 c5 01 29 01 00 00 00 00 02 c6 1f 29 01 00 00 00 00 02 c7 01 29 01 00 00 00 00 02 c8 41 29 01 00 00 00 00 02 c9 01 29 01 00 00 00 00 02 ca 78 29 01 00 00 00 00 02 cb 01 29 01 00 00 00 00 02 cc a5 29 01 00 00 00 00 02 cd 01 29 01 00 00 00 00 02 ce ee 29 01 00 00 00 00 02 cf 02 29 01 00 00 00 00 02 d0 29 29 01 00 00 00 00 02 d1 02 29 01 00 00 00 00 02 d2 2a 29 01 00 00 00 00 02 d3 02 29 01 00 00 00 00 02 d4 5d 29 01 00 00 00 00 02 d5 02 29 01 00 00 00 00 02 d6 93 29 01 00 00 00 00 02 d7 02 29 01 00 00 00 00 02 d8 b8 29 01 00 00 00 00 02 d9 02 29 01 00 00 00 00 02 da e7 29 01 00 00 00 00 02 db 03 29 01 00 00 00 00 02 dc 07 29 01 00 00 00 00 02 dd 03 29 01 00 00 00 00 02 de 37 29 01 00 00 00 00 02 df 03 29 01 00 00 00 00 02 e0 46 29 01 00 00 00 00 02 e1 03 29 01 00 00 00 00 02 e2 56 29 01 00 00 00 00 02 e3 03 29 01 00 00 00 00 02 e4 66 29 01 00 00 00 00 02 e5 03 29 01 00 00 00 00 02 e6 7a 29 01 00 00 00 00 02 e7 03 29 01 00 00 00 00 02 e8 93 29 01 00 00 00 00 02 e9 03 29 01 00 00 00 00 02 ea a3 29 01 00 00 00 00 02 eb 03 29 01 00 00 00 00 02 ec b4 29 01 00 00 00 00 02 ed 03 29 01 00 00 00 00 02 ee cb 29 01 00 00 00 00 02 ef 00 29 01 00 00 00 00 02 f0 ed 29 01 00 00 00 00 02 f1 00 29 01 00 00 00 00 02 f2 f3 29 01 00 00 00 00 02 f3 00 29 01 00 00 00 00 02 f4 fe 29 01 00 00 00 00 02 f5 01 29 01 00 00 00 00 02 f6 09 29 01 00 00 00 00 02 f7 01 29 01 00 00 00 00 02 f8 13 29 01 00 00 00 00 02 f9 01 29 01 00 00 00 00 02 fa 1d 29 01 00 00 00 00 02 ff 02 29 01 00 00 00 00 02 fb 01 29 01 00 00 00 00 02 00 01 29 01 00 00 00 00 02 01 26 29 01 00 00 00 00 02 02 01 29 01 00 00 00 00 02 03 2f 29 01 00 00 00 00 02 04 01 29 01 00 00 00 00 02 05 37 29 01 00 00 00 00 02 06 01 29 01 00 00 00 00 02 07 56 29 01 00 00 00 00 02 08 01 29 01 00 00 00 00 02 09 70 29 01 00 00 00 00 02 0a 01 29 01 00 00 00 00 02 0b 9d 29 01 00 00 00 00 02 0c 01 29 01 00 00 00 00 02 0d c2 29 01 00 00 00 00 02 0e 01 29 01 00 00 00 00 02 0f ff 29 01 00 00 00 00 02 10 02 29 01 00 00 00 00 02 11 31 29 01 00 00 00 00 02 12 02 29 01 00 00 00 00 02 13 32 29 01 00 00 00 00 02 14 02 29 01 00 00 00 00 02 15 60 29 01 00 00 00 00 02 16 02 29 01 00 00 00 00 02 17 94 29 01 00 00 00 00 02 18 02 29 01 00 00 00 00 02 19 b5 29 01 00 00 00 00 02 1a 02 29 01 00 00 00 00 02 1b e3 29 01 00 00 00 00 02 1c 03 29 01 00 00 00 00 02 1d 03 29 01 00 00 00 00 02 1e 03 29 01 00 00 00 00 02 1f 2d 29 01 00 00 00 00 02 20 03 29 01 00 00 00 00 02 21 3a 29 01 00 00 00 00 02 22 03 29 01 00 00 00 00 02 23 48 29 01 00 00 00 00 02 24 03 29 01 00 00 00 00 02 25 57 29 01 00 00 00 00 02 26 03 29 01 00 00 00 00 02 27 68 29 01 00 00 00 00 02 28 03 29 01 00 00 00 00 02 29 7b 29 01 00 00 00 00 02 2a 03 29 01 00 00 00 00 02 2b 90 29 01 00 00 00 00 02 2d 03 29 01 00 00 00 00 02 2f a0 29 01 00 00 00 00 02 30 03 29 01 00 00 00 00 02 31 cb 29 01 00 00 00 00 02 32 00 29 01 00 00 00 00 02 33 ed 29 01 00 00 00 00 02 34 00 29 01 00 00 00 00 02 35 f3 29 01 00 00 00 00 02 36 00 29 01 00 00 00 00 02 37 fe 29 01 00 00 00 00 02 38 01 29 01 00 00 00 00 02 39 09 29 01 00 00 00 00 02 3a 01 29 01 00 00 00 00 02 3b 13 29 01 00 00 00 00 02 3d 01 29 01 00 00 00 00 02 3f 1d 29 01 00 00 00 00 02 40 01 29 01 00 00 00 00 02 41 26 29 01 00 00 00 00 02 42 01 29 01 00 00 00 00 02 43 2f 29 01 00 00 00 00 02 44 01 29 01 00 00 00 00 02 45 37 29 01 00 00 00 00 02 46 01 29 01 00 00 00 00 02 47 56 29 01 00 00 00 00 02 48 01 29 01 00 00 00 00 02 49 70 29 01 00 00 00 00 02 4a 01 29 01 00 00 00 00 02 4b 9d 29 01 00 00 00 00 02 4c 01 29 01 00 00 00 00 02 4d c2 29 01 00 00 00 00 02 4e 01 29 01 00 00 00 00 02 4f ff 29 01 00 00 00 00 02 50 02 29 01 00 00 00 00 02 51 31 29 01 00 00 00 00 02 52 02 29 01 00 00 00 00 02 53 32 29 01 00 00 00 00 02 54 02 29 01 00 00 00 00 02 55 60 29 01 00 00 00 00 02 56 02 29 01 00 00 00 00 02 58 94 29 01 00 00 00 00 02 59 02 29 01 00 00 00 00 02 5a b5 29 01 00 00 00 00 02 5b 02 29 01 00 00 00 00 02 5c e3 29 01 00 00 00 00 02 5d 03 29 01 00 00 00 00 02 5e 03 29 01 00 00 00 00 02 5f 03 29 01 00 00 00 00 02 60 2d 29 01 00 00 00 00 02 61 03 29 01 00 00 00 00 02 62 3a 29 01 00 00 00 00 02 63 03 29 01 00 00 00 00 02 64 48 29 01 00 00 00 00 02 65 03 29 01 00 00 00 00 02 66 57 29 01 00 00 00 00 02 67 03 29 01 00 00 00 00 02 68 68 29 01 00 00 00 00 02 69 03 29 01 00 00 00 00 02 6a 7b 29 01 00 00 00 00 02 6b 03 29 01 00 00 00 00 02 6c 90 29 01 00 00 00 00 02 6d 03 29 01 00 00 00 00 02 6e a0 29 01 00 00 00 00 02 6f 03 29 01 00 00 00 00 02 70 cb 29 01 00 00 00 00 02 71 00 29 01 00 00 00 00 02 72 19 29 01 00 00 00 00 02 73 00 29 01 00 00 00 00 02 74 36 29 01 00 00 00 00 02 75 00 29 01 00 00 00 00 02 76 55 29 01 00 00 00 00 02 77 00 29 01 00 00 00 00 02 78 70 29 01 00 00 00 00 02 79 00 29 01 00 00 00 00 02 7a 83 29 01 00 00 00 00 02 7b 00 29 01 00 00 00 00 02 7c 99 29 01 00 00 00 00 02 7d 00 29 01 00 00 00 00 02 7e a8 29 01 00 00 00 00 02 7f 00 29 01 00 00 00 00 02 80 b7 29 01 00 00 00 00 02 81 00 29 01 00 00 00 00 02 82 c5 29 01 00 00 00 00 02 83 00 29 01 00 00 00 00 02 84 f7 29 01 00 00 00 00 02 85 01 29 01 00 00 00 00 02 86 1e 29 01 00 00 00 00 02 87 01 29 01 00 00 00 00 02 88 60 29 01 00 00 00 00 02 89 01 29 01 00 00 00 00 02 8a 95 29 01 00 00 00 00 02 8b 01 29 01 00 00 00 00 02 8c e1 29 01 00 00 00 00 02 8d 02 29 01 00 00 00 00 02 8e 20 29 01 00 00 00 00 02 8f 02 29 01 00 00 00 00 02 90 23 29 01 00 00 00 00 02 91 02 29 01 00 00 00 00 02 92 59 29 01 00 00 00 00 02 93 02 29 01 00 00 00 00 02 94 94 29 01 00 00 00 00 02 95 02 29 01 00 00 00 00 02 96 b4 29 01 00 00 00 00 02 97 02 29 01 00 00 00 00 02 98 e1 29 01 00 00 00 00 02 99 03 29 01 00 00 00 00 02 9a 01 29 01 00 00 00 00 02 9b 03 29 01 00 00 00 00 02 9c 28 29 01 00 00 00 00 02 9d 03 29 01 00 00 00 00 02 9e 30 29 01 00 00 00 00 02 9f 03 29 01 00 00 00 00 02 a0 37 29 01 00 00 00 00 02 a2 03 29 01 00 00 00 00 02 a3 3b 29 01 00 00 00 00 02 a4 03 29 01 00 00 00 00 02 a5 40 29 01 00 00 00 00 02 a6 03 29 01 00 00 00 00 02 a7 50 29 01 00 00 00 00 02 a9 03 29 01 00 00 00 00 02 aa 6d 29 01 00 00 00 00 02 ab 03 29 01 00 00 00 00 02 ac 80 29 01 00 00 00 00 02 ad 03 29 01 00 00 00 00 02 ae cb 29 01 00 00 00 00 02 af 00 29 01 00 00 00 00 02 b0 19 29 01 00 00 00 00 02 b1 00 29 01 00 00 00 00 02 b2 36 29 01 00 00 00 00 02 b3 00 29 01 00 00 00 00 02 b4 55 29 01 00 00 00 00 02 b5 00 29 01 00 00 00 00 02 b6 70 29 01 00 00 00 00 02 b7 00 29 01 00 00 00 00 02 b8 83 29 01 00 00 00 00 02 b9 00 29 01 00 00 00 00 02 ba 99 29 01 00 00 00 00 02 bb 00 29 01 00 00 00 00 02 bc a8 29 01 00 00 00 00 02 bd 00 29 01 00 00 00 00 02 be b7 29 01 00 00 00 00 02 bf 00 29 01 00 00 00 00 02 c0 c5 29 01 00 00 00 00 02 c1 00 29 01 00 00 00 00 02 c2 f7 29 01 00 00 00 00 02 c3 01 29 01 00 00 00 00 02 c4 1e 29 01 00 00 00 00 02 c5 01 29 01 00 00 00 00 02 c6 60 29 01 00 00 00 00 02 c7 01 29 01 00 00 00 00 02 c8 95 29 01 00 00 00 00 02 c9 01 29 01 00 00 00 00 02 ca e1 29 01 00 00 00 00 02 cb 02 29 01 00 00 00 00 02 cc 20 29 01 00 00 00 00 02 cd 02 29 01 00 00 00 00 02 ce 23 29 01 00 00 00 00 02 cf 02 29 01 00 00 00 00 02 d0 59 29 01 00 00 00 00 02 d1 02 29 01 00 00 00 00 02 d2 94 29 01 00 00 00 00 02 d3 02 29 01 00 00 00 00 02 d4 b4 29 01 00 00 00 00 02 d5 02 29 01 00 00 00 00 02 d6 e1 29 01 00 00 00 00 02 d7 03 29 01 00 00 00 00 02 d8 01 29 01 00 00 00 00 02 d9 03 29 01 00 00 00 00 02 da 28 29 01 00 00 00 00 02 db 03 29 01 00 00 00 00 02 dc 30 29 01 00 00 00 00 02 dd 03 29 01 00 00 00 00 02 de 37 29 01 00 00 00 00 02 df 03 29 01 00 00 00 00 02 e0 3b 29 01 00 00 00 00 02 e1 03 29 01 00 00 00 00 02 e2 40 29 01 00 00 00 00 02 e3 03 29 01 00 00 00 00 02 e4 50 29 01 00 00 00 00 02 e5 03 29 01 00 00 00 00 02 e6 6d 29 01 00 00 00 00 02 e7 03 29 01 00 00 00 00 02 e8 80 29 01 00 00 00 00 02 e9 03 29 01 00 00 00 00 02 ea cb 29 01 00 00 00 00 02 ff 01 29 01 00 00 00 00 02 fb 01 29 01 00 00 00 00 02 ff 02 29 01 00 00 00 00 02 fb 01 29 01 00 00 00 00 02 ff 04 29 01 00 00 00 00 02 fb 01 29 01 00 00 00 00 02 ff 00 29 01 00 00 64 00 02 11 00 29 01 00 00 00 00 02 ff ee 29 01 00 00 00 00 02 12 50 29 01 00 00 00 00 02 13 02 29 01 00 00 00 00 02 6a 60 29 01 00 00 00 00 02 ff 00 29 01 00 00 78 00 02 29 00 29 01 00 00 78 00 02 53 2c]; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| }; | |
| qcom,mdss_dsi_mot_cmi_720p_video_v0 { | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-panel-name = "mipi_mot_video_cmi_hd_450 v0"; | |
| qcom,mdss-dsi-tune-h-back-porch = <0x3e>; | |
| qcom,mdss-dsi-panel-height = <0x500>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-panel-controller = <0x1d>; | |
| qcom,panel-dis-reset-sequence = <0x00 0x03>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-tune-v-front-porch = <0x0f>; | |
| qcom,mdss-dsi-panel-timings = <0xc33e3400 0x554f3340 0x29030400>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-pan-physical-width-dimension = <0x38>; | |
| qcom,cont-splash-enabled; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-cont-splash-skip-ov-handoff; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-panel-clockrate = <0x2f8a6900>; | |
| qcom,mdss-dsi-h-back-porch = <0x40>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| status = "ok"; | |
| qcom,mdss-dsi-tune-v-pulse-width = <0x500>; | |
| qcom,mdss-pan-physical-height-dimension = <0x63>; | |
| mmi,panel_name = "mipi_mot_video_cmi_hd_450"; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-tune-h-pulse-width = <0x08>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-v-front-porch = <0x06>; | |
| mmi,panel_ver_min = <0x00 0x00>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-t-clk-post = <0x1e>; | |
| qcom,panel-en-reset-sequence = <0x01 0x0b>; | |
| qcom,mdss-dsi-tune-h-front-porch = <0x3e>; | |
| qcom,mdss-dsi-h-front-porch = <0x40>; | |
| qcom,mdss-dsi-tune-v-back-porch = <0x0f>; | |
| compatible = "qcom,mdss-dsi-panel"; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 32 00 02 10 00]; | |
| qcom,mdss-dsi-t-clk-pre = <0x32>; | |
| qcom,mdss-dsi-panel-destination = "display_1"; | |
| qcom,mdss-dsi-h-sync-pulse = <0x01>; | |
| qcom,mdss-dsi-esd-det-mode = <0x01>; | |
| qcom,mdss-dsi-v-back-porch = <0x01>; | |
| mmi,panel_ver_max = <0x00 0x185c1>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-h-pulse-width = <0x08>; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,panel-esd-power-mode-chk = <0x94>; | |
| qcom,mdss-dsi-on-command = <0x29010000 0x2ba 0x1290100 0x02 0xfb012901 0x7800 0x2110029 0x1000000 0x251ff 0x29010000 0x253 0x2c290100 0x02 0x35002901 0x00 0x2550329 0x1000000 0x22900>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,platform-supply-entry1 { | |
| qcom,supply-pre-off-sleep = <0x00>; | |
| qcom,supply-enable-load = <0x186a0>; | |
| qcom,supply-post-on-sleep = <0x02>; | |
| qcom,supply-min-voltage = <0x1b7740>; | |
| qcom,supply-max-voltage = <0x1b7740>; | |
| qcom,supply-post-off-sleep = <0x00>; | |
| qcom,supply-name = "vddio_disp"; | |
| qcom,supply-pre-on-sleep = <0x00>; | |
| qcom,supply-disable-load = <0x64>; | |
| }; | |
| qcom,platform-supply-entry2 { | |
| qcom,supply-pre-off-sleep = <0x00>; | |
| qcom,supply-enable-load = <0x186a0>; | |
| qcom,supply-post-on-sleep = <0x0b>; | |
| qcom,supply-min-voltage = <0x5265c0>; | |
| qcom,supply-max-voltage = <0x5265c0>; | |
| qcom,supply-post-off-sleep = <0x02>; | |
| qcom,supply-name = "lcdbias"; | |
| qcom,supply-pre-on-sleep = <0x00>; | |
| qcom,supply-disable-load = <0x64>; | |
| }; | |
| }; | |
| qcom,mdss_fb_wfd { | |
| cell-index = <0x01>; | |
| compatible = "qcom,mdss-fb"; | |
| phandle = <0x25>; | |
| linux,phandle = <0x25>; | |
| }; | |
| qcom,mdss_dsi_hx8394a_720p_video { | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-panel-name = "hx8394a 720p video mode dsi panel"; | |
| qcom,mdss-dsi-panel-height = <0x500>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-panel-controller = <0x1d>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-panel-timings = <0x8d241900 0x34341d26 0x2a030400>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-h-back-porch = <0x3b>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-v-front-porch = <0x07>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-t-clk-post = <0x1f>; | |
| qcom,mdss-dsi-h-front-porch = <0x4f>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x14 0x00 0x01 0x01 0x14>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 0a 00 02 28 00 05 01 00 00 96 00 02 10 00]; | |
| qcom,mdss-dsi-t-clk-pre = <0x2d>; | |
| qcom,mdss-dsi-panel-destination = "display_1"; | |
| qcom,mdss-dsi-h-sync-pulse = <0x01>; | |
| qcom,mdss-dsi-v-back-porch = <0x0a>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-h-pulse-width = <0x3c>; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 04 b9 ff 83 94 39 01 00 00 00 00 05 c7 00 10 00 10 39 01 00 00 00 00 02 bc 07 39 01 00 00 00 00 02 ba 13 39 01 00 00 00 00 10 b1 01 00 07 83 01 12 0f 32 38 29 29 50 02 00 00 39 01 00 00 00 00 07 b2 00 c8 09 05 00 71 39 01 00 00 00 00 02 cc 05 05 01 00 00 00 00 02 00 00 39 01 00 00 00 00 35 d5 00 00 00 00 0a 00 01 00 00 00 33 00 23 45 67 01 01 23 88 88 88 88 88 88 88 99 99 99 88 88 99 88 54 32 10 76 32 10 88 88 88 88 88 88 88 99 99 99 88 88 88 99 39 01 00 00 00 00 17 b4 80 08 32 10 00 32 15 08 32 12 20 33 05 4c 05 37 05 3f 1e 5f 5f 06 39 01 00 00 00 00 02 b6 00 39 01 00 00 00 00 23 e0 01 05 07 25 35 3f 0b 32 04 09 0e 10 13 10 14 16 1b 01 05 07 25 35 3f 0b 32 04 09 0e 10 13 10 14 16 1b 05 01 00 00 00 00 02 00 00 39 01 00 00 00 00 04 bf 06 00 10 05 01 00 00 c8 00 02 11 00 05 01 00 00 32 00 02 29 00]; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| }; | |
| qcom,mdss_dsi_mot_cmi_720p_video_v2 { | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-panel-name = "mipi_mot_video_cmi_hd_450 v2"; | |
| qcom,mdss-dsi-tune-h-back-porch = <0x3e>; | |
| qcom,mdss-dsi-panel-height = <0x500>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-panel-controller = <0x1d>; | |
| qcom,panel-dis-reset-sequence = <0x00 0x03>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-tune-v-front-porch = <0x0f>; | |
| qcom,mdss-dsi-panel-timings = <0xc33e3400 0x554f3340 0x29030400>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-pan-physical-width-dimension = <0x38>; | |
| qcom,cont-splash-enabled; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-cont-splash-skip-ov-handoff; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-panel-clockrate = <0x2f8a6900>; | |
| qcom,mdss-dsi-h-back-porch = <0x40>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| status = "ok"; | |
| qcom,mdss-dsi-tune-v-pulse-width = <0x500>; | |
| qcom,mdss-pan-physical-height-dimension = <0x63>; | |
| mmi,panel_name = "mipi_mot_video_cmi_hd_450"; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-tune-h-pulse-width = <0x08>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-v-front-porch = <0x06>; | |
| mmi,panel_ver_min = <0x00 0x186c2>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-t-clk-post = <0x1e>; | |
| qcom,panel-en-reset-sequence = <0x01 0x0b>; | |
| qcom,mdss-dsi-tune-h-front-porch = <0x3e>; | |
| qcom,mdss-dsi-h-front-porch = <0x40>; | |
| qcom,mdss-dsi-tune-v-back-porch = <0x0f>; | |
| compatible = "qcom,mdss-dsi-panel"; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 32 00 02 10 00]; | |
| qcom,mdss-dsi-t-clk-pre = <0x32>; | |
| qcom,mdss-dsi-panel-destination = "display_1"; | |
| qcom,mdss-dsi-h-sync-pulse = <0x01>; | |
| qcom,mdss-dsi-esd-det-mode = <0x01>; | |
| phandle = <0x21>; | |
| qcom,mdss-dsi-v-back-porch = <0x01>; | |
| mmi,panel_ver_max = <0xffffffff 0xffffffff>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-h-pulse-width = <0x08>; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| linux,phandle = <0x21>; | |
| qcom,panel-esd-power-mode-chk = <0x94>; | |
| qcom,mdss-dsi-on-command = [29 01 00 00 00 00 02 ff 01 29 01 00 00 00 00 02 4c 00 29 01 00 00 00 00 02 fb 01 29 01 00 00 00 00 02 ff 00 29 01 00 00 00 00 04 3b 03 01 03 29 01 00 00 00 00 02 fb 01 29 01 00 00 78 00 02 11 00 29 01 00 00 00 00 02 51 ff 29 01 00 00 00 00 02 53 2c 29 01 00 00 00 00 02 35 00 29 01 00 00 00 00 02 55 92 29 01 00 00 00 00 02 29 00]; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,platform-supply-entry1 { | |
| qcom,supply-pre-off-sleep = <0x00>; | |
| qcom,supply-enable-load = <0x186a0>; | |
| qcom,supply-post-on-sleep = <0x02>; | |
| qcom,supply-min-voltage = <0x1b7740>; | |
| qcom,supply-max-voltage = <0x1b7740>; | |
| qcom,supply-post-off-sleep = <0x00>; | |
| qcom,supply-name = "vddio_disp"; | |
| qcom,supply-pre-on-sleep = <0x00>; | |
| qcom,supply-disable-load = <0x64>; | |
| }; | |
| qcom,platform-supply-entry2 { | |
| qcom,supply-pre-off-sleep = <0x00>; | |
| qcom,supply-enable-load = <0x186a0>; | |
| qcom,supply-post-on-sleep = <0x0b>; | |
| qcom,supply-min-voltage = <0x5265c0>; | |
| qcom,supply-max-voltage = <0x5265c0>; | |
| qcom,supply-post-off-sleep = <0x02>; | |
| qcom,supply-name = "lcdbias"; | |
| qcom,supply-pre-on-sleep = <0x00>; | |
| qcom,supply-disable-load = <0x64>; | |
| }; | |
| }; | |
| qcom,mdss_dsi_mot_cmi_720p_video_v1 { | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-panel-name = "mipi_mot_video_cmi_hd_450 v1"; | |
| qcom,mdss-dsi-tune-h-back-porch = <0x3e>; | |
| qcom,mdss-dsi-panel-height = <0x500>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-panel-controller = <0x1d>; | |
| qcom,panel-dis-reset-sequence = <0x00 0x03>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-tune-v-front-porch = <0x0f>; | |
| qcom,mdss-dsi-panel-timings = <0xc33e3400 0x554f3340 0x29030400>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-pan-physical-width-dimension = <0x38>; | |
| qcom,cont-splash-enabled; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-cont-splash-skip-ov-handoff; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-panel-clockrate = <0x2f8a6900>; | |
| qcom,mdss-dsi-h-back-porch = <0x40>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| status = "ok"; | |
| qcom,mdss-dsi-tune-v-pulse-width = <0x500>; | |
| qcom,mdss-pan-physical-height-dimension = <0x63>; | |
| mmi,panel_name = "mipi_mot_video_cmi_hd_450"; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-tune-h-pulse-width = <0x08>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsi-v-front-porch = <0x06>; | |
| mmi,panel_ver_min = <0x00 0x185c2>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-t-clk-post = <0x1e>; | |
| qcom,panel-en-reset-sequence = <0x01 0x0b>; | |
| qcom,mdss-dsi-tune-h-front-porch = <0x3e>; | |
| qcom,mdss-dsi-h-front-porch = <0x40>; | |
| qcom,mdss-dsi-tune-v-back-porch = <0x0f>; | |
| compatible = "qcom,mdss-dsi-panel"; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 32 00 02 10 00]; | |
| qcom,mdss-dsi-t-clk-pre = <0x32>; | |
| qcom,mdss-dsi-panel-destination = "display_1"; | |
| qcom,mdss-dsi-h-sync-pulse = <0x01>; | |
| qcom,mdss-dsi-esd-det-mode = <0x01>; | |
| qcom,mdss-dsi-v-back-porch = <0x01>; | |
| mmi,panel_ver_max = <0x00 0x186c1>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-h-pulse-width = <0x08>; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,panel-esd-power-mode-chk = <0x94>; | |
| qcom,mdss-dsi-on-command = [29 01 00 00 00 00 02 ff 03 29 01 00 00 00 00 02 56 00 29 01 00 00 00 00 02 00 00 29 01 00 00 00 00 02 01 04 29 01 00 00 00 00 02 02 08 29 01 00 00 00 00 02 03 0c 29 01 00 00 00 00 02 04 10 29 01 00 00 00 00 02 05 14 29 01 00 00 00 00 02 06 18 29 01 00 00 00 00 02 07 20 29 01 00 00 00 00 02 08 24 29 01 00 00 00 00 02 09 28 29 01 00 00 00 00 02 0a 30 29 01 00 00 00 00 02 0b 38 29 01 00 00 00 00 02 0c 38 29 01 00 00 00 00 02 0d 30 29 01 00 00 00 00 02 0e 28 29 01 00 00 00 00 02 0f 20 29 01 00 00 00 00 02 1b 00 29 01 00 00 00 00 02 1c 04 29 01 00 00 00 00 02 1d 08 29 01 00 00 00 00 02 1e 0c 29 01 00 00 00 00 02 1f 10 29 01 00 00 00 00 02 20 14 29 01 00 00 00 00 02 24 10 29 01 00 00 00 00 02 25 08 29 01 00 00 00 00 02 18 28 29 01 00 00 00 00 02 19 38 29 01 00 00 00 00 02 1a 77 29 01 00 00 00 00 02 21 18 29 01 00 00 00 00 02 22 20 29 01 00 00 00 00 02 23 18 29 01 00 00 00 00 02 fb 01 29 01 00 00 00 00 02 ff 00 29 01 00 00 00 00 02 ff 01 29 01 00 00 00 00 02 4c 00 29 01 00 00 00 00 02 fb 01 29 01 00 00 00 00 02 ff 00 29 01 00 00 00 00 04 3b 03 01 03 29 01 00 00 00 00 02 fb 01 29 01 00 00 78 00 02 11 00 29 01 00 00 00 00 02 ff 04 29 01 00 00 00 00 02 08 04 29 01 00 00 00 00 02 ff 00 29 01 00 00 00 00 02 51 ff 29 01 00 00 00 00 02 53 2c 29 01 00 00 00 00 02 35 00 29 01 00 00 00 00 02 55 92 29 01 00 00 00 00 02 29 00]; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,platform-supply-entry1 { | |
| qcom,supply-pre-off-sleep = <0x00>; | |
| qcom,supply-enable-load = <0x186a0>; | |
| qcom,supply-post-on-sleep = <0x02>; | |
| qcom,supply-min-voltage = <0x1b7740>; | |
| qcom,supply-max-voltage = <0x1b7740>; | |
| qcom,supply-post-off-sleep = <0x00>; | |
| qcom,supply-name = "vddio_disp"; | |
| qcom,supply-pre-on-sleep = <0x00>; | |
| qcom,supply-disable-load = <0x64>; | |
| }; | |
| qcom,platform-supply-entry2 { | |
| qcom,supply-pre-off-sleep = <0x00>; | |
| qcom,supply-enable-load = <0x186a0>; | |
| qcom,supply-post-on-sleep = <0x0b>; | |
| qcom,supply-min-voltage = <0x5265c0>; | |
| qcom,supply-max-voltage = <0x5265c0>; | |
| qcom,supply-post-off-sleep = <0x02>; | |
| qcom,supply-name = "lcdbias"; | |
| qcom,supply-pre-on-sleep = <0x00>; | |
| qcom,supply-disable-load = <0x64>; | |
| }; | |
| }; | |
| }; | |
| qcom,msm-adsp-sensors { | |
| qcom,dst-id = <0x25c>; | |
| qcom,ib = <0x1f00000>; | |
| compatible = "qcom,msm-adsp-sensors"; | |
| qcom,ab = <0x1f00000>; | |
| qcom,src-id = <0x0b>; | |
| }; | |
| dsp_sharedmem { | |
| reg-names = "rfsa_dsp"; | |
| compatible = "qcom,sharedmem-uio"; | |
| reg = <0xfd60000 0x20000>; | |
| }; | |
| qcom,msm-adsp-loader { | |
| compatible = "qcom,adsp-loader"; | |
| qcom,adsp-state = <0x00>; | |
| }; | |
| android_usb@fe8050c8 { | |
| qcom,android-usb-swfi-latency = <0x01>; | |
| compatible = "qcom,android-usb"; | |
| reg = <0xfe8050c8 0xc8>; | |
| }; | |
| qcom,smp2pgpio_client_rdbg_2_out { | |
| gpios = <0x35 0x00 0x00>; | |
| compatible = "qcom,smp2pgpio_client_rdbg_2_out"; | |
| }; | |
| cti@fc342000 { | |
| reg-names = "cti-base"; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x1e>; | |
| compatible = "arm,coresight-cti"; | |
| reg = <0xfc342000 0x1000>; | |
| coresight-name = "coresight-cti-cpu1"; | |
| }; | |
| hob_ram@f500000 { | |
| compatible = "mmi,hob_ram"; | |
| reg = <0xf500000 0x40000 0xf540000 0x2000>; | |
| }; | |
| qcom,sdcc@f9824000 { | |
| qcom,pad-drv-off = <0x00 0x00 0x00>; | |
| qcom,bus-width = <0x08>; | |
| qcom,msm-bus,vectors-KBps = <0x4e 0x200 0x00 0x00 0x4e 0x200 0x640 0xc80 0x4e 0x200 0x13880 0x27100 0x4e 0x200 0x186a0 0x30d40 0x4e 0x200 0x30d40 0x61a80 0x4e 0x200 0x61a80 0xc3500 0x4e 0x200 0x61a80 0xc3500 0x4e 0x200 0x1f4000 0x3e8000>; | |
| qcom,vdd-current-level = <0x320 0x7a120>; | |
| qcom,pad-pull-on = <0x00 0x03 0x03>; | |
| qcom,msm-bus,num-cases = <0x08>; | |
| vdd-supply = <0x49>; | |
| qcom,vdd-lpm-sup; | |
| qcom,vdd-io-current-level = <0xfa 0x25990>; | |
| qcom,clk-rates = <0x61a80 0x17d7840 0x2faf080 0x5f5e100 0xbebc200>; | |
| reg-names = "core_mem\0dml_mem\0bam_mem"; | |
| interrupts = <0x00 0x7b 0x00 0x00 0x89 0x00>; | |
| qcom,bus-speed-mode = "HS200_1p8v\0DDR_1p8v"; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,bus-bw-vectors-bps = <0x00 0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100 0xbebc200 0xffffffff>; | |
| qcom,vdd-always-on; | |
| vdd-io-supply = <0x0b>; | |
| qcom,nonremovable; | |
| qcom,sup-voltages = <0xb86 0xb86>; | |
| qcom,pad-drv-on = <0x04 0x04 0x04>; | |
| status = "ok"; | |
| qcom,vdd-voltage-level = <0x2d0370 0x2d0370>; | |
| cell-index = <0x01>; | |
| compatible = "qcom,msm-sdcc"; | |
| qcom,pad-pull-off = <0x00 0x03 0x03>; | |
| qcom,vdd-io-voltage-level = <0x1b7740 0x1b7740>; | |
| reg = <0xf9824000 0x800 0xf9824800 0x100 0xf9804000 0x7000>; | |
| qcom,msm-bus,name = "sdcc1"; | |
| interrupt-names = "core_irq\0bam_irq"; | |
| qcom,vdd-io-always-on; | |
| }; | |
| qcom,smp2p-adsp { | |
| qcom,irq-bitmask = <0x400>; | |
| interrupts = <0x00 0x9e 0x01>; | |
| compatible = "qcom,smp2p"; | |
| qcom,remote-pid = <0x02>; | |
| reg = <0xf9011008 0x04>; | |
| }; | |
| qcom,lpass@fe200000 { | |
| qcom,gpio-err-ready = <0x54 0x01 0x00>; | |
| vdd_cx-supply = <0x1c>; | |
| reg-names = "qdsp6_base\0halt_base\0restart_reg"; | |
| interrupts = <0x00 0xa2 0x01>; | |
| qcom,gpio-err-fatal = <0x54 0x00 0x00>; | |
| qcom,gpio-force-stop = <0x55 0x00 0x00>; | |
| qcom,gpio-proxy-unvote = <0x54 0x02 0x00>; | |
| compatible = "qcom,pil-q6v5-lpass"; | |
| reg = <0xfe200000 0x100 0xfd485100 0x10 0xfc4016c0 0x04>; | |
| qcom,firmware-name = "adsp"; | |
| }; | |
| qcom,mpm2-sleep-counter@fc4a3000 { | |
| clock-frequency = <0x8000>; | |
| compatible = "qcom,mpm2-sleep-counter"; | |
| reg = <0xfc4a3000 0x1000>; | |
| }; | |
| cti@fc358000 { | |
| reg-names = "cti-base"; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x25>; | |
| compatible = "arm,coresight-cti"; | |
| reg = <0xfc358000 0x1000>; | |
| coresight-name = "coresight-cti-rpm-cpu0"; | |
| }; | |
| qcom,smp2p-modem { | |
| qcom,irq-bitmask = <0x4000>; | |
| interrupts = <0x00 0x1b 0x01>; | |
| compatible = "qcom,smp2p"; | |
| qcom,remote-pid = <0x01>; | |
| reg = <0xf9011008 0x04>; | |
| }; | |
| alsa_to_h2w { | |
| compatible = "mmi,alsa-to-h2w"; | |
| }; | |
| qcom,msm-pri-auxpcm { | |
| qcom,msm-cpudai-auxpcm-sync = <0x01 0x01>; | |
| qcom,msm-cpudai-auxpcm-data = <0x00 0x00>; | |
| qcom,msm-cpudai-auxpcm-pcm-clk-rate = <0x1f4000 0x1f4000>; | |
| qcom,msm-cpudai-auxpcm-quant = <0x02 0x02>; | |
| qcom,msm-cpudai-auxpcm-frame = <0x05 0x04>; | |
| qcom,msm-cpudai-auxpcm-slot = <0x01 0x01>; | |
| compatible = "qcom,msm-auxpcm-dev"; | |
| qcom,msm-auxpcm-interface = "primary"; | |
| qcom,msm-cpudai-auxpcm-mode = <0x00 0x00>; | |
| }; | |
| qcom,smp2pgpio_client_rdbg_2_in { | |
| gpios = <0x34 0x00 0x00>; | |
| compatible = "qcom,smp2pgpio_client_rdbg_2_in"; | |
| }; | |
| qcom,iommu@fe064000 { | |
| qcom,iommu-pmu-event-classes = <0x00 0x01 0x08 0x09 0x0a 0x10 0x11 0x12 0x80 0x81 0x82 0x83 0x90 0x91 0x92 0xb0 0xb1>; | |
| qcom,msm-bus,vectors-KBps = <0x34 0x200 0x00 0x00 0x34 0x200 0x00 0x3e8>; | |
| qcom,iommu-pmu-ngroups = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| qcom,iommu-bfb-data = <0x03 0x04 0x04 0x00 0x00 0x00 0x04 0x00 0x00 0x40 0x50 0x00 0x00>; | |
| reg-names = "iommu_base"; | |
| interrupts = <0x00 0xa6 0x00>; | |
| qcom,iommu-lpae-bfb-regs = <0x204c 0x2514 0x2540 0x256c 0x20ac 0x215c 0x220c 0x22bc 0x2314 0x2394 0x2414 0x2494 0x2008>; | |
| qcom,iommu-lpae-bfb-data = <0x03 0x00 0x04 0x04 0x00 0x0c 0x00 0x04 0x00 0x00 0x40 0x50 0x00>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| ranges; | |
| status = "disabled"; | |
| #address-cells = <0x01>; | |
| qcom,iommu-bfb-regs = <0x204c 0x2514 0x2540 0x256c 0x20ac 0x215c 0x220c 0x22bc 0x2314 0x2394 0x2414 0x2494 0x2008>; | |
| #size-cells = <0x01>; | |
| label = "lpass_core_iommu"; | |
| compatible = "qcom,msm-smmu-v1"; | |
| qcom,iommu-pmu-ncounters = <0x08>; | |
| reg = <0xfe064000 0x10000>; | |
| qcom,msm-bus,name = "lpass_core_ebi"; | |
| qcom,iommu-ctx@fe06c000 { | |
| interrupts = <0x00 0x10b 0x00>; | |
| qcom,iommu-ctx-sids = <0x00>; | |
| label = "lpass_core_cb_0"; | |
| compatible = "qcom,msm-smmu-v1-ctx"; | |
| reg = <0xfe06c000 0x1000>; | |
| }; | |
| qcom,iommu-ctx@fe06e000 { | |
| interrupts = <0x00 0x10b 0x00>; | |
| qcom,iommu-ctx-sids = <0x02>; | |
| label = "lpass_core_cb_2"; | |
| compatible = "qcom,msm-smmu-v1-ctx"; | |
| reg = <0xfe06e000 0x1000>; | |
| }; | |
| qcom,iommu-ctx@fe06d000 { | |
| interrupts = <0x00 0x10b 0x00>; | |
| qcom,iommu-ctx-sids = <0x01>; | |
| label = "lpass_core_cb_1"; | |
| compatible = "qcom,msm-smmu-v1-ctx"; | |
| reg = <0xfe06d000 0x1000>; | |
| }; | |
| }; | |
| csr@fc302000 { | |
| reg-names = "csr-base"; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x12>; | |
| qcom,blk-size = <0x01>; | |
| compatible = "qcom,coresight-csr"; | |
| reg = <0xfc302000 0x1000>; | |
| coresight-name = "coresight-csr"; | |
| }; | |
| qcom,cpp@fda04000 { | |
| vdd-supply = <0x06>; | |
| reg-names = "cpp\0cpp_vbif\0cpp_hw"; | |
| interrupts = <0x00 0x31 0x00>; | |
| cell-index = <0x00>; | |
| compatible = "qcom,cpp"; | |
| reg = <0xfda04000 0x100 0xfda40000 0x200 0xfda18000 0x18>; | |
| interrupt-names = "cpp"; | |
| }; | |
| qcom,smp2pgpio-ssr-smp2p-2-in { | |
| gpio-controller; | |
| #interrupt-cells = <0x02>; | |
| qcom,is-inbound; | |
| #gpio-cells = <0x02>; | |
| qcom,entry-name = "slave-kernel"; | |
| compatible = "qcom,smp2pgpio"; | |
| interrupt-controller; | |
| qcom,remote-pid = <0x02>; | |
| phandle = <0x54>; | |
| linux,phandle = <0x54>; | |
| }; | |
| qcom,gdsc@fc400404 { | |
| regulator-name = "gdsc_usb_hsic"; | |
| status = "ok"; | |
| compatible = "qcom,gdsc"; | |
| phandle = <0x3f>; | |
| reg = <0xfc400404 0x04>; | |
| linux,phandle = <0x3f>; | |
| }; | |
| qcom,msm-compress-dsp { | |
| compatible = "qcom,msm-compress-dsp"; | |
| }; | |
| qcom,ion { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,msm-ion"; | |
| qcom,ion-heap@28 { | |
| qcom,heap-align = <0x1000>; | |
| qcom,ion-heap-type = "CARVEOUT"; | |
| qcom,memory-reservation-size = "\01@"; | |
| qcom,memory-reservation-type = "EBI1"; | |
| compatible = "qcom,msm-ion-reserve"; | |
| reg = <0x1c>; | |
| }; | |
| qcom,ion-heap@27 { | |
| qcom,ion-heap-type = "DMA"; | |
| linux,contiguous-region = <0x04>; | |
| compatible = "qcom,msm-ion-reserve"; | |
| reg = <0x1b>; | |
| }; | |
| qcom,ion-heap@22 { | |
| qcom,heap-align = <0x1000>; | |
| qcom,ion-heap-type = "DMA"; | |
| linux,contiguous-region = <0x03>; | |
| compatible = "qcom,msm-ion-reserve"; | |
| reg = <0x16>; | |
| }; | |
| qcom,ion-heap@21 { | |
| qcom,ion-heap-type = "SYSTEM_CONTIG"; | |
| reg = <0x15>; | |
| }; | |
| qcom,ion-heap@25 { | |
| qcom,ion-heap-type = "SYSTEM"; | |
| reg = <0x19>; | |
| }; | |
| qcom,ion-heap@8 { | |
| qcom,default-prefetch-size = <0x3c00000>; | |
| qcom,heap-align = <0x1000>; | |
| qcom,ion-heap-type = "SECURE_DMA"; | |
| linux,contiguous-region = <0x02>; | |
| compatible = "qcom,msm-ion-reserve"; | |
| reg = <0x08>; | |
| }; | |
| qcom,ion-heap@23 { | |
| qcom,heap-align = <0x1000>; | |
| qcom,ion-heap-type = "CARVEOUT"; | |
| qcom,memory-fixed = <0xdc00000 0x1900000>; | |
| compatible = "qcom,msm-ion-reserve"; | |
| reg = <0x17>; | |
| }; | |
| }; | |
| qcom,mdss_wb_panel { | |
| qcom,mdss_pan_bpp = <0x18>; | |
| status = "disabled"; | |
| qcom,mdss-fb-map = <0x25>; | |
| compatible = "qcom,mdss_wb"; | |
| qcom,mdss_pan_res = <0x500 0x2d0>; | |
| }; | |
| qcom,iommu@f9bc4000 { | |
| qcom,iommu-pmu-event-classes = <0x00 0x01 0x08 0x09 0x0a 0x10 0x11 0x12 0x80 0x81 0x82 0x83 0x90 0x91 0x92 0xb0 0xb1>; | |
| qcom,msm-bus,vectors-KBps = <0x58 0x200 0x00 0x00 0x58 0x200 0x00 0x3e8>; | |
| qcom,iommu-pmu-ngroups = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| qcom,iommu-bfb-data = <0x03 0x04 0x04 0x00 0x00 0x00 0x01 0x00 0x00 0x40 0x44 0x00 0x00>; | |
| reg-names = "iommu_base"; | |
| interrupts = <0x00 0x99 0x00>; | |
| qcom,iommu-lpae-bfb-regs = <0x204c 0x2514 0x2540 0x256c 0x20ac 0x215c 0x220c 0x22bc 0x2314 0x2394 0x2414 0x2494 0x2008>; | |
| qcom,iommu-lpae-bfb-data = <0x03 0x00 0x04 0x04 0x00 0x05 0x00 0x01 0x00 0x00 0x40 0x44 0x00>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| ranges; | |
| status = "disabled"; | |
| #address-cells = <0x01>; | |
| qcom,iommu-bfb-regs = <0x204c 0x2514 0x2540 0x256c 0x20ac 0x215c 0x220c 0x22bc 0x2314 0x2394 0x2414 0x2494 0x2008>; | |
| #size-cells = <0x01>; | |
| label = "copss_iommu"; | |
| compatible = "qcom,msm-smmu-v1"; | |
| qcom,iommu-pmu-ncounters = <0x08>; | |
| reg = <0xf9bc4000 0x10000>; | |
| qcom,msm-bus,name = "copss_ebi"; | |
| qcom,iommu-ctx@f9bd0000 { | |
| interrupts = <0x00 0x8e 0x00>; | |
| qcom,iommu-ctx-sids = <0x04>; | |
| label = "copss_cb_4"; | |
| compatible = "qcom,msm-smmu-v1-ctx"; | |
| reg = <0xf9bd0000 0x1000>; | |
| }; | |
| qcom,iommu-ctx@f9bcc000 { | |
| interrupts = <0x00 0x8e 0x00>; | |
| qcom,iommu-ctx-sids = <0x00>; | |
| label = "copss_cb_0"; | |
| compatible = "qcom,msm-smmu-v1-ctx"; | |
| reg = <0xf9bcc000 0x1000>; | |
| }; | |
| qcom,iommu-ctx@f9bcf000 { | |
| interrupts = <0x00 0x8e 0x00>; | |
| qcom,iommu-ctx-sids = <0x03>; | |
| label = "copss_cb_3"; | |
| compatible = "qcom,msm-smmu-v1-ctx"; | |
| reg = <0xf9bcf000 0x1000>; | |
| }; | |
| qcom,iommu-ctx@f9bd2000 { | |
| interrupts = <0x00 0x8e 0x00>; | |
| qcom,iommu-ctx-sids = <0x06>; | |
| label = "copss_cb_6"; | |
| compatible = "qcom,msm-smmu-v1-ctx"; | |
| reg = <0xf9bd2000 0x1000>; | |
| }; | |
| qcom,iommu-ctx@f9bcd000 { | |
| interrupts = <0x00 0x8e 0x00>; | |
| qcom,iommu-ctx-sids = <0x01>; | |
| label = "copss_cb_1"; | |
| compatible = "qcom,msm-smmu-v1-ctx"; | |
| reg = <0xf9bcd000 0x1000>; | |
| }; | |
| qcom,iommu-ctx@f9bce000 { | |
| interrupts = <0x00 0x8e 0x00>; | |
| qcom,iommu-ctx-sids = <0x02>; | |
| label = "copss_cb_2"; | |
| compatible = "qcom,msm-smmu-v1-ctx"; | |
| reg = <0xf9bce000 0x1000>; | |
| }; | |
| qcom,iommu-ctx@f9bd1000 { | |
| interrupts = <0x00 0x8e 0x00>; | |
| qcom,iommu-ctx-sids = <0x05>; | |
| label = "copss_cb_5"; | |
| compatible = "qcom,msm-smmu-v1-ctx"; | |
| reg = <0xf9bd1000 0x1000>; | |
| }; | |
| qcom,iommu-ctx@f9bd3000 { | |
| interrupts = <0x00 0x8e 0x00>; | |
| qcom,iommu-ctx-sids = <0x07>; | |
| label = "copss_cb_7"; | |
| compatible = "qcom,msm-smmu-v1-ctx"; | |
| reg = <0xf9bd3000 0x1000>; | |
| }; | |
| }; | |
| timer@f9020000 { | |
| ranges; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| clock-frequency = <0x124f800>; | |
| compatible = "arm,armv7-timer-mem"; | |
| reg = <0xf9020000 0x1000>; | |
| frame@f9023000 { | |
| interrupts = <0x00 0x09 0x04>; | |
| frame-number = <0x01>; | |
| status = "disabled"; | |
| reg = <0xf9023000 0x1000>; | |
| }; | |
| frame@f9024000 { | |
| interrupts = <0x00 0x0a 0x04>; | |
| frame-number = <0x02>; | |
| status = "disabled"; | |
| reg = <0xf9024000 0x1000>; | |
| }; | |
| frame@f9028000 { | |
| interrupts = <0x00 0x0e 0x04>; | |
| frame-number = <0x06>; | |
| status = "disabled"; | |
| reg = <0xf9028000 0x1000>; | |
| }; | |
| frame@f9026000 { | |
| interrupts = <0x00 0x0c 0x04>; | |
| frame-number = <0x04>; | |
| status = "disabled"; | |
| reg = <0xf9026000 0x1000>; | |
| }; | |
| frame@f9025000 { | |
| interrupts = <0x00 0x0b 0x04>; | |
| frame-number = <0x03>; | |
| status = "disabled"; | |
| reg = <0xf9025000 0x1000>; | |
| }; | |
| frame@f9021000 { | |
| interrupts = <0x00 0x08 0x04 0x00 0x07 0x04>; | |
| frame-number = <0x00>; | |
| reg = <0xf9021000 0x1000 0xf9022000 0x1000>; | |
| }; | |
| frame@f9027000 { | |
| interrupts = <0x00 0x0d 0x04>; | |
| frame-number = <0x05>; | |
| status = "disabled"; | |
| reg = <0xf9027000 0x1000>; | |
| }; | |
| }; | |
| qcom,gdsc@fc401b44 { | |
| regulator-name = "gdsc_pcie_1"; | |
| status = "disabled"; | |
| compatible = "qcom,gdsc"; | |
| reg = <0xfc401b44 0x04>; | |
| }; | |
| qcom,msm-voip-dsp { | |
| compatible = "qcom,msm-voip-dsp"; | |
| }; | |
| etm@fc33d000 { | |
| reg-names = "etm-base"; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x0b>; | |
| coresight-child-list = <0x30>; | |
| coresight-outports = <0x00>; | |
| coresight-child-ports = <0x01>; | |
| qcom,round-robin; | |
| compatible = "arm,coresight-etm"; | |
| reg = <0xfc33d000 0x1000>; | |
| coresight-name = "coresight-etm1"; | |
| }; | |
| qcom,iommu@fda44000 { | |
| qcom,iommu-pmu-event-classes = <0x00 0x01 0x08 0x09 0x0a 0x10 0x11 0x12 0x80 0x81 0x82 0x83 0x90 0x91 0x92 0xb0 0xb1>; | |
| qcom,msm-bus,vectors-KBps = <0x1d 0x200 0x00 0x00 0x1d 0x200 0x00 0x3e8>; | |
| qcom,iommu-pmu-ngroups = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| vdd-supply = <0x06>; | |
| qcom,iommu-bfb-data = <0xffffffff 0x00 0x04 0x08 0x00 0x00 0x1b 0x5b 0x00 0x1b 0x2b 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; | |
| qcom,needs-alt-core-clk; | |
| reg-names = "iommu_base"; | |
| interrupts = <0x00 0x3e 0x00>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| ranges; | |
| status = "ok"; | |
| #address-cells = <0x01>; | |
| qcom,iommu-bfb-regs = <0x204c 0x2050 0x2514 0x2540 0x256c 0x2314 0x2394 0x2414 0x20ac 0x215c 0x220c 0x2008 0x200c 0x2010 0x2014 0x2018 0x201c 0x2020>; | |
| #size-cells = <0x01>; | |
| label = "vfe_iommu"; | |
| compatible = "qcom,msm-smmu-v1"; | |
| qcom,iommu-pmu-ncounters = <0x08>; | |
| reg = <0xfda44000 0x10000>; | |
| qcom,msm-bus,name = "vfe_ebi"; | |
| qcom,iommu-enable-halt; | |
| qcom,iommu-ctx@fda4d000 { | |
| interrupts = <0x00 0x41 0x00>; | |
| qcom,iommu-ctx-sids = <0x01>; | |
| label = "vfe1"; | |
| compatible = "qcom,msm-smmu-v1-ctx"; | |
| reg = <0xfda4d000 0x1000>; | |
| }; | |
| qcom,iommu-ctx@fda4c000 { | |
| interrupts = <0x00 0x41 0x00>; | |
| qcom,iommu-ctx-sids = <0x00>; | |
| label = "vfe0"; | |
| compatible = "qcom,msm-smmu-v1-ctx"; | |
| reg = <0xfda4c000 0x1000>; | |
| }; | |
| qcom,iommu-ctx@fda4e000 { | |
| interrupts = <0x00 0x41 0x00>; | |
| qcom,iommu-ctx-sids = <0x02>; | |
| label = "cpp"; | |
| compatible = "qcom,msm-smmu-v1-ctx"; | |
| reg = <0xfda4e000 0x1000>; | |
| }; | |
| }; | |
| qcom,kgsl-3d0@fdb00000 { | |
| qcom,msm-bus,vectors-KBps = <0x1a 0x200 0x00 0x00 0x59 0x25c 0x00 0x00 0x1a 0x200 0xc3500 0x186a00 0x59 0x25c 0x00 0x30d400 0x1a 0x200 0x186a00 0x30d400 0x59 0x25c 0x00 0x4e2000 0x1a 0x200 0x207880 0x40f100 0x59 0x25c 0x00 0x61a800>; | |
| qcom,msm-bus,num-cases = <0x04>; | |
| vdd-supply = <0x11>; | |
| qcom,idle-timeout = <0x08>; | |
| reg-names = "kgsl_3d0_reg_memory\0kgsl_3d0_shader_memory"; | |
| interrupts = <0x00 0x21 0x00>; | |
| qcom,msm-bus,num-paths = <0x02>; | |
| iommu = <0x1b>; | |
| qcom,clk-map = <0x16>; | |
| vddcx-supply = [00 00]; | |
| qcom,initial-pwrlevel = <0x01>; | |
| label = "kgsl-3d0"; | |
| compatible = "qcom,kgsl-3d0\0qcom,kgsl-3d"; | |
| qcom,id = <0x00>; | |
| qcom,chipid = <0x3000512>; | |
| qcom,strtstp-sleepwake; | |
| reg = <0xfdb00000 0x10000 0xfdb20000 0x10000>; | |
| qcom,msm-bus,name = "grp3d"; | |
| interrupt-names = "kgsl_3d0_irq"; | |
| qcom,gpu-pwrlevels { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,gpu-pwrlevels"; | |
| qcom,gpu-pwrlevel@3 { | |
| qcom,io-fraction = <0x00>; | |
| qcom,gpu-freq = <0x121eac0>; | |
| qcom,bus-freq = <0x00>; | |
| reg = <0x03>; | |
| }; | |
| qcom,gpu-pwrlevel@0 { | |
| qcom,io-fraction = <0x00>; | |
| qcom,gpu-freq = <0x1ad27480>; | |
| qcom,bus-freq = <0x03>; | |
| reg = <0x00>; | |
| }; | |
| qcom,gpu-pwrlevel@1 { | |
| qcom,io-fraction = <0x21>; | |
| qcom,gpu-freq = <0x1312d000>; | |
| qcom,bus-freq = <0x02>; | |
| reg = <0x01>; | |
| }; | |
| qcom,gpu-pwrlevel@2 { | |
| qcom,io-fraction = <0x64>; | |
| qcom,gpu-freq = <0xbebc200>; | |
| qcom,bus-freq = <0x01>; | |
| reg = <0x02>; | |
| }; | |
| }; | |
| qcom,dcvs-core-info { | |
| qcom,algo-ss-win-size-min-us = <0xf4240>; | |
| qcom,algo-slack-time-min-us = <0x9858>; | |
| qcom,energy-leakage-coeff-d = <0x00>; | |
| qcom,energy-active-coeff-b = <0x00>; | |
| qcom,algo-em-max-util-pct = <0x61>; | |
| qcom,sensors = <0x00>; | |
| qcom,num-cores = <0x01>; | |
| qcom,power-current-temp = <0x19>; | |
| qcom,algo-ss-util-pct = <0x5f>; | |
| qcom,algo-em-win-size-min-us = <0x186a0>; | |
| qcom,algo-slack-weight-thresh-pct = <0x00>; | |
| qcom,energy-leakage-coeff-b = <0x265de>; | |
| qcom,energy-leakage-coeff-a = <0x0b>; | |
| qcom,algo-ss-no-corr-below-freq = <0x00>; | |
| qcom,energy-active-coeff-c = <0x00>; | |
| qcom,energy-active-coeff-a = <0x9bc>; | |
| #address-cells = <0x01>; | |
| qcom,algo-max-freq-chg-time-us = <0x186a0>; | |
| qcom,core-core-type = <0x01>; | |
| qcom,power-num-freq = <0x04>; | |
| qcom,algo-disable-pc-threshold = <0x00>; | |
| #size-cells = <0x00>; | |
| qcom,algo-group-id = <0x5f>; | |
| qcom,algo-slack-mode-dynamic = <0x186a0>; | |
| compatible = "qcom,dcvs-core-info"; | |
| qcom,algo-ss-win-size-max-us = <0xf4240>; | |
| qcom,energy-leakage-coeff-c = <0x00>; | |
| qcom,algo-em-win-size-max-us = <0x493e0>; | |
| qcom,algo-slack-time-max-us = <0x9858>; | |
| qcom,dcvs-freq@1 { | |
| qcom,active-energy-offset = <0x64>; | |
| qcom,leakage-energy-offset = <0x00>; | |
| qcom,freq = <0x00>; | |
| qcom,voltage = <0x00>; | |
| qcom,is_trans_level = <0x00>; | |
| reg = <0x01>; | |
| }; | |
| qcom,dcvs-freq@3 { | |
| qcom,active-energy-offset = <0xce301>; | |
| qcom,leakage-energy-offset = <0x00>; | |
| qcom,freq = <0x00>; | |
| qcom,voltage = <0x00>; | |
| qcom,is_trans_level = <0x00>; | |
| reg = <0x03>; | |
| }; | |
| qcom,dcvs-freq@0 { | |
| qcom,active-energy-offset = <0x64>; | |
| qcom,leakage-energy-offset = <0x00>; | |
| qcom,freq = <0x00>; | |
| qcom,voltage = <0x00>; | |
| qcom,is_trans_level = <0x00>; | |
| reg = <0x00>; | |
| }; | |
| qcom,dcvs-freq@2 { | |
| qcom,active-energy-offset = <0x64>; | |
| qcom,leakage-energy-offset = <0x00>; | |
| qcom,freq = <0x00>; | |
| qcom,voltage = <0x00>; | |
| qcom,is_trans_level = <0x00>; | |
| reg = <0x02>; | |
| }; | |
| }; | |
| }; | |
| msm-config-noc@fc480000 { | |
| qcom,hw-sel = "NoC"; | |
| qcom,fabclk-dual = "bus_clk"; | |
| qcom,rpm-en; | |
| cell-id = <0x1400>; | |
| qcom,ntieredslaves = <0x00>; | |
| qcom,fabclk-active = "bus_a_clk"; | |
| label = "msm_config_noc"; | |
| compatible = "msm-bus-fabric"; | |
| reg = <0xfc480000 0x4000>; | |
| slv-ebi1-phy-cfg { | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x18>; | |
| qcom,slv-hw-id = <0x49>; | |
| cell-id = <0x285>; | |
| label = "slv-ebi1-phy-cfg"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-cnoc-mnoc-cfg { | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x13>; | |
| qcom,slv-hw-id = <0x42>; | |
| cell-id = <0x280>; | |
| label = "slv-cnoc-mnoc-cfg"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-pnoc-cfg { | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x15>; | |
| qcom,slv-hw-id = <0x45>; | |
| cell-id = <0x281>; | |
| label = "slv-pnoc-cfg"; | |
| qcom,tier = <0x02>; | |
| }; | |
| mas-qdss-dsp { | |
| qcom,masterp = <0x04>; | |
| qcom,buswidth = <0x08>; | |
| qcom,mas-hw-id = <0x31>; | |
| cell-id = <0x4c>; | |
| label = "mas-qdss-dap"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-phy-apu-cfg { | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x17>; | |
| qcom,slv-hw-id = <0x48>; | |
| cell-id = <0x284>; | |
| label = "slv-phy-apu-cfg"; | |
| qcom,tier = <0x02>; | |
| }; | |
| mas-rpm-sys { | |
| qcom,masterp = <0x02>; | |
| qcom,buswidth = <0x08>; | |
| qcom,mas-hw-id = <0x2f>; | |
| cell-id = <0x4a>; | |
| label = "mas-rpm-sys"; | |
| qcom,tier = <0x02>; | |
| }; | |
| mas-tic { | |
| qcom,masterp = <0x06>; | |
| qcom,buswidth = <0x08>; | |
| qcom,mas-hw-id = <0x33>; | |
| cell-id = <0x4d>; | |
| label = "mas-tic"; | |
| qcom,tier = <0x02>; | |
| }; | |
| mas-dehr { | |
| qcom,masterp = <0x03>; | |
| qcom,buswidth = <0x08>; | |
| qcom,mas-hw-id = <0x30>; | |
| cell-id = <0x4b>; | |
| label = "mas-dehr"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-bimc-cfg { | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x09>; | |
| qcom,slv-hw-id = <0x38>; | |
| cell-id = <0x275>; | |
| label = "slv-bimc-cfg"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-dehr-cfg { | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x0e>; | |
| qcom,slv-hw-id = <0x3d>; | |
| cell-id = <0x27a>; | |
| label = "slv-dehr-cfg"; | |
| qcom,tier = <0x02>; | |
| }; | |
| mas-rpm-inst { | |
| qcom,masterp = <0x00>; | |
| qcom,buswidth = <0x08>; | |
| qcom,mas-hw-id = <0x2d>; | |
| cell-id = <0x48>; | |
| label = "mas-rpm-inst"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-security { | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x03>; | |
| qcom,slv-hw-id = <0x31>; | |
| cell-id = <0x26e>; | |
| label = "slv-security"; | |
| qcom,tier = <0x02>; | |
| }; | |
| mas-spdm { | |
| qcom,masterp = <0x05>; | |
| qcom,buswidth = <0x08>; | |
| qcom,mas-hw-id = <0x32>; | |
| cell-id = <0x24>; | |
| label = "mas-spdm"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-clk-ctl { | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x01>; | |
| qcom,slv-hw-id = <0x2f>; | |
| cell-id = <0x26c>; | |
| label = "slv-clk-ctl"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-boot-rom { | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x0a>; | |
| qcom,slv-hw-id = <0x39>; | |
| cell-id = <0x276>; | |
| label = "slv-boot-rom"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-rbcpr-cfg { | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x11>; | |
| qcom,slv-hw-id = <0x40>; | |
| cell-id = <0x27c>; | |
| label = "slv-rbcpr-cfg"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-rpm { | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x19>; | |
| qcom,slv-hw-id = <0x4a>; | |
| cell-id = <0x216>; | |
| label = "slv-rpm"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-snoc-mpu-cfg { | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x14>; | |
| qcom,slv-hw-id = <0x43>; | |
| cell-id = <0x27e>; | |
| label = "slv-snoc-mpu-cfg"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-service-cnoc { | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x1b>; | |
| qcom,slv-hw-id = <0x4c>; | |
| cell-id = <0x286>; | |
| label = "slv-service-cnoc"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-tlmm { | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x05>; | |
| qcom,slv-hw-id = <0x33>; | |
| cell-id = <0x270>; | |
| label = "slv-tlmm"; | |
| qcom,tier = <0x02>; | |
| }; | |
| mas-rpm-data { | |
| qcom,masterp = <0x01>; | |
| qcom,buswidth = <0x08>; | |
| qcom,mas-hw-id = <0x2e>; | |
| cell-id = <0x49>; | |
| label = "mas-rpm-data"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-mpm { | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x0f>; | |
| qcom,slv-hw-id = <0x3e>; | |
| cell-id = <0x218>; | |
| label = "slv-mpm"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-imem-cfg { | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x07>; | |
| qcom,slv-hw-id = <0x36>; | |
| cell-id = <0x273>; | |
| label = "slv-imem-cfg"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-tcsr { | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x04>; | |
| qcom,slv-hw-id = <0x32>; | |
| cell-id = <0x26f>; | |
| label = "slv-tcsr"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-qdss-cfg { | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x10>; | |
| qcom,slv-hw-id = <0x3f>; | |
| cell-id = <0x27b>; | |
| label = "slv-qdss-cfg"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-message-ram { | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x08>; | |
| qcom,slv-hw-id = <0x37>; | |
| cell-id = <0x274>; | |
| label = "slv-message-ram"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-cnoc-mnoc-mmss-cfg { | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x0b>; | |
| qcom,slv-hw-id = <0x3a>; | |
| cell-id = <0x277>; | |
| label = "slv-cnoc-mnoc-mmss-cfg"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-cnoc-mss { | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x02>; | |
| qcom,slv-hw-id = <0x30>; | |
| cell-id = <0x26d>; | |
| label = "slv-cnoc-mss"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-pmic-arb { | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x0c>; | |
| qcom,slv-hw-id = <0x3b>; | |
| cell-id = <0x278>; | |
| label = "slv-pmic-arb"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-crypto-0-cfg { | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x06>; | |
| qcom,slv-hw-id = <0x34>; | |
| cell-id = <0x271>; | |
| label = "slv-crypto-0-cfg"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-rbcpr-qdss-apu-cfg { | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x12>; | |
| qcom,slv-hw-id = <0x41>; | |
| cell-id = <0x27d>; | |
| label = "slv-rbcpr-qdss-apu-cfg"; | |
| qcom,tier = <0x02>; | |
| }; | |
| fab-snoc { | |
| qcom,masterp = <0x07>; | |
| qcom,gateway; | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x1a>; | |
| qcom,slv-hw-id = <0x4b>; | |
| qcom,mas-hw-id = <0x34>; | |
| cell-id = <0x400>; | |
| label = "fab-snoc"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-snoc-cfg { | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x16>; | |
| qcom,slv-hw-id = <0x46>; | |
| cell-id = <0x282>; | |
| label = "slv-snoc-cfg"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-spdm-wrapper { | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x0d>; | |
| qcom,slv-hw-id = <0x3c>; | |
| cell-id = <0x279>; | |
| label = "slv-spdm-wrapper"; | |
| qcom,tier = <0x02>; | |
| }; | |
| }; | |
| gpiomux { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| compatible = "qcom,msm8x26-pinmux"; | |
| pin@fd51290 { | |
| qcom,pin-num = <0x29>; | |
| reg = <0xfd511290 0x10>; | |
| qcom,active@0 { | |
| qcom,func = <0x01>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x03>; | |
| }; | |
| qcom,suspend@1 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x03>; | |
| }; | |
| }; | |
| pin@fd51330 { | |
| qcom,pin-num = <0x33>; | |
| reg = <0xfd511330 0x10>; | |
| qcom,active@0 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x00>; | |
| }; | |
| qcom,suspend@1 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x00>; | |
| }; | |
| }; | |
| pin@fd51210 { | |
| qcom,pin-keep-state; | |
| qcom,pin-num = <0x21>; | |
| reg = <0xfd511210 0x10>; | |
| qcom,active@0 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x01>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x00>; | |
| }; | |
| qcom,suspend@1 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x00>; | |
| }; | |
| }; | |
| pin@fd51130 { | |
| qcom,pin-num = <0x13>; | |
| reg = <0xfd511130 0x10>; | |
| qcom,active@0 { | |
| qcom,func = <0x03>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x00>; | |
| }; | |
| qcom,suspend@1 { | |
| qcom,func = <0x03>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x00>; | |
| }; | |
| }; | |
| pin@fd51000 { | |
| qcom,pin-num = <0x00>; | |
| reg = <0xfd511000 0x10>; | |
| qcom,active@0 { | |
| qcom,func = <0x01>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x03>; | |
| qcom,pull = <0x00>; | |
| }; | |
| qcom,suspend@1 { | |
| qcom,func = <0x01>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x03>; | |
| qcom,pull = <0x00>; | |
| }; | |
| }; | |
| pin@fd51100 { | |
| qcom,pin-num = <0x10>; | |
| reg = <0xfd511100 0x10>; | |
| qcom,active@0 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x01>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x03>; | |
| }; | |
| qcom,suspend@1 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x01>; | |
| }; | |
| }; | |
| pin@fd516d0 { | |
| qcom,pin-num = <0x6d>; | |
| reg = <0xfd5116d0 0x10>; | |
| qcom,active@0 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x00>; | |
| }; | |
| qcom,suspend@1 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x00>; | |
| }; | |
| }; | |
| pin@fd510b0 { | |
| qcom,pin-num = <0x0b>; | |
| reg = <0xfd5110b0 0x10>; | |
| qcom,active@0 { | |
| qcom,func = <0x03>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x00>; | |
| }; | |
| qcom,suspend@1 { | |
| qcom,func = <0x03>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x00>; | |
| }; | |
| }; | |
| pin@fd51250 { | |
| qcom,pin-num = <0x25>; | |
| reg = <0xfd511250 0x10>; | |
| qcom,active@0 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x00>; | |
| }; | |
| qcom,suspend@1 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x01>; | |
| }; | |
| }; | |
| pin@fd513e0 { | |
| qcom,pin-num = <0x3e>; | |
| reg = <0xfd5113e0 0x10>; | |
| qcom,active@0 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x01>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x00>; | |
| }; | |
| qcom,suspend@1 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x01>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x00>; | |
| }; | |
| }; | |
| pin@fd51220 { | |
| qcom,pin-keep-state; | |
| qcom,pin-num = <0x22>; | |
| reg = <0xfd511220 0x10>; | |
| qcom,active@0 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x01>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x00>; | |
| }; | |
| qcom,suspend@1 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x01>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x00>; | |
| }; | |
| }; | |
| pin@fd51060 { | |
| qcom,pin-num = <0x06>; | |
| reg = <0xfd511060 0x10>; | |
| qcom,active@0 { | |
| qcom,func = <0x03>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x00>; | |
| }; | |
| qcom,suspend@1 { | |
| qcom,func = <0x03>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x00>; | |
| }; | |
| }; | |
| pin@fd51260 { | |
| qcom,pin-num = <0x26>; | |
| reg = <0xfd511260 0x10>; | |
| qcom,active@0 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x00>; | |
| }; | |
| qcom,suspend@1 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x03>; | |
| }; | |
| }; | |
| pin@fd51240 { | |
| qcom,pin-num = <0x24>; | |
| reg = <0xfd511240 0x10>; | |
| qcom,active@0 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x00>; | |
| }; | |
| qcom,suspend@1 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x01>; | |
| }; | |
| }; | |
| pin@fd5116a0 { | |
| qcom,pin-num = <0x6a>; | |
| reg = <0xfd5116a0 0x10>; | |
| qcom,active@0 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x03>; | |
| }; | |
| qcom,suspend@1 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x00>; | |
| }; | |
| }; | |
| pin@fd51030 { | |
| qcom,pin-num = <0x03>; | |
| reg = <0xfd511030 0x10>; | |
| qcom,active@0 { | |
| qcom,func = <0x01>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x03>; | |
| qcom,pull = <0x00>; | |
| }; | |
| qcom,suspend@1 { | |
| qcom,func = <0x01>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x03>; | |
| qcom,pull = <0x00>; | |
| }; | |
| }; | |
| pin@fd51040 { | |
| qcom,pin-num = <0x04>; | |
| reg = <0xfd511040 0x10>; | |
| qcom,active@0 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x03>; | |
| }; | |
| qcom,suspend@1 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x03>; | |
| }; | |
| }; | |
| pin@fd510d0 { | |
| qcom,pin-num = <0x0d>; | |
| reg = <0xfd5110d0 0x10>; | |
| qcom,active@0 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x00>; | |
| }; | |
| qcom,suspend@1 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x00>; | |
| }; | |
| }; | |
| pin@fd51020 { | |
| qcom,pin-num = <0x02>; | |
| reg = <0xfd511020 0x10>; | |
| qcom,active@0 { | |
| qcom,func = <0x01>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x03>; | |
| qcom,pull = <0x00>; | |
| }; | |
| qcom,suspend@1 { | |
| qcom,func = <0x01>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x03>; | |
| qcom,pull = <0x00>; | |
| }; | |
| }; | |
| pin@fd511b0 { | |
| qcom,pin-num = <0x1b>; | |
| reg = <0xfd5111b0 0x10>; | |
| qcom,active@0 { | |
| qcom,func = <0x01>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x02>; | |
| qcom,pull = <0x00>; | |
| }; | |
| qcom,suspend@1 { | |
| qcom,func = <0x01>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x01>; | |
| }; | |
| }; | |
| pin@fd510a0 { | |
| qcom,pin-num = <0x0a>; | |
| reg = <0xfd5110a0 0x10>; | |
| qcom,active@0 { | |
| qcom,func = <0x03>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x00>; | |
| }; | |
| qcom,suspend@1 { | |
| qcom,func = <0x03>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x00>; | |
| }; | |
| }; | |
| pin@fd51190 { | |
| qcom,pin-keep-state; | |
| qcom,pin-num = <0x19>; | |
| reg = <0xfd511190 0x10>; | |
| qcom,active@0 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x01>; | |
| qcom,drv = <0x03>; | |
| qcom,pull = <0x00>; | |
| }; | |
| qcom,suspend@1 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x01>; | |
| }; | |
| }; | |
| pin@fd512b0 { | |
| qcom,pin-num = <0x2b>; | |
| reg = <0xfd5112b0 0x10>; | |
| qcom,active@0 { | |
| qcom,func = <0x01>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x03>; | |
| }; | |
| qcom,suspend@1 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x03>; | |
| }; | |
| }; | |
| pin@fd511f0 { | |
| qcom,pin-keep-state; | |
| qcom,pin-num = <0x1f>; | |
| reg = <0xfd5111f0 0x10>; | |
| qcom,active@0 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x01>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x00>; | |
| }; | |
| qcom,suspend@1 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x00>; | |
| }; | |
| }; | |
| pin@fd511a0 { | |
| qcom,pin-num = <0x1a>; | |
| reg = <0xfd5111a0 0x10>; | |
| qcom,active@0 { | |
| qcom,func = <0x01>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x02>; | |
| qcom,pull = <0x00>; | |
| }; | |
| qcom,suspend@1 { | |
| qcom,func = <0x01>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x01>; | |
| }; | |
| }; | |
| pin@fd510e0 { | |
| qcom,pin-num = <0x0e>; | |
| reg = <0xfd5110e0 0x10>; | |
| qcom,active@0 { | |
| qcom,func = <0x03>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x00>; | |
| }; | |
| qcom,suspend@1 { | |
| qcom,func = <0x03>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x00>; | |
| }; | |
| }; | |
| pin@fd512a0 { | |
| qcom,pin-num = <0x2a>; | |
| reg = <0xfd5112a0 0x10>; | |
| qcom,active@0 { | |
| qcom,func = <0x01>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x03>; | |
| }; | |
| qcom,suspend@1 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x03>; | |
| }; | |
| }; | |
| pin@fd511e0 { | |
| qcom,pin-num = <0x1e>; | |
| reg = <0xfd5111e0 0x10>; | |
| qcom,active@0 { | |
| qcom,func = <0x01>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x00>; | |
| }; | |
| qcom,suspend@1 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x00>; | |
| }; | |
| }; | |
| pin@fd51700 { | |
| qcom,pin-num = <0x70>; | |
| reg = <0xfd511700 0x10>; | |
| qcom,active@0 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x03>; | |
| }; | |
| qcom,suspend@1 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x03>; | |
| }; | |
| }; | |
| pin@fd512c0 { | |
| qcom,pin-num = <0x2c>; | |
| reg = <0xfd5112c0 0x10>; | |
| qcom,active@0 { | |
| qcom,func = <0x01>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x03>; | |
| }; | |
| qcom,suspend@1 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x03>; | |
| }; | |
| }; | |
| pin@fd51230 { | |
| qcom,pin-num = <0x23>; | |
| reg = <0xfd511230 0x10>; | |
| qcom,active@0 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x00>; | |
| }; | |
| qcom,suspend@1 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x01>; | |
| }; | |
| }; | |
| pin@fd51110 { | |
| qcom,pin-num = <0x11>; | |
| reg = <0xfd511110 0x10>; | |
| qcom,active@0 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x03>; | |
| }; | |
| qcom,suspend@1 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x01>; | |
| }; | |
| }; | |
| pin@fd51010 { | |
| qcom,pin-num = <0x01>; | |
| reg = <0xfd511010 0x10>; | |
| qcom,active@0 { | |
| qcom,func = <0x01>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x03>; | |
| qcom,pull = <0x00>; | |
| }; | |
| qcom,suspend@1 { | |
| qcom,func = <0x01>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x03>; | |
| qcom,pull = <0x00>; | |
| }; | |
| }; | |
| pin@fd516f0 { | |
| qcom,pin-num = <0x6f>; | |
| reg = <0xfd5116f0 0x10>; | |
| qcom,active@0 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x03>; | |
| }; | |
| qcom,suspend@1 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x03>; | |
| }; | |
| }; | |
| pin@fd51400 { | |
| qcom,pin-num = <0x40>; | |
| reg = <0xfd511400 0x10>; | |
| qcom,active@0 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x00>; | |
| }; | |
| qcom,suspend@1 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x00>; | |
| }; | |
| }; | |
| pin@fd513f0 { | |
| qcom,pin-num = <0x3f>; | |
| reg = <0xfd5113f0 0x10>; | |
| qcom,active@0 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x00>; | |
| }; | |
| qcom,suspend@1 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x00>; | |
| }; | |
| }; | |
| pin@fd51720 { | |
| qcom,pin-num = <0x72>; | |
| reg = <0xfd511720 0x10>; | |
| qcom,active@0 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x00>; | |
| }; | |
| qcom,suspend@1 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x00>; | |
| }; | |
| }; | |
| pin@fd510f0 { | |
| qcom,pin-num = <0x0f>; | |
| reg = <0xfd5110f0 0x10>; | |
| qcom,active@0 { | |
| qcom,func = <0x03>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x00>; | |
| }; | |
| qcom,suspend@1 { | |
| qcom,func = <0x03>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x00>; | |
| }; | |
| }; | |
| pin@fd51070 { | |
| qcom,pin-num = <0x07>; | |
| reg = <0xfd511070 0x10>; | |
| qcom,active@0 { | |
| qcom,func = <0x03>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x00>; | |
| }; | |
| qcom,suspend@1 { | |
| qcom,func = <0x03>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x00>; | |
| }; | |
| }; | |
| pin@fd51160 { | |
| qcom,pin-num = <0x16>; | |
| reg = <0xfd511160 0x10>; | |
| qcom,active@0 { | |
| qcom,func = <0x04>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x02>; | |
| qcom,pull = <0x01>; | |
| }; | |
| qcom,suspend@1 { | |
| qcom,func = <0x04>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x02>; | |
| qcom,pull = <0x01>; | |
| }; | |
| }; | |
| pin@fd51450 { | |
| qcom,pin-num = <0x45>; | |
| reg = <0xfd511450 0x10>; | |
| qcom,active@0 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x03>; | |
| }; | |
| qcom,suspend@1 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x03>; | |
| }; | |
| }; | |
| pin@fd51280 { | |
| qcom,pin-num = <0x28>; | |
| reg = <0xfd511280 0x10>; | |
| qcom,active@0 { | |
| qcom,func = <0x01>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x03>; | |
| }; | |
| qcom,suspend@1 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x03>; | |
| }; | |
| }; | |
| pin@fd511d0 { | |
| qcom,pin-num = <0x1d>; | |
| reg = <0xfd5111d0 0x10>; | |
| qcom,active@0 { | |
| qcom,func = <0x01>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x00>; | |
| }; | |
| qcom,suspend@1 { | |
| qcom,func = <0x00>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x00>; | |
| }; | |
| }; | |
| pin@fd51120 { | |
| qcom,pin-num = <0x12>; | |
| reg = <0xfd511120 0x10>; | |
| qcom,active@0 { | |
| qcom,func = <0x03>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x00>; | |
| }; | |
| qcom,suspend@1 { | |
| qcom,func = <0x03>; | |
| qcom,dir = <0x00>; | |
| qcom,drv = <0x00>; | |
| qcom,pull = <0x00>; | |
| }; | |
| }; | |
| }; | |
| slim@fe12f000 { | |
| reg-names = "slimbus_physical\0slimbus_bam_physical"; | |
| interrupts = <0x00 0xa3 0x00 0x00 0xa4 0x00>; | |
| cell-index = <0x01>; | |
| compatible = "qcom,slim-ngd"; | |
| reg = <0xfe12f000 0x35000 0xfe104000 0x20000>; | |
| interrupt-names = "slimbus_irq\0slimbus_bam_irq"; | |
| tapan_codec { | |
| qcom,cdc-vdd-buck-current = <0x9eb10>; | |
| qcom,cdc-vdd-cx-voltage = <0x124f80 0x124f80>; | |
| qcom,cdc-micbias-ldoh-v = <0x03>; | |
| qcom,cdc-micbias-cfilt3-mv = <0x708>; | |
| qcom,cdc-vdd-buckhelper-current = <0x2710>; | |
| qcom,cdc-vdd-buckhelper-voltage = <0x1b1598 0x206cc8>; | |
| qcom,cdc-micbias1-cfilt-sel = <0x00>; | |
| qcom,cdc-vdd-h-voltage = <0x1b7740 0x1b7740>; | |
| elemental-addr = [00 01 e0 00 17 02]; | |
| qcom,cdc-micbias-cfilt1-mv = <0x708>; | |
| qcom,cdc-micbias-cfilt2-mv = <0xa8c>; | |
| interrupts = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c>; | |
| qcom,cdc-vdd-buck-voltage = <0x1b7740 0x20ce70>; | |
| qcom,cdc-vdd-cx-current = <0x7d0>; | |
| cdc-vdd-px-supply = <0x0b>; | |
| qcom,cdc-slim-ifd = "tapan-slim-ifd"; | |
| qcom,cdc-static-supplies = "cdc-vdd-h\0cdc-vdd-px\0cdc-vdd-cx"; | |
| interrupt-parent = <0x40>; | |
| cdc-vdd-buck-supply = <0x41>; | |
| qcom,cdc-micbias1-ext-cap; | |
| cdc-vdd-buckhelper-supply = <0x42>; | |
| cdc-vdd-cx-supply = <0x05>; | |
| qcom,cdc-reset-gpio = <0x08 0x48 0x00>; | |
| qcom,cdc-mclk-clk-rate = <0x927c00>; | |
| qcom,cdc-cp-supplies = "cdc-vdd-buck\0cdc-vdd-buckhelper"; | |
| qcom,cdc-micbias2-cfilt-sel = <0x01>; | |
| qcom,cdc-vdd-px-voltage = <0x1b7740 0x1b7740>; | |
| compatible = "qcom,tapan-slim-pgd"; | |
| qcom,cdc-micbias3-cfilt-sel = <0x02>; | |
| qcom,cdc-vdd-px-current = <0x61a8>; | |
| qcom,cdc-slim-ifd-elemental-addr = [00 00 e0 00 17 02]; | |
| qcom,cdc-vdd-h-current = <0x61a8>; | |
| cdc-vdd-h-supply = <0x0b>; | |
| }; | |
| }; | |
| etm@fc33c000 { | |
| reg-names = "etm-base"; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x0a>; | |
| coresight-child-list = <0x30>; | |
| coresight-outports = <0x00>; | |
| coresight-child-ports = <0x00>; | |
| qcom,round-robin; | |
| compatible = "arm,coresight-etm"; | |
| reg = <0xfc33c000 0x1000>; | |
| coresight-name = "coresight-etm0"; | |
| }; | |
| qcom,gdsc@fc401ec0 { | |
| regulator-name = "gdsc_usb30_sec"; | |
| status = "disabled"; | |
| compatible = "qcom,gdsc"; | |
| reg = <0xfc401ec0 0x04>; | |
| }; | |
| qcom,mpm@fc4281d0 { | |
| reg-names = "vmpm\0ipc"; | |
| interrupts = <0x00 0xab 0x01>; | |
| qcom,gic-parent = <0x01>; | |
| qcom,gpio-map = <0x03 0x01 0x04 0x04 0x05 0x05 0x06 0x09 0x07 0x0d 0x08 0x11 0x09 0x15 0x0a 0x1b 0x0b 0x1d 0x0c 0x1f 0x0d 0x21 0x0e 0x23 0x0f 0x25 0x10 0x26 0x11 0x27 0x12 0x29 0x13 0x2e 0x14 0x30 0x15 0x31 0x16 0x32 0x17 0x33 0x18 0x34 0x19 0x36 0x1a 0x3e 0x1b 0x3f 0x1c 0x40 0x1d 0x41 0x1e 0x42 0x1f 0x43 0x20 0x44 0x21 0x45 0x22 0x47 0x23 0x48 0x24 0x6a 0x25 0x6b 0x26 0x6c 0x27 0x6d 0x28 0x6e 0x29 0x73 0x36 0x6f 0x37 0x70 0x38 0x71>; | |
| qcom,gic-map = <0x2f 0xac 0x35 0x68 0x3e 0xde 0x02 0xd8 0xff 0x12 0xff 0x13 0xff 0x23 0xff 0x28 0xff 0x2f 0xff 0x38 0xff 0x39 0xff 0x3a 0xff 0x3b 0xff 0x3c 0xff 0x3d 0xff 0x41 0xff 0x4a 0xff 0x4b 0xff 0x4e 0xff 0x4f 0xff 0x61 0xff 0x66 0xff 0x6d 0xff 0x80 0xff 0x81 0xff 0x82 0xff 0x83 0xff 0x8d 0xff 0x9b 0xff 0x9d 0xff 0xa1 0xff 0xa2 0xff 0xa6 0xff 0xa9 0xff 0xaa 0xff 0xad 0xff 0xae 0xff 0xaf 0xff 0xb0 0xff 0xb1 0xff 0xb2 0xff 0xb3 0xff 0xb5 0xff 0xbc 0xff 0xbd 0xff 0xbe 0xff 0xbf 0xff 0xc0 0xff 0xc2 0xff 0xc3 0xff 0xc4 0xff 0xc6 0xff 0xc8 0xff 0xc9 0xff 0xca 0xff 0xcb 0xff 0xcc 0xff 0xcd 0xff 0xce 0xff 0xcf 0xff 0xea 0xff 0xeb 0xff 0xf0 0xff 0xfd 0xff 0x102 0xff 0x103 0xff 0x10d 0xff 0x10e 0xff 0x113 0xff 0x114>; | |
| compatible = "qcom,mpm-v2"; | |
| qcom,ipc-bit-offset = <0x01>; | |
| qcom,gpio-parent = <0x08>; | |
| reg = <0xfc4281d0 0x1000 0xf9011008 0x04>; | |
| }; | |
| qcom,csiphy@fda0ac00 { | |
| reg-names = "csiphy\0csiphy_clk_mux"; | |
| interrupts = <0x00 0x4e 0x00>; | |
| cell-index = <0x00>; | |
| compatible = "qcom,csiphy"; | |
| reg = <0xfda0ac00 0x200 0xfda00030 0x04>; | |
| interrupt-names = "csiphy"; | |
| }; | |
| qcom,smp2pgpio-ssr-smp2p-1-in { | |
| gpio-controller; | |
| #interrupt-cells = <0x02>; | |
| qcom,is-inbound; | |
| #gpio-cells = <0x02>; | |
| qcom,entry-name = "slave-kernel"; | |
| compatible = "qcom,smp2pgpio"; | |
| interrupt-controller; | |
| qcom,remote-pid = <0x01>; | |
| phandle = <0x56>; | |
| linux,phandle = <0x56>; | |
| }; | |
| qcom,smp2pgpio_test_smp2p_7_out { | |
| gpios = <0x14 0x00 0x00>; | |
| compatible = "qcom,smp2pgpio_test_smp2p_7_out"; | |
| }; | |
| qcom,smp2pgpio_test_smp2p_2_out { | |
| gpios = <0x18 0x00 0x00>; | |
| compatible = "qcom,smp2pgpio_test_smp2p_2_out"; | |
| }; | |
| cti@fc344000 { | |
| reg-names = "cti-base"; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x20>; | |
| compatible = "arm,coresight-cti"; | |
| reg = <0xfc344000 0x1000>; | |
| coresight-name = "coresight-cti-cpu3"; | |
| }; | |
| etm@fc33e000 { | |
| reg-names = "etm-base"; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x0c>; | |
| coresight-child-list = <0x30>; | |
| coresight-outports = <0x00>; | |
| coresight-child-ports = <0x02>; | |
| qcom,round-robin; | |
| compatible = "arm,coresight-etm"; | |
| reg = <0xfc33e000 0x1000>; | |
| coresight-name = "coresight-etm2"; | |
| }; | |
| qcom,vidc { | |
| qcom,max-hw-load = <0x1a5e0>; | |
| qcom,hfi = "q6"; | |
| compatible = "qcom,msm-vidc"; | |
| }; | |
| qcom,msm-pcm-voice { | |
| compatible = "qcom,msm-pcm-voice"; | |
| }; | |
| qcom,spm@f9099000 { | |
| qcom,core-id = <0x01>; | |
| qcom,saw2-cfg = <0x00>; | |
| qcom,saw2-spm-ctl = <0x08>; | |
| qcom,saw2-spm-cmd-wfi = [60 03 60 0b 0f]; | |
| qcom,saw2-spm-dly = <0x3c102800>; | |
| qcom,saw2-spm-cmd-spc = <0x20108030 0x905b6003 0x603b7676 0xb945b80 0x1026300f>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| compatible = "qcom,spm-v2"; | |
| qcom,saw2-spm-cmd-pc = <0x20108030 0x905b6003 0x603b7676 0xb945b80 0x1026300f>; | |
| reg = <0xf9099000 0x1000>; | |
| qcom,saw2-ver-reg = <0xfd0>; | |
| }; | |
| qcom,spm@f9012000 { | |
| qcom,saw2-spm-cmd-pc-no-rpm = <0x32b010 0xe0d06bc0 0x42f01103 0x1b0504e 0x202c0d0 0x12e06b02 0x3250f00f>; | |
| qcom,saw2-pmic-data0 = <0x2030080>; | |
| qcom,core-id = <0xffff>; | |
| qcom,saw2-cfg = <0x14>; | |
| qcom,saw2-spm-ctl = <0x00>; | |
| qcom,pfm-port = <0x02>; | |
| qcom,L2-spm-is-apcs-master; | |
| qcom,saw2-spm-dly = <0x3c102800>; | |
| qcom,vctl-port = <0x00>; | |
| qcom,saw2-spm-cmd-ret = <0x3000f>; | |
| qcom,saw2-spm-cmd-gdhs = [00 20 32 6b c0 e0 d0 42 07 50 4e 02 02 d0 e0 c0 22 6b 02 32 50 0f]; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| qcom,phase-port = <0x01>; | |
| compatible = "qcom,spm-v2"; | |
| qcom,saw2-spm-cmd-pc = <0x32b010 0xe0d06bc0 0x42f01107 0x1b0504e 0x202c0d0 0x12e06b02 0x3250f00f>; | |
| qcom,vctl-timeout-us = <0x32>; | |
| reg = <0xf9012000 0x1000>; | |
| qcom,saw2-pmic-data1 = <0x30000>; | |
| qcom,saw2-ver-reg = <0xfd0>; | |
| }; | |
| qcom,spm@f9089000 { | |
| qcom,core-id = <0x00>; | |
| qcom,saw2-cfg = <0x00>; | |
| qcom,saw2-spm-ctl = <0x08>; | |
| qcom,saw2-spm-cmd-wfi = [60 03 60 0b 0f]; | |
| qcom,saw2-spm-dly = <0x3c102800>; | |
| qcom,saw2-spm-cmd-spc = <0x20108030 0x905b6003 0x603b7676 0xb945b80 0x1026300f>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| compatible = "qcom,spm-v2"; | |
| qcom,saw2-spm-cmd-pc = <0x20108030 0x905b6003 0x603b7676 0xb945b80 0x1026300f>; | |
| reg = <0xf9089000 0x1000>; | |
| qcom,saw2-ver-reg = <0xfd0>; | |
| }; | |
| qcom,msm-compr-dsp { | |
| compatible = "qcom,msm-compr-dsp"; | |
| }; | |
| modem_etm0 { | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x0f>; | |
| coresight-child-list = <0x31>; | |
| coresight-outports = <0x00>; | |
| coresight-child-ports = <0x01>; | |
| compatible = "qcom,coresight-modem-etm"; | |
| coresight-name = "coresight-modem-etm0"; | |
| }; | |
| qcom,smp2pgpio-smp2p-7-out { | |
| gpio-controller; | |
| #interrupt-cells = <0x02>; | |
| #gpio-cells = <0x02>; | |
| qcom,entry-name = "smp2p"; | |
| compatible = "qcom,smp2pgpio"; | |
| interrupt-controller; | |
| qcom,remote-pid = <0x07>; | |
| phandle = <0x14>; | |
| linux,phandle = <0x14>; | |
| }; | |
| rmtfs_sharedmem { | |
| reg-names = "rmtfs"; | |
| compatible = "qcom,sharedmem-uio"; | |
| reg = <0xfd80000 0x180000>; | |
| }; | |
| cti@fc30d000 { | |
| reg-names = "cti-base"; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x18>; | |
| compatible = "arm,coresight-cti"; | |
| reg = <0xfc30d000 0x1000>; | |
| coresight-name = "coresight-cti5"; | |
| }; | |
| qcom,msm-dai-q6 { | |
| compatible = "qcom,msm-dai-q6"; | |
| qcom,msm-dai-q6-bt-sco-rx { | |
| qcom,msm-dai-q6-dev-id = <0x3000>; | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| }; | |
| qcom,msm-dai-q6-int-fm-tx { | |
| qcom,msm-dai-q6-dev-id = <0x3005>; | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| }; | |
| qcom,msm-dai-q6-incall-music-rx { | |
| qcom,msm-dai-q6-dev-id = <0x8005>; | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| }; | |
| qcom,msm-dai-q6-int-fm-rx { | |
| qcom,msm-dai-q6-dev-id = <0x3004>; | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| }; | |
| qcom,msm-dai-q6-incall-music-2-rx { | |
| qcom,msm-dai-q6-dev-id = <0x8002>; | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| }; | |
| qcom,msm-dai-q6-incall-record-tx { | |
| qcom,msm-dai-q6-dev-id = <0x8004>; | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| }; | |
| qcom,msm-dai-q6-sb-3-tx { | |
| qcom,msm-dai-q6-dev-id = <0x4007>; | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| }; | |
| qcom,msm-dai-q6-sb-3-rx { | |
| qcom,msm-dai-q6-dev-id = <0x4006>; | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| }; | |
| qcom,msm-dai-q6-sb-1-tx { | |
| qcom,msm-dai-q6-dev-id = <0x4003>; | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| }; | |
| qcom,msm-dai-q6-incall-record-rx { | |
| qcom,msm-dai-q6-dev-id = <0x8003>; | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| }; | |
| qcom,msm-dai-q6-sb-0-rx { | |
| qcom,msm-dai-q6-dev-id = <0x4000>; | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| }; | |
| qcom,msm-dai-q6-bt-sco-tx { | |
| qcom,msm-dai-q6-dev-id = <0x3001>; | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| }; | |
| qcom,msm-dai-q6-afe-proxy-tx { | |
| qcom,msm-dai-q6-dev-id = <0xf0>; | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| }; | |
| qcom,msm-dai-q6-sb-4-rx { | |
| qcom,msm-dai-q6-dev-id = <0x4008>; | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| }; | |
| qcom,msm-dai-q6-afe-proxy-rx { | |
| qcom,msm-dai-q6-dev-id = <0xf1>; | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| }; | |
| qcom,msm-dai-q6-sb-5-tx { | |
| qcom,msm-dai-q6-dev-id = <0x400b>; | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| }; | |
| qcom,msm-dai-q6-sb-1-rx { | |
| qcom,msm-dai-q6-dev-id = <0x4002>; | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| }; | |
| qcom,msm-dai-q6-be-afe-pcm-rx { | |
| qcom,msm-dai-q6-dev-id = <0xe0>; | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| }; | |
| qcom,msm-dai-q6-sb-0-tx { | |
| qcom,msm-dai-q6-dev-id = <0x4001>; | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| }; | |
| qcom,msm-dai-q6-be-afe-pcm-tx { | |
| qcom,msm-dai-q6-dev-id = <0xe1>; | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| }; | |
| qcom,msm-dai-q6-sb-4-tx { | |
| qcom,msm-dai-q6-dev-id = <0x4009>; | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| }; | |
| }; | |
| qcom,qcedev@fd400000 { | |
| qcom,msm-bus,vectors-KBps = <0x37 0x200 0x00 0x00 0x37 0x200 0x3c0f00 0x60180>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| reg-names = "crypto-base\0crypto-bam-base"; | |
| interrupts = <0x00 0xcf 0x00>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,bam-pipe-pair = <0x01>; | |
| qcom,ce-hw-shared; | |
| compatible = "qcom,qcedev"; | |
| qcom,ce-hw-instance = <0x00>; | |
| qcom,msm-bus,active-only = <0x00>; | |
| reg = <0xfd400000 0x20000 0xfd404000 0x8000>; | |
| qcom,msm-bus,name = "qcedev-noc"; | |
| }; | |
| replicator@fc31c000 { | |
| reg-names = "replicator-base"; | |
| coresight-nr-inports = <0x01>; | |
| coresight-id = <0x02>; | |
| coresight-child-list = <0x2a 0x2b>; | |
| coresight-outports = <0x00 0x01>; | |
| coresight-child-ports = <0x00 0x00>; | |
| compatible = "qcom,coresight-replicator"; | |
| phandle = <0x2c>; | |
| reg = <0xfc31c000 0x1000>; | |
| linux,phandle = <0x2c>; | |
| coresight-name = "coresight-replicator"; | |
| }; | |
| qcom,pronto@fb21b000 { | |
| qcom,gpio-err-ready = <0x52 0x01 0x00>; | |
| reg-names = "pmu_base\0clk_base\0halt_base"; | |
| interrupts = <0x00 0x95 0x01>; | |
| vdd_pronto_pll-supply = <0x20>; | |
| qcom,gpio-err-fatal = <0x52 0x00 0x00>; | |
| qcom,gpio-force-stop = <0x53 0x00 0x00>; | |
| qcom,gpio-proxy-unvote = <0x52 0x02 0x00>; | |
| compatible = "qcom,pil-pronto"; | |
| reg = <0xfb21b000 0x3000 0xfc401700 0x04 0xfd485300 0x0c>; | |
| qcom,firmware-name = "wcnss"; | |
| }; | |
| tmc@fc307000 { | |
| coresight-ctis = <0x26 0x27>; | |
| reg-names = "tmc-base"; | |
| coresight-nr-inports = <0x01>; | |
| coresight-id = <0x03>; | |
| coresight-default-sink; | |
| coresight-child-list = <0x2c>; | |
| coresight-outports = <0x00>; | |
| coresight-child-ports = <0x00>; | |
| compatible = "arm,coresight-tmc"; | |
| phandle = <0x2d>; | |
| reg = <0xfc307000 0x1000>; | |
| linux,phandle = <0x2d>; | |
| coresight-name = "coresight-tmc-etf"; | |
| }; | |
| qcom,cpubw { | |
| qcom,cpu-mem-ports = <0x01 0x200>; | |
| compatible = "qcom,cpubw"; | |
| qcom,bw-tbl = <0x5f5 0x989 0xbeb 0xfe2>; | |
| }; | |
| tpiu@fc318000 { | |
| qcom,vdd-current-level = "\0\0#(\0\f5"; | |
| vdd-supply = <0x28>; | |
| qcom,vdd-io-current-level = <0x06 0x55f0>; | |
| reg-names = "tpiu-base"; | |
| coresight-nr-inports = <0x01>; | |
| coresight-id = <0x01>; | |
| vdd-io-supply = <0x29>; | |
| qcom,vdd-voltage-level = <0x2d0370 0x2d0370>; | |
| compatible = "arm,coresight-tpiu"; | |
| phandle = <0x2b>; | |
| qcom,vdd-io-voltage-level = <0x2d0370 0x2d0370>; | |
| reg = <0xfc318000 0x1000>; | |
| linux,phandle = <0x2b>; | |
| coresight-name = "coresight-tpiu"; | |
| }; | |
| qcom,msm-thermal { | |
| qcom,freq-control-mask = <0x0f>; | |
| qcom,core-control-mask = <0x0e>; | |
| qcom,hotplug-temp = <0x6e>; | |
| qcom,vdd-restriction-temp-hysteresis = <0x0a>; | |
| qcom,core-temp-hysteresis = <0x0a>; | |
| qcom,freq-step = <0x02>; | |
| qcom,temp-hysteresis = <0x0a>; | |
| qcom,vdd-restriction-temp = <0x05>; | |
| qcom,sensor-id = <0x00>; | |
| qcom,hotplug-temp-hysteresis = <0x14>; | |
| qcom,limit-temp = <0x3c>; | |
| compatible = "qcom,msm-thermal"; | |
| qcom,poll-ms = <0xfa>; | |
| vdd-dig-supply = <0x58>; | |
| qcom,core-limit-temp = <0x50>; | |
| qcom,cpu-sensors = "tsens_tz_sensor5\0tsens_tz_sensor5\0tsens_tz_sensor2\0tsens_tz_sensor2"; | |
| qcom,vdd-dig-rstr { | |
| qcom,vdd-rstr-reg = "vdd-dig"; | |
| qcom,min-level = <0x01>; | |
| qcom,levels = <0x05 0x07 0x07>; | |
| }; | |
| qcom,vdd-apps-rstr { | |
| qcom,vdd-rstr-reg = "vdd-apps"; | |
| qcom,freq-req; | |
| qcom,levels = <0x927c0 0xc0300 0xf3c00>; | |
| }; | |
| }; | |
| qcom,gdsc@fd8c1804 { | |
| regulator-name = "gdsc_vcap"; | |
| status = "disabled"; | |
| compatible = "qcom,gdsc"; | |
| reg = <0xfd8c1804 0x04>; | |
| }; | |
| i2c@f9926000 { | |
| qcom,i2c-bus-freq = <0x186a0>; | |
| reg-names = "qup_phys_addr"; | |
| interrupts = <0x00 0x62 0x00>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| cell-index = <0x00>; | |
| compatible = "qcom,i2c-qup"; | |
| reg = <0xf9926000 0x1000>; | |
| interrupt-names = "qup_err_intr"; | |
| }; | |
| qcom,gdsc@fd8c4024 { | |
| regulator-name = "gdsc_oxili_gx"; | |
| status = "disabled"; | |
| compatible = "qcom,gdsc"; | |
| phandle = <0x12>; | |
| reg = <0xfd8c4024 0x04>; | |
| linux,phandle = <0x12>; | |
| }; | |
| qcom,msm-pcm-hostless { | |
| compatible = "qcom,msm-pcm-hostless"; | |
| }; | |
| qcom,gdsc@fd8c2304 { | |
| regulator-name = "gdsc_mdss"; | |
| status = "ok"; | |
| compatible = "qcom,gdsc"; | |
| phandle = <0x0f>; | |
| qcom,clock-names = "core_clk\0lut_clk"; | |
| reg = <0xfd8c2304 0x04>; | |
| linux,phandle = <0x0f>; | |
| }; | |
| qcom,spmi@fc4c0000 { | |
| qcom,pmic-arb-channel = <0x00>; | |
| #interrupt-cells = <0x03>; | |
| reg-names = "core\0intr\0cnfg"; | |
| interrupts = <0x00 0xbe 0x00 0x00 0xbb 0x00>; | |
| qcom,pmic-arb-ee = <0x00>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| cell-index = <0x00>; | |
| compatible = "qcom,spmi-pmic-arb"; | |
| interrupt-controller; | |
| reg = <0xfc4cf000 0x1000 0xfc4cb000 0x1000 0xfc4ca000 0x1000>; | |
| qcom,pm8226@0 { | |
| spmi-slave-container; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| reg = <0x00>; | |
| qcom,leds@a300 { | |
| label = "mpp"; | |
| compatible = "qcom,leds-qpnp"; | |
| reg = <0xa300 0x100>; | |
| }; | |
| gpios { | |
| gpio-controller; | |
| spmi-dev-container; | |
| #gpio-cells = <0x02>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| label = "pm8226-gpio"; | |
| compatible = "qcom,qpnp-pin"; | |
| phandle = <0x43>; | |
| linux,phandle = <0x43>; | |
| gpio@c700 { | |
| qcom,invert = <0x00>; | |
| qcom,master-en = <0x01>; | |
| qcom,pin-num = <0x08>; | |
| qcom,mode = <0x00>; | |
| qcom,out-strength = <0x01>; | |
| qcom,pull = <0x04>; | |
| qcom,src-sel = <0x00>; | |
| qcom,vin-sel = <0x00>; | |
| reg = <0xc700 0x100>; | |
| qcom,output-type = <0x00>; | |
| }; | |
| gpio@c100 { | |
| qcom,master-en = <0x01>; | |
| qcom,pin-num = <0x02>; | |
| qcom,mode = <0x01>; | |
| qcom,out-strength = <0x03>; | |
| qcom,pull = <0x05>; | |
| qcom,src-sel = <0x02>; | |
| qcom,vin-sel = <0x02>; | |
| reg = <0xc100 0x100>; | |
| qcom,output-type = <0x00>; | |
| }; | |
| gpio@c500 { | |
| qcom,invert = <0x00>; | |
| qcom,master-en = <0x01>; | |
| qcom,pin-num = <0x06>; | |
| qcom,mode = <0x00>; | |
| qcom,out-strength = <0x01>; | |
| qcom,pull = <0x05>; | |
| qcom,src-sel = <0x02>; | |
| qcom,vin-sel = <0x03>; | |
| reg = <0xc500 0x100>; | |
| qcom,output-type = <0x00>; | |
| }; | |
| gpio@c000 { | |
| qcom,master-en = <0x01>; | |
| qcom,pin-num = <0x01>; | |
| qcom,mode = <0x01>; | |
| qcom,out-strength = <0x03>; | |
| qcom,pull = <0x05>; | |
| qcom,src-sel = <0x02>; | |
| qcom,vin-sel = <0x02>; | |
| reg = <0xc000 0x100>; | |
| qcom,output-type = <0x00>; | |
| }; | |
| gpio@c200 { | |
| qcom,invert = <0x00>; | |
| qcom,master-en = <0x01>; | |
| qcom,pin-num = <0x03>; | |
| qcom,mode = <0x00>; | |
| qcom,out-strength = <0x01>; | |
| qcom,pull = <0x04>; | |
| qcom,src-sel = <0x00>; | |
| qcom,vin-sel = <0x00>; | |
| reg = <0xc200 0x100>; | |
| qcom,output-type = <0x00>; | |
| }; | |
| gpio@c300 { | |
| qcom,invert = <0x00>; | |
| qcom,master-en = <0x01>; | |
| qcom,pin-num = <0x04>; | |
| qcom,mode = <0x02>; | |
| qcom,out-strength = <0x01>; | |
| qcom,pull = <0x04>; | |
| qcom,src-sel = <0x02>; | |
| qcom,vin-sel = <0x03>; | |
| reg = <0xc300 0x100>; | |
| qcom,output-type = <0x00>; | |
| }; | |
| gpio@c400 { | |
| qcom,invert = <0x00>; | |
| qcom,master-en = <0x01>; | |
| qcom,pin-num = <0x05>; | |
| qcom,mode = <0x00>; | |
| qcom,out-strength = <0x01>; | |
| qcom,pull = <0x04>; | |
| qcom,src-sel = <0x00>; | |
| qcom,vin-sel = <0x00>; | |
| reg = <0xc400 0x100>; | |
| qcom,output-type = <0x00>; | |
| }; | |
| gpio@c600 { | |
| qcom,master-en = <0x01>; | |
| qcom,pin-num = <0x07>; | |
| qcom,mode = <0x00>; | |
| qcom,pull = <0x05>; | |
| qcom,src-sel = <0x02>; | |
| qcom,vin-sel = <0x03>; | |
| reg = <0xc600 0x100>; | |
| }; | |
| }; | |
| mpps { | |
| gpio-controller; | |
| spmi-dev-container; | |
| #gpio-cells = <0x02>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| label = "pm8226-mpp"; | |
| compatible = "qcom,qpnp-pin"; | |
| mpp@a100 { | |
| qcom,invert = <0x00>; | |
| qcom,master-en = <0x01>; | |
| qcom,cs-out = <0x00>; | |
| qcom,pin-num = <0x02>; | |
| qcom,mode = <0x06>; | |
| qcom,aout-ref = <0x00>; | |
| qcom,pull = <0x00>; | |
| qcom,src-sel = <0x0c>; | |
| qcom,vin-sel = <0x00>; | |
| reg = <0xa100 0x100>; | |
| qcom,ain-route = <0x00>; | |
| }; | |
| mpp@a000 { | |
| qcom,invert = <0x00>; | |
| qcom,master-en = <0x01>; | |
| qcom,cs-out = <0x00>; | |
| qcom,pin-num = <0x01>; | |
| qcom,mode = <0x05>; | |
| qcom,aout-ref = <0x00>; | |
| qcom,pull = <0x00>; | |
| qcom,src-sel = <0x01>; | |
| qcom,vin-sel = <0x02>; | |
| reg = <0xa000 0x100>; | |
| qcom,ain-route = <0x00>; | |
| }; | |
| mpp@a600 { | |
| qcom,invert = <0x00>; | |
| qcom,master-en = <0x00>; | |
| qcom,cs-out = <0x00>; | |
| qcom,pin-num = <0x07>; | |
| qcom,mode = <0x00>; | |
| qcom,aout-ref = <0x00>; | |
| qcom,pull = <0x00>; | |
| qcom,src-sel = <0x00>; | |
| qcom,vin-sel = <0x00>; | |
| reg = <0xa600 0x100>; | |
| qcom,ain-route = <0x00>; | |
| }; | |
| mpp@a200 { | |
| qcom,invert = <0x00>; | |
| qcom,master-en = <0x01>; | |
| qcom,cs-out = <0x00>; | |
| qcom,pin-num = <0x03>; | |
| qcom,mode = <0x05>; | |
| qcom,aout-ref = <0x00>; | |
| qcom,pull = <0x00>; | |
| qcom,src-sel = <0x01>; | |
| qcom,vin-sel = <0x02>; | |
| reg = <0xa200 0x100>; | |
| qcom,ain-route = <0x00>; | |
| }; | |
| mpp@a700 { | |
| qcom,invert = <0x00>; | |
| qcom,master-en = <0x00>; | |
| qcom,cs-out = <0x00>; | |
| qcom,pin-num = <0x08>; | |
| qcom,mode = <0x00>; | |
| qcom,aout-ref = <0x00>; | |
| qcom,pull = <0x00>; | |
| qcom,src-sel = <0x00>; | |
| qcom,vin-sel = <0x00>; | |
| reg = <0xa700 0x100>; | |
| qcom,ain-route = <0x00>; | |
| }; | |
| mpp@a500 { | |
| qcom,invert = <0x00>; | |
| qcom,master-en = <0x01>; | |
| qcom,cs-out = <0x00>; | |
| qcom,pin-num = <0x06>; | |
| qcom,mode = <0x06>; | |
| qcom,aout-ref = <0x00>; | |
| qcom,pull = <0x00>; | |
| qcom,src-sel = <0x0a>; | |
| qcom,vin-sel = <0x00>; | |
| reg = <0xa500 0x100>; | |
| qcom,ain-route = <0x00>; | |
| }; | |
| mpp@a400 { | |
| qcom,invert = <0x00>; | |
| qcom,master-en = <0x01>; | |
| qcom,cs-out = <0x00>; | |
| qcom,pin-num = <0x05>; | |
| qcom,mode = <0x04>; | |
| qcom,aout-ref = <0x00>; | |
| qcom,pull = <0x00>; | |
| qcom,src-sel = <0x01>; | |
| qcom,vin-sel = <0x00>; | |
| reg = <0xa400 0x100>; | |
| qcom,ain-route = <0x00>; | |
| }; | |
| mpp@a300 { | |
| qcom,invert = <0x00>; | |
| qcom,master-en = <0x01>; | |
| qcom,cs-out = <0x00>; | |
| qcom,pin-num = <0x04>; | |
| qcom,mode = <0x06>; | |
| qcom,aout-ref = <0x00>; | |
| qcom,pull = <0x00>; | |
| qcom,src-sel = <0x08>; | |
| qcom,vin-sel = <0x00>; | |
| reg = <0xa300 0x100>; | |
| qcom,ain-route = <0x00>; | |
| }; | |
| }; | |
| qcom,bms { | |
| qcom,bms-vadc = <0x3c>; | |
| qcom,low-soc-calculate-soc-ms = <0x1388>; | |
| qcom,ocv-voltage-high-threshold-uv = <0x393870>; | |
| qcom,low-soc-calculate-soc-threshold = <0x0f>; | |
| qcom,low-voltage-threshold = <0x312220>; | |
| qcom,batt-type = <0x00>; | |
| qcom,adjust-soc-low-threshold = <0x0f>; | |
| qcom,r-conn-mohm = <0x00>; | |
| qcom,calculate-soc-ms = <0x4e20>; | |
| qcom,bms-adc_tm = <0x48>; | |
| qcom,v-cutoff-uv = <0x30d400>; | |
| qcom,tm-temp-margin = <0x1388>; | |
| qcom,high-ocv-correction-limit-uv = <0x32>; | |
| spmi-dev-container; | |
| qcom,r-sense-uohm = <0x2710>; | |
| qcom,chg-term-ua = <0x186a0>; | |
| qcom,low-voltage-calculate-soc-ms = <0x3e8>; | |
| qcom,max-voltage-uv = <0x401640>; | |
| qcom,battery-data = <0x4f>; | |
| qcom,min-fcc-ocv-pc = <0x14>; | |
| status = "ok"; | |
| #address-cells = <0x01>; | |
| qcom,min-fcc-learning-samples = <0x04>; | |
| qcom,enable-fcc-learning = <0x01>; | |
| qcom,fcc-resolution = <0x0a>; | |
| qcom,bms-iadc = <0x4e>; | |
| #size-cells = <0x01>; | |
| qcom,use-ocv-thresholds = <0x00>; | |
| qcom,ocv-voltage-low-threshold-uv = <0x37b1d0>; | |
| qcom,min-fcc-learning-soc = <0x14>; | |
| compatible = "qcom,qpnp-bms"; | |
| qcom,use-external-rsense = <0x01>; | |
| qcom,low-ocv-correction-limit-uv = <0x64>; | |
| qcom,shutdown-soc-valid-limit = <0x64>; | |
| qcom,hold-soc-est = <0x03>; | |
| qcom,bms-bms@4000 { | |
| interrupts = <0x00 0x40 0x00 0x00 0x40 0x01 0x00 0x40 0x02 0x00 0x40 0x03 0x00 0x40 0x04 0x00 0x40 0x05 0x00 0x40 0x06 0x00 0x40 0x07>; | |
| reg = <0x4000 0x100>; | |
| interrupt-names = "cc_thr\0ocv_for_r\0good_ocv\0charge_begin\0ocv_thr\0sw_cc_thr\0vsense_avg\0vsense_for_r"; | |
| }; | |
| qcom,bms-iadc@3800 { | |
| reg = <0x3800 0x100>; | |
| }; | |
| }; | |
| qcom,temp-alarm@2400 { | |
| qcom,channel-num = <0x08>; | |
| qcom,threshold-set = <0x00>; | |
| interrupts = <0x00 0x24 0x00>; | |
| label = "pm8226_tz"; | |
| compatible = "qcom,qpnp-temp-alarm"; | |
| qcom,temp_alarm-vadc = <0x3c>; | |
| reg = <0x2400 0x100>; | |
| }; | |
| qcom,chargerfac { | |
| qcom,chg-adc_tm = <0x48>; | |
| qcom,warm-bat-decidegc = <0x1c2>; | |
| qcom,ibatsafe-ma = <0xcb2>; | |
| qcom,batt-cold-percentage = <0x50>; | |
| qcom,thermal-mitigation = <0x5dc 0x2bc 0x258 0x145>; | |
| qcom,vinmin-mv = <0x10cc>; | |
| qcom,vbatdet-delta-mv = <0x96>; | |
| qcom,tchg-mins = <0x96>; | |
| spmi-dev-container; | |
| qcom,ibatmax-cool-ma = <0x7d0>; | |
| qcom,vddmax-mv = <0x1068>; | |
| status = "ok"; | |
| #address-cells = <0x01>; | |
| qcom,ibatterm-ma = <0x64>; | |
| #size-cells = <0x01>; | |
| qcom,batt-hot-percentage = <0x19>; | |
| compatible = "qcom,qpnp-charger-factory"; | |
| qcom,warm-bat-mv = <0xfa0>; | |
| qcom,vddsafe-mv = <0x1130>; | |
| qcom,cool-bat-decidegc = <0x0a>; | |
| qcom,ibatmax-ma = <0x7d0>; | |
| qcom,cool-bat-mv = <0xfa0>; | |
| qcom,resume-soc = <0x63>; | |
| qcom,chg-vadc = <0x3c>; | |
| qcom,ibatmax-warm-ma = <0x7d0>; | |
| qcom,bat-if@1200 { | |
| interrupts = <0x00 0x12 0x00 0x00 0x12 0x01 0x00 0x12 0x02 0x00 0x12 0x03 0x00 0x12 0x04>; | |
| status = "ok"; | |
| reg = <0x1200 0x100>; | |
| interrupt-names = "batt-pres\0bat-temp-ok\0bat-fet-on\0vcp-on\0psi"; | |
| }; | |
| qcom,buck@1100 { | |
| interrupts = <0x00 0x11 0x00 0x00 0x11 0x01 0x00 0x11 0x02 0x00 0x11 0x03 0x00 0x11 0x04 0x00 0x11 0x05 0x00 0x11 0x06>; | |
| status = "ok"; | |
| reg = <0x1100 0x100>; | |
| interrupt-names = "vbat-ov\0vreg-ov\0overtemp\0vchg-loop\0ichg-loop\0ibat-loop\0vdd-loop"; | |
| }; | |
| qcom,chg-misc@1600 { | |
| status = "ok"; | |
| reg = <0x1600 0x100>; | |
| }; | |
| qcom,usb-chgpth@1300 { | |
| interrupts = <0x00 0x13 0x00 0x00 0x13 0x01 0x00 0x13 0x02 0x00 0x13 0x03>; | |
| status = "ok"; | |
| reg = <0x1300 0x100>; | |
| interrupt-names = "coarse-det-usb\0usbin-valid\0chg-gone\0usb-ocp"; | |
| }; | |
| qcom,chgr@1000 { | |
| interrupts = <0x00 0x10 0x00 0x00 0x10 0x01 0x00 0x10 0x02 0x00 0x10 0x03 0x00 0x10 0x04 0x00 0x10 0x05 0x00 0x10 0x06 0x00 0x10 0x07>; | |
| status = "ok"; | |
| reg = <0x1000 0x100>; | |
| interrupt-names = "vbat-det-lo\0vbat-det-hi\0chgwdog\0state-change\0trkl-chg-on\0fast-chg-on\0chg-failed\0chg-done"; | |
| }; | |
| qcom,boost@1500 { | |
| interrupts = <0x00 0x15 0x00 0x00 0x15 0x01>; | |
| status = "ok"; | |
| reg = <0x1500 0x100>; | |
| interrupt-names = "boost-pwr-ok\0limit-error"; | |
| }; | |
| }; | |
| qcom,leds@a100 { | |
| label = "mpp"; | |
| compatible = "qcom,leds-qpnp"; | |
| reg = <0xa100 0x100>; | |
| }; | |
| qcom,power-on@800 { | |
| qcom,s3-debounce = <0x20>; | |
| interrupts = <0x00 0x08 0x00 0x00 0x08 0x01 0x00 0x08 0x03 0x00 0x08 0x05>; | |
| compatible = "qcom,qpnp-power-on"; | |
| reg = <0x800 0x100>; | |
| interrupt-names = "kpdpwr\0resin\0kpdpwr-bark\0kpdpwr-resin-bark"; | |
| qcom,system-reset; | |
| qcom,pon-dbc-delay = <0x3d09>; | |
| qcom,pon_1 { | |
| qcom,s2-type = <0x07>; | |
| qcom,s2-timer = <0x7d0>; | |
| qcom,s1-timer = <0x1a40>; | |
| qcom,pull-up = <0x01>; | |
| qcom,support-reset = <0x00>; | |
| linux,code = <0x74>; | |
| qcom,pon-type = <0x00>; | |
| }; | |
| qcom,pon_3 { | |
| qcom,s2-type = <0x07>; | |
| qcom,use-bark; | |
| qcom,s2-timer = <0x7d0>; | |
| qcom,s1-timer = <0x1a40>; | |
| qcom,pull-up = <0x01>; | |
| qcom,support-reset = <0x00>; | |
| qcom,pon-type = <0x03>; | |
| }; | |
| qcom,pon_2 { | |
| qcom,s2-type = <0x07>; | |
| qcom,s2-timer = <0x7d0>; | |
| qcom,s1-timer = <0x1a40>; | |
| qcom,pull-up = <0x01>; | |
| qcom,support-reset = <0x00>; | |
| linux,code = <0x72>; | |
| qcom,pon-type = <0x01>; | |
| }; | |
| }; | |
| qcom,charger { | |
| qcom,chg-adc_tm = <0x48>; | |
| qcom,warm-bat-decidegc = <0x1c2>; | |
| qcom,ibatsafe-ma = <0xcb2>; | |
| qcom,batt-cold-percentage = <0x50>; | |
| qcom,thermal-mitigation = <0x5dc 0x2bc 0x258 0x145>; | |
| qcom,pmic-revid = <0x4c>; | |
| qcom,vinmin-mv = <0x10cc>; | |
| qcom,step-charge-current = <0x46a>; | |
| qcom,vbatdet-delta-mv = <0x96>; | |
| qcom,tchg-mins = <0x200>; | |
| spmi-dev-container; | |
| qcom,ibatmax-cool-ma = <0x7d0>; | |
| qcom,vddmax-mv = <0x1068>; | |
| status = "ok"; | |
| #address-cells = <0x01>; | |
| qcom,ibatterm-ma = <0x64>; | |
| #size-cells = <0x01>; | |
| qcom,batt-hot-percentage = <0x19>; | |
| compatible = "qcom,qpnp-charger"; | |
| qcom,warm-bat-mv = <0xfa0>; | |
| qcom,vddsafe-mv = <0x1130>; | |
| qcom,cool-bat-decidegc = <0x00>; | |
| qcom,ibatmax-ma = <0x7d0>; | |
| qcom,cool-bat-mv = <0xfa0>; | |
| qcom,step-charge-voltage = <0x1068>; | |
| qcom,resume-soc = <0x63>; | |
| otg-parent-supply = <0x4d>; | |
| qcom,chg-vadc = <0x3c>; | |
| qcom,ibatmax-warm-ma = <0x7d0>; | |
| qcom,bat-if@1200 { | |
| interrupts = <0x00 0x12 0x00 0x00 0x12 0x01 0x00 0x12 0x02 0x00 0x12 0x03 0x00 0x12 0x04>; | |
| regulator-name = "batfet"; | |
| status = "ok"; | |
| reg = <0x1200 0x100>; | |
| interrupt-names = "batt-pres\0bat-temp-ok\0bat-fet-on\0vcp-on\0psi"; | |
| }; | |
| qcom,buck@1100 { | |
| interrupts = <0x00 0x11 0x00 0x00 0x11 0x01 0x00 0x11 0x02 0x00 0x11 0x03 0x00 0x11 0x04 0x00 0x11 0x05 0x00 0x11 0x06>; | |
| status = "ok"; | |
| reg = <0x1100 0x100>; | |
| interrupt-names = "vbat-ov\0vreg-ov\0overtemp\0vchg-loop\0ichg-loop\0ibat-loop\0vdd-loop"; | |
| }; | |
| qcom,chg-misc@1600 { | |
| status = "ok"; | |
| reg = <0x1600 0x100>; | |
| }; | |
| qcom,usb-chgpth@1300 { | |
| interrupts = <0x00 0x13 0x00 0x00 0x13 0x01 0x00 0x13 0x02 0x00 0x13 0x03>; | |
| regulator-name = "8226_smbbp_otg"; | |
| status = "ok"; | |
| phandle = <0x3d>; | |
| reg = <0x1300 0x100>; | |
| interrupt-names = "coarse-det-usb\0usbin-valid\0chg-gone\0usb-ocp"; | |
| linux,phandle = <0x3d>; | |
| }; | |
| qcom,chgr@1000 { | |
| interrupts = <0x00 0x10 0x00 0x00 0x10 0x01 0x00 0x10 0x02 0x00 0x10 0x03 0x00 0x10 0x04 0x00 0x10 0x05 0x00 0x10 0x06 0x00 0x10 0x07>; | |
| status = "ok"; | |
| reg = <0x1000 0x100>; | |
| interrupt-names = "vbat-det-lo\0vbat-det-hi\0chgwdog\0state-change\0trkl-chg-on\0fast-chg-on\0chg-failed\0chg-done"; | |
| }; | |
| qcom,boost@1500 { | |
| regulator-max-microvolt = <0x4c4b40>; | |
| interrupts = <0x00 0x15 0x00 0x00 0x15 0x01>; | |
| regulator-name = "8226_smbbp_boost"; | |
| status = "ok"; | |
| regulator-min-microvolt = <0x4c4b40>; | |
| phandle = <0x4d>; | |
| reg = <0x1500 0x100>; | |
| interrupt-names = "boost-pwr-ok\0limit-error"; | |
| linux,phandle = <0x4d>; | |
| }; | |
| }; | |
| vadc@3100 { | |
| qcom,adc-batt-therm-type = <0x01>; | |
| interrupts = <0x00 0x31 0x00>; | |
| qcom,adc-bit-resolution = <0x0f>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,qpnp-vadc"; | |
| qcom,vadc-poll-eoc; | |
| qcom,adc-vdd-reference = <0x708>; | |
| phandle = <0x3c>; | |
| reg = <0x3100 0x100>; | |
| interrupt-names = "eoc-int-en-set"; | |
| linux,phandle = <0x3c>; | |
| chan@5 { | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,calibration-type = "absolute"; | |
| qcom,decimation = <0x00>; | |
| qcom,scale-function = <0x00>; | |
| qcom,hw-settle-time = <0x00>; | |
| qcom,pre-div-channel-scaling = <0x01>; | |
| label = "vcoin"; | |
| reg = <0x05>; | |
| }; | |
| chan@a { | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,calibration-type = "absolute"; | |
| qcom,decimation = <0x00>; | |
| qcom,scale-function = <0x00>; | |
| qcom,hw-settle-time = <0x00>; | |
| qcom,pre-div-channel-scaling = <0x00>; | |
| label = "ref_1250v"; | |
| reg = <0x0a>; | |
| }; | |
| chan@9 { | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,calibration-type = "absolute"; | |
| qcom,decimation = <0x00>; | |
| qcom,scale-function = <0x00>; | |
| qcom,hw-settle-time = <0x00>; | |
| qcom,pre-div-channel-scaling = <0x00>; | |
| label = "ref_625mv"; | |
| reg = <0x09>; | |
| }; | |
| chan@c { | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,calibration-type = "absolute"; | |
| qcom,decimation = <0x00>; | |
| qcom,scale-function = <0x00>; | |
| qcom,hw-settle-time = <0x00>; | |
| qcom,pre-div-channel-scaling = <0x00>; | |
| label = "ref_buf_625mv"; | |
| reg = <0x0c>; | |
| }; | |
| chan@2 { | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,calibration-type = "absolute"; | |
| qcom,decimation = <0x00>; | |
| qcom,scale-function = <0x00>; | |
| qcom,hw-settle-time = <0x00>; | |
| qcom,pre-div-channel-scaling = <0x03>; | |
| label = "vchg_sns"; | |
| reg = <0x02>; | |
| }; | |
| chan@0 { | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,calibration-type = "absolute"; | |
| qcom,decimation = <0x00>; | |
| qcom,scale-function = <0x00>; | |
| qcom,hw-settle-time = <0x00>; | |
| qcom,pre-div-channel-scaling = <0x04>; | |
| label = "usb_in"; | |
| reg = <0x00>; | |
| }; | |
| chan@39 { | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,calibration-type = "ratiometric"; | |
| qcom,decimation = <0x00>; | |
| qcom,scale-function = <0x00>; | |
| qcom,hw-settle-time = <0x02>; | |
| qcom,pre-div-channel-scaling = <0x00>; | |
| label = "usb_id_nopull"; | |
| reg = <0x39>; | |
| }; | |
| chan@30 { | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,calibration-type = "ratiometric"; | |
| qcom,decimation = <0x00>; | |
| qcom,scale-function = <0x01>; | |
| qcom,hw-settle-time = <0x02>; | |
| qcom,pre-div-channel-scaling = <0x00>; | |
| label = "batt_therm"; | |
| reg = <0x30>; | |
| }; | |
| chan@7 { | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,calibration-type = "absolute"; | |
| qcom,decimation = <0x00>; | |
| qcom,scale-function = <0x00>; | |
| qcom,hw-settle-time = <0x00>; | |
| qcom,pre-div-channel-scaling = <0x01>; | |
| label = "vph_pwr"; | |
| reg = <0x07>; | |
| }; | |
| chan@17 { | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,calibration-type = "ratiometric"; | |
| qcom,decimation = <0x00>; | |
| qcom,scale-function = <0x02>; | |
| qcom,hw-settle-time = <0x02>; | |
| qcom,pre-div-channel-scaling = <0x00>; | |
| label = "pa_therm1"; | |
| reg = <0x17>; | |
| }; | |
| chan@b2 { | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,calibration-type = "ratiometric"; | |
| qcom,decimation = <0x00>; | |
| qcom,scale-function = <0x04>; | |
| qcom,hw-settle-time = <0x02>; | |
| qcom,pre-div-channel-scaling = <0x00>; | |
| label = "xo_therm_pu2"; | |
| reg = <0xb2>; | |
| }; | |
| chan@6 { | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,calibration-type = "absolute"; | |
| qcom,decimation = <0x00>; | |
| qcom,scale-function = <0x00>; | |
| qcom,hw-settle-time = <0x00>; | |
| qcom,pre-div-channel-scaling = <0x01>; | |
| label = "vbat_sns"; | |
| reg = <0x06>; | |
| }; | |
| chan@8 { | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,calibration-type = "absolute"; | |
| qcom,decimation = <0x00>; | |
| qcom,scale-function = <0x03>; | |
| qcom,hw-settle-time = <0x00>; | |
| qcom,pre-div-channel-scaling = <0x00>; | |
| label = "die_temp"; | |
| reg = <0x08>; | |
| }; | |
| chan@14 { | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,calibration-type = "ratiometric"; | |
| qcom,decimation = <0x00>; | |
| qcom,scale-function = <0x02>; | |
| qcom,hw-settle-time = <0x02>; | |
| qcom,pre-div-channel-scaling = <0x00>; | |
| label = "pa_therm0"; | |
| reg = <0x14>; | |
| }; | |
| chan@31 { | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,calibration-type = "ratiometric"; | |
| qcom,decimation = <0x00>; | |
| qcom,scale-function = <0x00>; | |
| qcom,hw-settle-time = <0x02>; | |
| qcom,pre-div-channel-scaling = <0x00>; | |
| label = "batt_id"; | |
| reg = <0x31>; | |
| }; | |
| }; | |
| qcom,pm8226_rtc { | |
| spmi-dev-container; | |
| qcom,qpnp-rtc-alarm-pwrup = <0x00>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| qcom,qpnp-rtc-write = <0x00>; | |
| compatible = "qcom,qpnp-rtc"; | |
| qcom,pm8226_rtc_alarm@6100 { | |
| interrupts = <0x00 0x61 0x01>; | |
| reg = <0x6100 0x100>; | |
| }; | |
| qcom,pm8226_rtc_rw@6000 { | |
| reg = <0x6000 0x100>; | |
| }; | |
| }; | |
| qcom,revid@100 { | |
| compatible = "qcom,qpnp-revid"; | |
| phandle = <0x4c>; | |
| reg = <0x100 0x100>; | |
| linux,phandle = <0x4c>; | |
| }; | |
| iadc@3600 { | |
| qcom,rsense = <0x989680>; | |
| interrupts = <0x00 0x36 0x00>; | |
| qcom,iadc-poll-eoc; | |
| qcom,adc-bit-resolution = <0x10>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,iadc-vadc = <0x3c>; | |
| compatible = "qcom,qpnp-iadc"; | |
| qcom,adc-vdd-reference = <0x708>; | |
| phandle = <0x4e>; | |
| reg = <0x3600 0x100>; | |
| interrupt-names = "eoc-int-en-set"; | |
| linux,phandle = <0x4e>; | |
| chan@0 { | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,calibration-type = "absolute"; | |
| qcom,decimation = <0x00>; | |
| qcom,scale-function = <0x00>; | |
| qcom,hw-settle-time = <0x00>; | |
| qcom,pre-div-channel-scaling = <0x01>; | |
| label = "internal_rsense"; | |
| reg = <0x00>; | |
| }; | |
| chan@1 { | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,calibration-type = "absolute"; | |
| qcom,decimation = <0x00>; | |
| qcom,scale-function = <0x00>; | |
| qcom,hw-settle-time = <0x00>; | |
| qcom,pre-div-channel-scaling = <0x01>; | |
| label = "external_rsense"; | |
| reg = <0x01>; | |
| }; | |
| }; | |
| qcom,leds@a500 { | |
| status = "okay"; | |
| label = "mpp"; | |
| compatible = "qcom,leds-qpnp-rgb"; | |
| reg = <0xa500 0x100>; | |
| qcom,led_rgb { | |
| linux,name = "rgb"; | |
| qcom,max-current = <0x0c>; | |
| label = "combo"; | |
| qcom,id = <0x09>; | |
| }; | |
| qcom,led_mpp_6 { | |
| linux,name = "white"; | |
| qcom,current-setting = <0x05>; | |
| qcom,mode = "pwm"; | |
| linux,default-trigger = "none"; | |
| qcom,default-state = "off"; | |
| qcom,max-current = <0x28>; | |
| qcom,pwm-us = <0x3e8>; | |
| qcom,pwm-channel = <0x05>; | |
| label = "mpp"; | |
| qcom,id = <0x06>; | |
| qcom,source-sel = <0x0a>; | |
| qcom,mode-ctrl = <0x60>; | |
| }; | |
| }; | |
| qcom,leds@1000 { | |
| status = "ok"; | |
| compatible = "qcom,leds-qpnp"; | |
| reg = <0x1000 0x100>; | |
| qcom,led_atc { | |
| linux,name = "charging"; | |
| qcom,mode = <0x02>; | |
| qcom,max-current = <0x28>; | |
| label = "atc"; | |
| qcom,id = <0x08>; | |
| }; | |
| }; | |
| vadc@3400 { | |
| qcom,adc-batt-therm-type = <0x01>; | |
| interrupts = <0x00 0x34 0x00 0x00 0x34 0x03 0x00 0x34 0x04>; | |
| qcom,adc-bit-resolution = <0x0f>; | |
| #address-cells = <0x01>; | |
| qcom,adc_tm-vadc = <0x3c>; | |
| #size-cells = <0x00>; | |
| compatible = "qcom,qpnp-adc-tm"; | |
| qcom,adc-vdd-reference = <0x708>; | |
| phandle = <0x48>; | |
| reg = <0x3400 0x100>; | |
| interrupt-names = "eoc-int-en-set\0high-thr-en-set\0low-thr-en-set"; | |
| linux,phandle = <0x48>; | |
| chan@30 { | |
| qcom,btm-channel-number = <0x48>; | |
| qcom,fast-avg-setup = <0x03>; | |
| qcom,calibration-type = "ratiometric"; | |
| qcom,meas-interval-timer-idx = <0x02>; | |
| qcom,decimation = <0x00>; | |
| qcom,scale-function = <0x01>; | |
| qcom,hw-settle-time = <0x02>; | |
| qcom,pre-div-channel-scaling = <0x00>; | |
| label = "batt_therm"; | |
| reg = <0x30>; | |
| }; | |
| chan@17 { | |
| qcom,btm-channel-number = <0x80>; | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,calibration-type = "ratiometric"; | |
| qcom,decimation = <0x00>; | |
| qcom,scale-function = <0x02>; | |
| qcom,hw-settle-time = <0x02>; | |
| qcom,pre-div-channel-scaling = <0x00>; | |
| label = "pa_therm1"; | |
| qcom,thermal-node; | |
| reg = <0x17>; | |
| }; | |
| chan@6 { | |
| qcom,btm-channel-number = <0x70>; | |
| qcom,fast-avg-setup = <0x03>; | |
| qcom,calibration-type = "absolute"; | |
| qcom,decimation = <0x00>; | |
| qcom,scale-function = <0x00>; | |
| qcom,hw-settle-time = <0x00>; | |
| qcom,pre-div-channel-scaling = <0x01>; | |
| label = "vbat_sns"; | |
| reg = <0x06>; | |
| }; | |
| chan@8 { | |
| qcom,btm-channel-number = <0x68>; | |
| qcom,fast-avg-setup = <0x03>; | |
| qcom,calibration-type = "absolute"; | |
| qcom,decimation = <0x00>; | |
| qcom,scale-function = <0x03>; | |
| qcom,hw-settle-time = <0x00>; | |
| qcom,pre-div-channel-scaling = <0x00>; | |
| label = "die_temp"; | |
| reg = <0x08>; | |
| }; | |
| chan@14 { | |
| qcom,btm-channel-number = <0x78>; | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,calibration-type = "ratiometric"; | |
| qcom,decimation = <0x00>; | |
| qcom,scale-function = <0x02>; | |
| qcom,hw-settle-time = <0x02>; | |
| qcom,pre-div-channel-scaling = <0x00>; | |
| label = "pa_therm0"; | |
| qcom,thermal-node; | |
| reg = <0x14>; | |
| }; | |
| }; | |
| }; | |
| qcom,pm8226@1 { | |
| spmi-slave-container; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| reg = <0x01>; | |
| pwm@b200 { | |
| reg-names = "qpnp-lpg-channel-base\0qpnp-lpg-lut-base"; | |
| compatible = "qcom,qpnp-pwm"; | |
| qcom,channel-id = <0x01>; | |
| reg = <0xb200 0x100 0xb042 0x7e>; | |
| }; | |
| pwm@b500 { | |
| reg-names = "qpnp-lpg-channel-base\0qpnp-lpg-lut-base"; | |
| compatible = "qcom,qpnp-pwm"; | |
| qcom,channel-id = <0x04>; | |
| reg = <0xb500 0x100 0xb042 0x7e>; | |
| }; | |
| regulator@4e00 { | |
| regulator-name = "8226_l15"; | |
| status = "disabled"; | |
| compatible = "qcom,qpnp-regulator"; | |
| reg = <0x4e00 0x100>; | |
| }; | |
| regulator@5900 { | |
| regulator-name = "8226_l26"; | |
| status = "disabled"; | |
| compatible = "qcom,qpnp-regulator"; | |
| reg = <0x5900 0x100>; | |
| }; | |
| regulator@5500 { | |
| regulator-name = "8226_l22"; | |
| status = "disabled"; | |
| compatible = "qcom,qpnp-regulator"; | |
| reg = <0x5500 0x100>; | |
| }; | |
| qcom,leds@d300 { | |
| status = "okay"; | |
| label = "flash"; | |
| compatible = "qcom,leds-qpnp"; | |
| reg = <0xd300 0x100>; | |
| qcom,flash_torch { | |
| linux,name = "led:flash_torch"; | |
| qcom,torch-enable; | |
| linux,default-trigger = "torch_trigger"; | |
| qcom,default-state = "off"; | |
| qcom,current = <0xb4>; | |
| qcom,max-current = <0xc8>; | |
| label = "flash"; | |
| qcom,id = <0x01>; | |
| phandle = <0x5d>; | |
| linux,phandle = <0x5d>; | |
| }; | |
| qcom,flash_0 { | |
| linux,name = "led:flash_0"; | |
| qcom,safety-timer; | |
| qcom,duration = <0x500>; | |
| linux,default-trigger = "flash0_trigger"; | |
| qcom,default-state = "off"; | |
| qcom,headroom = <0x03>; | |
| qcom,current = <0x3e8>; | |
| qcom,clamp-curr = <0xc8>; | |
| qcom,startup-dly = <0x03>; | |
| qcom,max-current = <0x3e8>; | |
| label = "flash"; | |
| qcom,id = <0x01>; | |
| phandle = <0x5c>; | |
| linux,phandle = <0x5c>; | |
| }; | |
| }; | |
| regulator@4200 { | |
| regulator-name = "8226_l3"; | |
| status = "disabled"; | |
| compatible = "qcom,qpnp-regulator"; | |
| reg = <0x4200 0x100>; | |
| }; | |
| regulator@5400 { | |
| regulator-name = "8226_l21"; | |
| status = "disabled"; | |
| compatible = "qcom,qpnp-regulator"; | |
| reg = <0x5400 0x100>; | |
| }; | |
| pwm@b600 { | |
| reg-names = "qpnp-lpg-channel-base\0qpnp-lpg-lut-base"; | |
| compatible = "qcom,qpnp-pwm"; | |
| qcom,channel-id = <0x05>; | |
| reg = <0xb600 0x100 0xb042 0x7e>; | |
| }; | |
| regulator@5200 { | |
| regulator-name = "8226_l19"; | |
| status = "disabled"; | |
| compatible = "qcom,qpnp-regulator"; | |
| reg = <0x5200 0x100>; | |
| }; | |
| regulator@5600 { | |
| regulator-name = "8226_l23"; | |
| status = "disabled"; | |
| compatible = "qcom,qpnp-regulator"; | |
| reg = <0x5600 0x100>; | |
| }; | |
| pwm@b100 { | |
| reg-names = "qpnp-lpg-channel-base\0qpnp-lpg-lut-base"; | |
| compatible = "qcom,qpnp-pwm"; | |
| qcom,channel-id = <0x00>; | |
| reg = <0xb100 0x100 0xb042 0x7e>; | |
| }; | |
| regulator@5100 { | |
| regulator-name = "8226_l18"; | |
| status = "disabled"; | |
| compatible = "qcom,qpnp-regulator"; | |
| reg = <0x5100 0x100>; | |
| }; | |
| regulator@5300 { | |
| regulator-name = "8226_l20"; | |
| status = "disabled"; | |
| compatible = "qcom,qpnp-regulator"; | |
| reg = <0x5300 0x100>; | |
| }; | |
| regulator@4000 { | |
| regulator-name = "8226_l1"; | |
| status = "disabled"; | |
| compatible = "qcom,qpnp-regulator"; | |
| reg = <0x4000 0x100>; | |
| }; | |
| regulator@4400 { | |
| regulator-name = "8226_l5"; | |
| status = "disabled"; | |
| compatible = "qcom,qpnp-regulator"; | |
| reg = <0x4400 0x100>; | |
| }; | |
| regulator@4d00 { | |
| regulator-name = "8226_l14"; | |
| status = "disabled"; | |
| compatible = "qcom,qpnp-regulator"; | |
| reg = <0x4d00 0x100>; | |
| }; | |
| regulator@1d00 { | |
| spmi-dev-container; | |
| regulator-name = "8226_s4"; | |
| status = "disabled"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| compatible = "qcom,qpnp-regulator"; | |
| reg = <0x1d00 0x300>; | |
| qcom,ctl@1d00 { | |
| reg = <0x1d00 0x100>; | |
| }; | |
| qcom,freq@1f00 { | |
| reg = <0x1f00 0x100>; | |
| }; | |
| qcom,ps@1e00 { | |
| reg = <0x1e00 0x100>; | |
| }; | |
| }; | |
| regulator@4900 { | |
| regulator-name = "8226_l10"; | |
| status = "disabled"; | |
| compatible = "qcom,qpnp-regulator"; | |
| reg = <0x4900 0x100>; | |
| }; | |
| regulator@1a00 { | |
| spmi-dev-container; | |
| regulator-name = "8226_s3"; | |
| status = "disabled"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| compatible = "qcom,qpnp-regulator"; | |
| reg = <0x1a00 0x300>; | |
| qcom,ps@1b00 { | |
| reg = <0x1b00 0x100>; | |
| }; | |
| qcom,ctl@1a00 { | |
| reg = <0x1a00 0x100>; | |
| }; | |
| qcom,freq@1c00 { | |
| reg = <0x1c00 0x100>; | |
| }; | |
| }; | |
| regulator@1400 { | |
| spmi-dev-container; | |
| regulator-name = "8226_s1"; | |
| status = "disabled"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| compatible = "qcom,qpnp-regulator"; | |
| reg = <0x1400 0x300>; | |
| qcom,freq@1600 { | |
| reg = <0x1600 0x100>; | |
| }; | |
| qcom,ctl@1400 { | |
| reg = <0x1400 0x100>; | |
| }; | |
| qcom,ps@1500 { | |
| reg = <0x1500 0x100>; | |
| }; | |
| }; | |
| spm-regulator@1700 { | |
| qcom,mode = "auto"; | |
| regulator-max-microvolt = <0x149970>; | |
| regulator-name = "8226_s2"; | |
| regulator-min-microvolt = <0xdbba0>; | |
| compatible = "qcom,spm-regulator"; | |
| phandle = <0x59>; | |
| reg = <0x1700 0x100>; | |
| linux,phandle = <0x59>; | |
| }; | |
| regulator@1700 { | |
| spmi-dev-container; | |
| regulator-name = "8226_s2"; | |
| status = "disabled"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| compatible = "qcom,qpnp-regulator"; | |
| reg = <0x1700 0x300>; | |
| qcom,freq@1900 { | |
| reg = <0x1900 0x100>; | |
| }; | |
| qcom,ctl@1700 { | |
| reg = <0x1700 0x100>; | |
| }; | |
| qcom,ps@1800 { | |
| reg = <0x1800 0x100>; | |
| }; | |
| }; | |
| regulator@4600 { | |
| regulator-name = "8226_l7"; | |
| status = "disabled"; | |
| compatible = "qcom,qpnp-regulator"; | |
| reg = <0x4600 0x100>; | |
| }; | |
| regulator@4800 { | |
| regulator-name = "8226_l9"; | |
| status = "disabled"; | |
| compatible = "qcom,qpnp-regulator"; | |
| reg = <0x4800 0x100>; | |
| }; | |
| regulator@4100 { | |
| regulator-name = "8226_l2"; | |
| status = "disabled"; | |
| compatible = "qcom,qpnp-regulator"; | |
| reg = <0x4100 0x100>; | |
| }; | |
| regulator@5700 { | |
| regulator-name = "8226_l24"; | |
| status = "disabled"; | |
| compatible = "qcom,qpnp-regulator"; | |
| reg = <0x5700 0x100>; | |
| }; | |
| regulator@5b00 { | |
| regulator-name = "8226_l28"; | |
| status = "disabled"; | |
| compatible = "qcom,qpnp-regulator"; | |
| reg = <0x5b00 0x100>; | |
| }; | |
| pwm@b400 { | |
| reg-names = "qpnp-lpg-channel-base\0qpnp-lpg-lut-base"; | |
| compatible = "qcom,qpnp-pwm"; | |
| qcom,channel-id = <0x03>; | |
| reg = <0xb400 0x100 0xb042 0x7e>; | |
| }; | |
| regulator@5a00 { | |
| regulator-name = "8226_l27"; | |
| status = "disabled"; | |
| compatible = "qcom,qpnp-regulator"; | |
| reg = <0x5a00 0x100>; | |
| }; | |
| regulator@4300 { | |
| regulator-name = "8226_l4"; | |
| status = "disabled"; | |
| compatible = "qcom,qpnp-regulator"; | |
| reg = <0x4300 0x100>; | |
| }; | |
| regulator@2000 { | |
| spmi-dev-container; | |
| regulator-name = "8226_s5"; | |
| status = "disabled"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| compatible = "qcom,qpnp-regulator"; | |
| reg = <0x2000 0x300>; | |
| qcom,ps@2100 { | |
| reg = <0x2100 0x100>; | |
| }; | |
| qcom,ctl@2000 { | |
| reg = <0x2000 0x100>; | |
| }; | |
| qcom,freq@2200 { | |
| reg = <0x2200 0x100>; | |
| }; | |
| }; | |
| regulator@4f00 { | |
| regulator-name = "8226_l16"; | |
| status = "disabled"; | |
| compatible = "qcom,qpnp-regulator"; | |
| reg = <0x4f00 0x100>; | |
| }; | |
| qcom,vibrator@c000 { | |
| qcom,vib-boot-up-vibe-ms = <0x64>; | |
| status = "okay"; | |
| qcom,vib-timeout-ms = <0x7530>; | |
| label = "vibrator"; | |
| compatible = "qcom,qpnp-vibrator"; | |
| qcom,vib-vtg-level-mV = <0x708>; | |
| qcom,vib-vtg-level-mV-haptic = <0xaf0>; | |
| reg = <0xc000 0x100>; | |
| }; | |
| regulator@4b00 { | |
| regulator-name = "8226_l12"; | |
| status = "disabled"; | |
| compatible = "qcom,qpnp-regulator"; | |
| reg = <0x4b00 0x100>; | |
| }; | |
| qcom,leds@d800 { | |
| status = "okay"; | |
| label = "wled"; | |
| compatible = "qcom,leds-qpnp"; | |
| reg = <0xd800 0x100>; | |
| qcom,wled_0 { | |
| linux,name = "wled:backlight"; | |
| qcom,cs-out-en; | |
| qcom,boost-curr-lim = <0x03>; | |
| qcom,cp-sel = <0x00>; | |
| linux,default-trigger = "bkl-trigger"; | |
| qcom,default-state = "off"; | |
| qcom,num-strings = <0x01>; | |
| qcom,ovp-val = <0x02>; | |
| qcom,max-current = <0x12>; | |
| qcom,ctrl-delay-us = <0x00>; | |
| qcom,mod-scheme = <0x00>; | |
| label = "wled"; | |
| qcom,id = <0x00>; | |
| qcom,op-fdbck = <0x01>; | |
| qcom,switch-freq = <0x0b>; | |
| qcom,max-boost-duty = <0x02>; | |
| mmi,panels { | |
| panel@0 { | |
| panel_name = "mipi_mot_video_cmi_hd_450"; | |
| version = <0x85>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| regulator@8000 { | |
| regulator-name = "8226_lvs1"; | |
| status = "disabled"; | |
| compatible = "qcom,qpnp-regulator"; | |
| reg = <0x8000 0x100>; | |
| }; | |
| pwm@b300 { | |
| reg-names = "qpnp-lpg-channel-base\0qpnp-lpg-lut-base"; | |
| compatible = "qcom,qpnp-pwm"; | |
| qcom,channel-id = <0x02>; | |
| reg = <0xb300 0x100 0xb042 0x7e>; | |
| }; | |
| regulator@4700 { | |
| regulator-name = "8226_l8"; | |
| status = "disabled"; | |
| compatible = "qcom,qpnp-regulator"; | |
| reg = <0x4700 0x100>; | |
| }; | |
| regulator@5000 { | |
| regulator-name = "8226_l17"; | |
| status = "disabled"; | |
| compatible = "qcom,qpnp-regulator"; | |
| reg = <0x5000 0x100>; | |
| }; | |
| regulator@4500 { | |
| regulator-name = "8226_l6"; | |
| status = "disabled"; | |
| compatible = "qcom,qpnp-regulator"; | |
| reg = <0x4500 0x100>; | |
| }; | |
| }; | |
| }; | |
| jtagmm@fc33f000 { | |
| reg-names = "etm-base\0debug-base"; | |
| compatible = "qcom,jtag-mm"; | |
| reg = <0xfc33f000 0x1000 0xfc336000 0x1000>; | |
| }; | |
| qcom,smp2pgpio-smp2p-1-out { | |
| gpio-controller; | |
| #interrupt-cells = <0x02>; | |
| #gpio-cells = <0x02>; | |
| qcom,entry-name = "smp2p"; | |
| compatible = "qcom,smp2pgpio"; | |
| interrupt-controller; | |
| qcom,remote-pid = <0x01>; | |
| phandle = <0x16>; | |
| linux,phandle = <0x16>; | |
| }; | |
| wcn_etm0 { | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x10>; | |
| coresight-child-list = <0x2f>; | |
| coresight-outports = <0x00>; | |
| coresight-child-ports = <0x02>; | |
| compatible = "qcom,coresight-wcn-etm"; | |
| coresight-name = "coresight-wcn-etm0"; | |
| }; | |
| qcom,ispif@fda0a000 { | |
| reg-names = "ispif\0csi_clk_mux"; | |
| interrupts = <0x00 0x37 0x00>; | |
| cell-index = <0x00>; | |
| compatible = "qcom,ispif"; | |
| reg = <0xfda0a000 0x500 0xfda00020 0x10>; | |
| interrupt-names = "ispif"; | |
| }; | |
| qcom,smp2pgpio-smp2p-2-in { | |
| gpio-controller; | |
| #interrupt-cells = <0x02>; | |
| qcom,is-inbound; | |
| #gpio-cells = <0x02>; | |
| qcom,entry-name = "smp2p"; | |
| compatible = "qcom,smp2pgpio"; | |
| interrupt-controller; | |
| qcom,remote-pid = <0x02>; | |
| phandle = <0x17>; | |
| linux,phandle = <0x17>; | |
| }; | |
| qcom,rpm-smd { | |
| rpm-channel-name = "rpm_requests"; | |
| rpm-channel-type = <0x0f>; | |
| compatible = "qcom,rpm-smd"; | |
| rpm-regulator-ldoa9 { | |
| qcom,resource-id = <0x09>; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,resource-name = "ldoa"; | |
| status = "okay"; | |
| compatible = "qcom,rpm-regulator-smd-resource"; | |
| qcom,regulator-type = <0x00>; | |
| regulator-l9 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x1f47d0>; | |
| regulator-name = "8226_l9"; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x1f47d0>; | |
| qcom,init-voltage = <0x1f47d0>; | |
| compatible = "qcom,rpm-regulator-smd"; | |
| }; | |
| }; | |
| rpm-regulator-ldoa16 { | |
| qcom,resource-id = <0x10>; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,resource-name = "ldoa"; | |
| status = "okay"; | |
| compatible = "qcom,rpm-regulator-smd-resource"; | |
| qcom,regulator-type = <0x00>; | |
| regulator-l16 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x331df0>; | |
| regulator-name = "8226_l16"; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x2dc6c0>; | |
| qcom,init-voltage = <0x325aa0>; | |
| compatible = "qcom,rpm-regulator-smd"; | |
| phandle = <0x47>; | |
| linux,phandle = <0x47>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa22 { | |
| qcom,resource-id = <0x16>; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,resource-name = "ldoa"; | |
| status = "okay"; | |
| compatible = "qcom,rpm-regulator-smd-resource"; | |
| qcom,regulator-type = <0x00>; | |
| regulator-l22 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x2d0370>; | |
| regulator-name = "8226_l22"; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x1b7740>; | |
| qcom,init-voltage = <0x2d0370>; | |
| compatible = "qcom,rpm-regulator-smd"; | |
| }; | |
| }; | |
| rpm-regulator-ldoa17 { | |
| qcom,resource-id = <0x11>; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,resource-name = "ldoa"; | |
| status = "okay"; | |
| compatible = "qcom,rpm-regulator-smd-resource"; | |
| qcom,regulator-type = <0x00>; | |
| regulator-l17 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x2d0370>; | |
| regulator-name = "8226_l17"; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x2d0370>; | |
| qcom,init-voltage = <0x2d0370>; | |
| compatible = "qcom,rpm-regulator-smd"; | |
| phandle = <0x49>; | |
| linux,phandle = <0x49>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa19 { | |
| qcom,resource-id = <0x13>; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,resource-name = "ldoa"; | |
| status = "okay"; | |
| compatible = "qcom,rpm-regulator-smd-resource"; | |
| qcom,regulator-type = <0x00>; | |
| regulator-l19 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x2b7cd0>; | |
| regulator-name = "8226_l19"; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x2b7cd0>; | |
| qcom,init-voltage = <0x2b7cd0>; | |
| compatible = "qcom,rpm-regulator-smd"; | |
| phandle = <0x0d>; | |
| linux,phandle = <0x0d>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa15 { | |
| qcom,resource-id = <0x0f>; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,resource-name = "ldoa"; | |
| status = "okay"; | |
| compatible = "qcom,rpm-regulator-smd-resource"; | |
| qcom,regulator-type = <0x00>; | |
| regulator-l15 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x2ab980>; | |
| regulator-name = "8226_l15"; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x2ab980>; | |
| qcom,init-voltage = <0x2ab980>; | |
| compatible = "qcom,rpm-regulator-smd"; | |
| phandle = <0x0e>; | |
| linux,phandle = <0x0e>; | |
| }; | |
| }; | |
| rpm-regulator-smpa3 { | |
| qcom,resource-id = <0x03>; | |
| qcom,hpm-min-load = <0x186a0>; | |
| qcom,resource-name = "smpa"; | |
| status = "okay"; | |
| compatible = "qcom,rpm-regulator-smd-resource"; | |
| qcom,regulator-type = <0x01>; | |
| regulator-s3 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x13d620>; | |
| regulator-name = "8226_s3"; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x124f80>; | |
| qcom,init-voltage = <0x124f80>; | |
| compatible = "qcom,rpm-regulator-smd"; | |
| }; | |
| }; | |
| rpm-regulator-smpa4 { | |
| qcom,resource-id = <0x04>; | |
| qcom,hpm-min-load = <0x186a0>; | |
| qcom,resource-name = "smpa"; | |
| status = "okay"; | |
| compatible = "qcom,rpm-regulator-smd-resource"; | |
| qcom,regulator-type = <0x01>; | |
| regulator-s4 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x2191c0>; | |
| regulator-name = "8226_s4"; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x1b7740>; | |
| qcom,init-voltage = <0x1b7740>; | |
| compatible = "qcom,rpm-regulator-smd"; | |
| phandle = <0x41>; | |
| linux,phandle = <0x41>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa5 { | |
| qcom,resource-id = <0x05>; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,resource-name = "ldoa"; | |
| status = "okay"; | |
| compatible = "qcom,rpm-regulator-smd-resource"; | |
| qcom,regulator-type = <0x00>; | |
| regulator-l5 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x124f80>; | |
| regulator-name = "8226_l5"; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x124f80>; | |
| qcom,init-voltage = <0x124f80>; | |
| compatible = "qcom,rpm-regulator-smd"; | |
| phandle = <0x0c>; | |
| linux,phandle = <0x0c>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa12 { | |
| qcom,resource-id = <0x0c>; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,resource-name = "ldoa"; | |
| status = "okay"; | |
| compatible = "qcom,rpm-regulator-smd-resource"; | |
| qcom,regulator-type = <0x00>; | |
| regulator-l12 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x1b7740>; | |
| regulator-name = "8226_l12"; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x1b7740>; | |
| qcom,init-voltage = <0x1b7740>; | |
| compatible = "qcom,rpm-regulator-smd"; | |
| }; | |
| }; | |
| rpm-regulator-ldoa25 { | |
| qcom,resource-id = <0x19>; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,resource-name = "ldoa"; | |
| status = "okay"; | |
| compatible = "qcom,rpm-regulator-smd-resource"; | |
| qcom,regulator-type = <0x00>; | |
| regulator-l25 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x206cc8>; | |
| regulator-name = "8226_l25"; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x1b1598>; | |
| qcom,init-voltage = <0x1b1598>; | |
| compatible = "qcom,rpm-regulator-smd"; | |
| phandle = <0x42>; | |
| linux,phandle = <0x42>; | |
| }; | |
| }; | |
| rpm-regulator-smpa5 { | |
| qcom,resource-id = <0x05>; | |
| qcom,hpm-min-load = <0x186a0>; | |
| qcom,resource-name = "smpa"; | |
| status = "okay"; | |
| compatible = "qcom,rpm-regulator-smd-resource"; | |
| qcom,regulator-type = <0x01>; | |
| regulator-s5 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x118c30>; | |
| regulator-name = "8226_s5"; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x118c30>; | |
| qcom,init-voltage = <0x118c30>; | |
| compatible = "qcom,rpm-regulator-smd"; | |
| }; | |
| }; | |
| rpm-regulator-ldoa6 { | |
| qcom,resource-id = <0x06>; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,resource-name = "ldoa"; | |
| status = "okay"; | |
| compatible = "qcom,rpm-regulator-smd-resource"; | |
| qcom,regulator-type = <0x00>; | |
| regulator-l6 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x1b7740>; | |
| regulator-name = "8226_l6"; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x1b7740>; | |
| qcom,init-voltage = <0x1b7740>; | |
| compatible = "qcom,rpm-regulator-smd"; | |
| phandle = <0x0b>; | |
| linux,phandle = <0x0b>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa23 { | |
| qcom,resource-id = <0x17>; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,resource-name = "ldoa"; | |
| status = "okay"; | |
| compatible = "qcom,rpm-regulator-smd-resource"; | |
| qcom,regulator-type = <0x00>; | |
| regulator-l23 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x2d0370>; | |
| regulator-name = "8226_l23"; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x1b7740>; | |
| qcom,init-voltage = <0x2d0370>; | |
| compatible = "qcom,rpm-regulator-smd"; | |
| }; | |
| }; | |
| rpm-regulator-ldoa28 { | |
| qcom,resource-id = <0x1c>; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,resource-name = "ldoa"; | |
| status = "okay"; | |
| compatible = "qcom,rpm-regulator-smd-resource"; | |
| qcom,regulator-type = <0x00>; | |
| regulator-l28 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x33e140>; | |
| regulator-name = "8226_l28"; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x1b7740>; | |
| qcom,init-voltage = <0x2f4d60>; | |
| compatible = "qcom,rpm-regulator-smd"; | |
| regulator-boot-on; | |
| phandle = <0x22>; | |
| linux,phandle = <0x22>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa1 { | |
| qcom,resource-id = <0x01>; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,resource-name = "ldoa"; | |
| status = "okay"; | |
| compatible = "qcom,rpm-regulator-smd-resource"; | |
| qcom,regulator-type = <0x00>; | |
| regulator-l1 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x12b128>; | |
| regulator-name = "8226_l1"; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x12b128>; | |
| qcom,init-voltage = <0x12b128>; | |
| compatible = "qcom,rpm-regulator-smd"; | |
| }; | |
| }; | |
| rpm-regulator-ldoa27 { | |
| qcom,resource-id = <0x1b>; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,resource-name = "ldoa"; | |
| status = "okay"; | |
| compatible = "qcom,rpm-regulator-smd-resource"; | |
| qcom,regulator-type = <0x00>; | |
| regulator-l27 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x1f47d0>; | |
| regulator-name = "8226_l27"; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x1f47d0>; | |
| qcom,init-voltage = <0x1f47d0>; | |
| compatible = "qcom,rpm-regulator-smd"; | |
| }; | |
| }; | |
| rpm-regulator-ldoa18 { | |
| qcom,resource-id = <0x12>; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,resource-name = "ldoa"; | |
| status = "okay"; | |
| compatible = "qcom,rpm-regulator-smd-resource"; | |
| qcom,regulator-type = <0x00>; | |
| regulator-l18 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x2d0370>; | |
| regulator-name = "8226_l18"; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x2d0370>; | |
| qcom,init-voltage = <0x2d0370>; | |
| compatible = "qcom,rpm-regulator-smd"; | |
| phandle = <0x28>; | |
| linux,phandle = <0x28>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa20 { | |
| qcom,resource-id = <0x14>; | |
| qcom,hpm-min-load = <0x1388>; | |
| qcom,resource-name = "ldoa"; | |
| status = "okay"; | |
| compatible = "qcom,rpm-regulator-smd-resource"; | |
| qcom,regulator-type = <0x00>; | |
| regulator-l20 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x2eebb8>; | |
| regulator-name = "8226_l20"; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x2eebb8>; | |
| qcom,init-voltage = <0x2eebb8>; | |
| compatible = "qcom,rpm-regulator-smd"; | |
| phandle = <0x3b>; | |
| linux,phandle = <0x3b>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa2 { | |
| qcom,resource-id = <0x02>; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,resource-name = "ldoa"; | |
| status = "okay"; | |
| compatible = "qcom,rpm-regulator-smd-resource"; | |
| qcom,regulator-type = <0x00>; | |
| regulator-l2 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x124f80>; | |
| regulator-name = "8226_l2"; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x124f80>; | |
| qcom,init-voltage = <0x124f80>; | |
| compatible = "qcom,rpm-regulator-smd"; | |
| }; | |
| }; | |
| rpm-regulator-ldoa10 { | |
| qcom,resource-id = <0x0a>; | |
| qcom,hpm-min-load = <0x1388>; | |
| qcom,resource-name = "ldoa"; | |
| status = "okay"; | |
| compatible = "qcom,rpm-regulator-smd-resource"; | |
| qcom,regulator-type = <0x00>; | |
| regulator-l10 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x1b7740>; | |
| regulator-name = "8226_l10"; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x1b7740>; | |
| qcom,init-voltage = <0x1b7740>; | |
| compatible = "qcom,rpm-regulator-smd"; | |
| phandle = <0x3a>; | |
| linux,phandle = <0x3a>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa8 { | |
| qcom,resource-id = <0x08>; | |
| qcom,hpm-min-load = <0x1388>; | |
| qcom,resource-name = "ldoa"; | |
| status = "okay"; | |
| compatible = "qcom,rpm-regulator-smd-resource"; | |
| qcom,regulator-type = <0x00>; | |
| regulator-l8-so { | |
| qcom,set = <0x02>; | |
| regulator-max-microvolt = <0x1b7740>; | |
| regulator-name = "8226_l8_so"; | |
| regulator-min-microvolt = <0x1b7740>; | |
| qcom,init-voltage = <0x1b7740>; | |
| compatible = "qcom,rpm-regulator-smd"; | |
| qcom,init-enable = <0x00>; | |
| }; | |
| regulator-l8 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x1b7740>; | |
| regulator-name = "8226_l8"; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x1b7740>; | |
| qcom,init-voltage = <0x1b7740>; | |
| compatible = "qcom,rpm-regulator-smd"; | |
| phandle = <0x20>; | |
| linux,phandle = <0x20>; | |
| }; | |
| regulator-l8-ao { | |
| qcom,consumer-supplies = "vdd_sr2_pll\0"; | |
| qcom,set = <0x01>; | |
| regulator-max-microvolt = <0x1b7740>; | |
| regulator-name = "8226_l8_ao"; | |
| regulator-min-microvolt = <0x1b7740>; | |
| qcom,init-voltage = <0x1b7740>; | |
| compatible = "qcom,rpm-regulator-smd"; | |
| }; | |
| }; | |
| rpm-regulator-vsa1 { | |
| qcom,resource-id = <0x01>; | |
| qcom,resource-name = "vsa"; | |
| status = "okay"; | |
| compatible = "qcom,rpm-regulator-smd-resource"; | |
| qcom,regulator-type = <0x02>; | |
| regulator-lvs1 { | |
| qcom,set = <0x03>; | |
| regulator-name = "8226_lvs1"; | |
| status = "okay"; | |
| regulator-always-on; | |
| compatible = "qcom,rpm-regulator-smd"; | |
| phandle = <0x50>; | |
| linux,phandle = <0x50>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa24 { | |
| qcom,resource-id = <0x18>; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,resource-name = "ldoa"; | |
| status = "okay"; | |
| compatible = "qcom,rpm-regulator-smd-resource"; | |
| qcom,regulator-type = <0x00>; | |
| regulator-l24 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x149970>; | |
| regulator-name = "8226_l24"; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x13d620>; | |
| qcom,init-voltage = <0x13d620>; | |
| compatible = "qcom,rpm-regulator-smd"; | |
| phandle = <0x46>; | |
| linux,phandle = <0x46>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa14 { | |
| qcom,resource-id = <0x0e>; | |
| qcom,hpm-min-load = <0x1388>; | |
| qcom,resource-name = "ldoa"; | |
| status = "okay"; | |
| compatible = "qcom,rpm-regulator-smd-resource"; | |
| qcom,regulator-type = <0x00>; | |
| regulator-l14 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x29f630>; | |
| regulator-name = "8226_l14"; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x29f630>; | |
| qcom,init-voltage = <0x29f630>; | |
| compatible = "qcom,rpm-regulator-smd"; | |
| }; | |
| }; | |
| rpm-regulator-smpa1 { | |
| qcom,resource-id = <0x01>; | |
| qcom,hpm-min-load = <0x186a0>; | |
| qcom,resource-name = "smpa"; | |
| status = "okay"; | |
| compatible = "qcom,rpm-regulator-smd-resource"; | |
| qcom,regulator-type = <0x01>; | |
| regulator-s1-corner-ao { | |
| qcom,consumer-supplies = "vdd_sr2_dig\0"; | |
| qcom,set = <0x01>; | |
| qcom,use-voltage-corner; | |
| regulator-max-microvolt = <0x07>; | |
| regulator-name = "8226_s1_corner_ao"; | |
| regulator-min-microvolt = <0x01>; | |
| compatible = "qcom,rpm-regulator-smd"; | |
| }; | |
| regulator-s1 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x137478>; | |
| regulator-name = "8226_s1"; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x7a120>; | |
| compatible = "qcom,rpm-regulator-smd"; | |
| phandle = <0x45>; | |
| linux,phandle = <0x45>; | |
| }; | |
| regulator-s1-corner { | |
| qcom,consumer-supplies = "vdd_dig\0"; | |
| qcom,set = <0x03>; | |
| qcom,use-voltage-corner; | |
| regulator-max-microvolt = <0x07>; | |
| regulator-name = "8226_s1_corner"; | |
| regulator-min-microvolt = <0x01>; | |
| compatible = "qcom,rpm-regulator-smd"; | |
| phandle = <0x1c>; | |
| linux,phandle = <0x1c>; | |
| }; | |
| regulator-s1-floor-corner { | |
| qcom,set = <0x03>; | |
| qcom,use-voltage-floor-corner; | |
| regulator-max-microvolt = <0x07>; | |
| regulator-name = "8226_s1_floor_corner"; | |
| regulator-min-microvolt = <0x01>; | |
| qcom,always-send-voltage; | |
| compatible = "qcom,rpm-regulator-smd"; | |
| phandle = <0x58>; | |
| linux,phandle = <0x58>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa3 { | |
| qcom,resource-id = <0x03>; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,resource-name = "ldoa"; | |
| status = "okay"; | |
| compatible = "qcom,rpm-regulator-smd-resource"; | |
| qcom,regulator-type = <0x00>; | |
| regulator-l3-so { | |
| qcom,set = <0x02>; | |
| regulator-max-microvolt = <0x14689c>; | |
| regulator-name = "8226_l3_so"; | |
| status = "okay"; | |
| regulator-min-microvolt = <0xb71b0>; | |
| qcom,init-voltage = <0xb71b0>; | |
| compatible = "qcom,rpm-regulator-smd"; | |
| }; | |
| regulator-3-ao { | |
| qcom,set = <0x01>; | |
| regulator-max-microvolt = <0x14689c>; | |
| regulator-name = "8226_l3_ao"; | |
| status = "okay"; | |
| regulator-min-microvolt = <0xb71b0>; | |
| compatible = "qcom,rpm-regulator-smd"; | |
| phandle = <0x5a>; | |
| linux,phandle = <0x5a>; | |
| }; | |
| regulator-l3 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x14689c>; | |
| regulator-name = "8226_l3"; | |
| status = "okay"; | |
| regulator-min-microvolt = <0xb71b0>; | |
| compatible = "qcom,rpm-regulator-smd"; | |
| phandle = <0x44>; | |
| linux,phandle = <0x44>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa4 { | |
| qcom,resource-id = <0x04>; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,resource-name = "ldoa"; | |
| status = "okay"; | |
| compatible = "qcom,rpm-regulator-smd-resource"; | |
| qcom,regulator-type = <0x00>; | |
| regulator-l4 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x124f80>; | |
| regulator-name = "8226_l4"; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x124f80>; | |
| qcom,init-voltage = <0x124f80>; | |
| compatible = "qcom,rpm-regulator-smd"; | |
| phandle = <0x05>; | |
| linux,phandle = <0x05>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa26 { | |
| qcom,resource-id = <0x1a>; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,resource-name = "ldoa"; | |
| status = "okay"; | |
| compatible = "qcom,rpm-regulator-smd-resource"; | |
| qcom,regulator-type = <0x00>; | |
| regulator-l26 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x12b128>; | |
| regulator-name = "8226_l26"; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x12b128>; | |
| qcom,init-voltage = <0x12b128>; | |
| compatible = "qcom,rpm-regulator-smd"; | |
| }; | |
| }; | |
| rpm-regulator-ldoa7 { | |
| qcom,resource-id = <0x07>; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,resource-name = "ldoa"; | |
| status = "okay"; | |
| compatible = "qcom,rpm-regulator-smd-resource"; | |
| qcom,regulator-type = <0x00>; | |
| regulator-l7 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x1c3a90>; | |
| regulator-name = "8226_l7"; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x1c3a90>; | |
| qcom,init-voltage = <0x1c3a90>; | |
| compatible = "qcom,rpm-regulator-smd"; | |
| }; | |
| }; | |
| rpm-regulator-ldoa21 { | |
| qcom,resource-id = <0x15>; | |
| qcom,hpm-min-load = <0x1388>; | |
| qcom,resource-name = "ldoa"; | |
| status = "okay"; | |
| compatible = "qcom,rpm-regulator-smd-resource"; | |
| qcom,regulator-type = <0x00>; | |
| regulator-l21 { | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x2d0370>; | |
| regulator-name = "8226_l21"; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x1b7740>; | |
| qcom,init-voltage = <0x2d0370>; | |
| compatible = "qcom,rpm-regulator-smd"; | |
| phandle = <0x29>; | |
| linux,phandle = <0x29>; | |
| }; | |
| }; | |
| }; | |
| qcom,smp2pgpio-ssr-smp2p-2-out { | |
| gpio-controller; | |
| #interrupt-cells = <0x02>; | |
| #gpio-cells = <0x02>; | |
| qcom,entry-name = "master-kernel"; | |
| compatible = "qcom,smp2pgpio"; | |
| interrupt-controller; | |
| qcom,remote-pid = <0x02>; | |
| phandle = <0x55>; | |
| linux,phandle = <0x55>; | |
| }; | |
| qcom,iommu@fda64000 { | |
| qcom,iommu-pmu-event-classes = <0x00 0x01 0x08 0x09 0x0a 0x10 0x11 0x12 0x80 0x81 0x82 0x83 0x90 0x91 0x92 0xb0 0xb1>; | |
| qcom,msm-bus,vectors-KBps = <0x3e 0x200 0x00 0x00 0x3e 0x200 0x00 0x3e8>; | |
| qcom,iommu-pmu-ngroups = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| vdd-supply = <0x07>; | |
| qcom,iommu-bfb-data = <0xffff 0x00 0x04 0x04 0x00 0x00 0x10 0x50 0x00 0x10 0x20 0x00 0x00 0x00 0x00>; | |
| qcom,needs-alt-core-clk; | |
| reg-names = "iommu_base"; | |
| interrupts = <0x00 0x43 0x00>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| ranges; | |
| status = "ok"; | |
| #address-cells = <0x01>; | |
| qcom,iommu-bfb-regs = <0x204c 0x2050 0x2514 0x2540 0x256c 0x2314 0x2394 0x2414 0x20ac 0x215c 0x220c 0x2008 0x200c 0x2010 0x2014>; | |
| #size-cells = <0x01>; | |
| label = "jpeg_iommu"; | |
| compatible = "qcom,msm-smmu-v1"; | |
| qcom,iommu-pmu-ncounters = <0x08>; | |
| reg = <0xfda64000 0x10000>; | |
| qcom,msm-bus,name = "jpeg_ebi"; | |
| qcom,iommu-enable-halt; | |
| qcom,iommu-ctx@fda6c000 { | |
| interrupts = <0x00 0x46 0x00>; | |
| qcom,iommu-ctx-sids = <0x00>; | |
| label = "jpeg_enc0"; | |
| compatible = "qcom,msm-smmu-v1-ctx"; | |
| reg = <0xfda6c000 0x1000>; | |
| }; | |
| qcom,iommu-ctx@fda6e000 { | |
| interrupts = <0x00 0x46 0x00>; | |
| qcom,iommu-ctx-sids = <0x02>; | |
| label = "jpeg_dec"; | |
| compatible = "qcom,msm-smmu-v1-ctx"; | |
| reg = <0xfda6e000 0x1000>; | |
| }; | |
| qcom,iommu-ctx@fda6d000 { | |
| interrupts = <0x00 0x46 0x00>; | |
| qcom,iommu-ctx-sids = <0x01>; | |
| label = "jpeg_enc1"; | |
| compatible = "qcom,msm-smmu-v1-ctx"; | |
| reg = <0xfda6d000 0x1000>; | |
| }; | |
| }; | |
| sound-9302 { | |
| qcom,cdc-mclk-gpios = <0x43 0x01 0x00>; | |
| qcom,prim-auxpcm-gpio-set = "prim-gpio-prim"; | |
| qcom,prim-auxpcm-gpio-clk = <0x08 0x3f 0x00>; | |
| qcom,prim-auxpcm-gpio-sync = <0x08 0x40 0x00>; | |
| qcom,model = "msm8226-tapan9302-snd-card"; | |
| qcom,tapan-codec-9302; | |
| qcom,audio-routing = "RX_BIAS\0MCLK\0LDO_H\0MCLK\0SPK_OUT\0MCLK\0SPK_OUT\0EXT_VDD_SPKR\0AMIC1\0MIC BIAS1 External\0MIC BIAS1 External\0Handset Mic\0AMIC2\0MIC BIAS2 External\0MIC BIAS2 External\0Headset Mic\0AMIC3\0MIC BIAS1 External\0MIC BIAS1 External\0ANCRight Headset Mic\0AMIC4\0MIC BIAS2 External\0MIC BIAS2 External\0ANCLeft Headset Mic"; | |
| compatible = "qcom,msm8226-audio-tapan"; | |
| qcom,cdc-vdd-spkr-gpios = <0x43 0x02 0x00>; | |
| qcom,tapan-mclk-clk-freq = <0x927c00>; | |
| qcom,prim-auxpcm-gpio-din = <0x08 0x41 0x00>; | |
| qcom,prim-auxpcm-gpio-dout = <0x08 0x42 0x00>; | |
| }; | |
| qcom,msm-cpufreq@0 { | |
| compatible = "qcom,msm-cpufreq"; | |
| reg = <0x00 0x04>; | |
| qcom,cpufreq-table = <0x493e0 0x5f5 0x5dc00 0x5f5 0x927c0 0x5f5 0xc0300 0xbeb 0xf3c00 0xfe2 0x10b300 0xfe2 0x122a00 0xfe2 0x13ec00 0xfe2 0x148200 0xfe2 0x156300 0xfe2 0x16da00 0xfe2 0x185100 0xfe2>; | |
| }; | |
| audio_etm0 { | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x0e>; | |
| coresight-child-list = <0x31>; | |
| coresight-outports = <0x00>; | |
| coresight-child-ports = <0x02>; | |
| compatible = "qcom,coresight-audio-etm"; | |
| coresight-name = "coresight-audio-etm0"; | |
| }; | |
| rpm_etm0 { | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x11>; | |
| coresight-child-list = <0x31>; | |
| coresight-outports = <0x00>; | |
| coresight-child-ports = <0x00>; | |
| compatible = "qcom,coresight-rpm-etm"; | |
| coresight-name = "coresight-rpm-etm0"; | |
| }; | |
| fuse@fc4be024 { | |
| reg-names = "fuse-base"; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x27>; | |
| compatible = "arm,coresight-fuse"; | |
| reg = <0xfc4be024 0x08>; | |
| coresight-name = "coresight-fuse"; | |
| }; | |
| qcom,msm-pcm-afe { | |
| compatible = "qcom,msm-pcm-afe"; | |
| }; | |
| msm-sys-noc@fc460000 { | |
| qcom,hw-sel = "NoC"; | |
| qcom,qos-freq = <0x12c0>; | |
| qcom,fabclk-dual = "bus_clk"; | |
| qcom,rpm-en; | |
| cell-id = <0x400>; | |
| qcom,ntieredslaves = <0x00>; | |
| qcom,fabclk-active = "bus_a_clk"; | |
| label = "msm_sys_noc"; | |
| compatible = "msm-bus-fabric"; | |
| reg = <0xfc460000 0x4000>; | |
| mas-lpass-proc { | |
| qcom,prio-rd = <0x02>; | |
| qcom,masterp = <0x06>; | |
| qcom,qport = <0x04>; | |
| qcom,mode = "Fixed"; | |
| qcom,mas-hw-id = <0x19>; | |
| cell-id = <0x0b>; | |
| qcom,prio-wr = <0x02>; | |
| label = "mas-lpass-proc"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-lpass { | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x02>; | |
| qcom,slv-hw-id = <0x15>; | |
| cell-id = <0x20a>; | |
| label = "slv-lpass"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-ocimem { | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x09>; | |
| qcom,slv-hw-id = <0x1a>; | |
| cell-id = <0x249>; | |
| label = "slv-ocimem"; | |
| qcom,tier = <0x02>; | |
| }; | |
| fab-bimc { | |
| qcom,masterp = <0x03>; | |
| qcom,gateway; | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x07>; | |
| qcom,slv-hw-id = <0x18>; | |
| qcom,mas-hw-id = <0x15>; | |
| cell-id = <0x00>; | |
| label = "fab-bimc"; | |
| }; | |
| mas-qdss-etr { | |
| qcom,masterp = <0x0c>; | |
| qcom,qport = <0x0a>; | |
| qcom,mode = "Fixed"; | |
| qcom,mas-hw-id = <0x1f>; | |
| cell-id = <0x3c>; | |
| label = "mas-qdss-etr"; | |
| qcom,tier = <0x02>; | |
| }; | |
| mas-crypto-core0 { | |
| qcom,prio-rd = <0x01>; | |
| qcom,hw-sel = "NoC"; | |
| qcom,masterp = <0x05>; | |
| qcom,mode = "Fixed"; | |
| qcom,mas-hw-id = <0x17>; | |
| cell-id = <0x37>; | |
| qcom,prio-wr = <0x01>; | |
| label = "mas-crypto-core0"; | |
| qcom,tier = <0x02>; | |
| }; | |
| fab-pnoc { | |
| qcom,prio-rd = <0x02>; | |
| qcom,masterp = <0x0a>; | |
| qcom,gateway; | |
| qcom,qport = <0x08>; | |
| qcom,buswidth = <0x08>; | |
| qcom,mode = "Fixed"; | |
| qcom,slavep = <0x0a>; | |
| qcom,slv-hw-id = <0x1c>; | |
| qcom,mas-hw-id = <0x1d>; | |
| cell-id = <0x1000>; | |
| qcom,prio-wr = <0x02>; | |
| label = "fab-pnoc"; | |
| }; | |
| mas-mss-nav { | |
| qcom,masterp = <0x08>; | |
| qcom,mas-hw-id = <0x1b>; | |
| cell-id = <0x39>; | |
| label = "mas-mss-nav"; | |
| qcom,tier = <0x02>; | |
| }; | |
| mas-wcss { | |
| qcom,masterp = <0x0b>; | |
| qcom,mas-hw-id = <0x1e>; | |
| cell-id = <0x3b>; | |
| label = "mas-wcss"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-wcss { | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x06>; | |
| qcom,slv-hw-id = <0x17>; | |
| cell-id = <0x248>; | |
| label = "slv-wcss"; | |
| qcom,tier = <0x02>; | |
| }; | |
| mas-lpass-ahb { | |
| qcom,prio-rd = <0x02>; | |
| qcom,masterp = <0x00>; | |
| qcom,qport = <0x00>; | |
| qcom,mode = "Fixed"; | |
| qcom,mas-hw-id = <0x12>; | |
| cell-id = <0x34>; | |
| qcom,prio-wr = <0x02>; | |
| label = "mas-lpass-ahb"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-ampss { | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x01>; | |
| qcom,slv-hw-id = <0x14>; | |
| cell-id = <0x208>; | |
| label = "slv-ampss"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-service-snoc { | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x0b>; | |
| qcom,slv-hw-id = <0x1d>; | |
| cell-id = <0x24b>; | |
| label = "slv-service-snoc"; | |
| qcom,tier = <0x02>; | |
| }; | |
| fab-cnoc { | |
| qcom,masterp = <0x04>; | |
| qcom,gateway; | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x08>; | |
| qcom,slv-hw-id = <0x19>; | |
| qcom,mas-hw-id = <0x16>; | |
| cell-id = <0x1400>; | |
| label = "fab-cnoc"; | |
| }; | |
| mas-mss { | |
| qcom,masterp = <0x07>; | |
| qcom,mas-hw-id = <0x1a>; | |
| cell-id = <0x26>; | |
| label = "mas-mss"; | |
| qcom,tier = <0x02>; | |
| }; | |
| fab-ovnoc { | |
| qcom,gateway; | |
| qcom,buswidth = <0x08>; | |
| qcom,slv-hw-id = <0x4d>; | |
| qcom,mas-hw-id = <0x35>; | |
| cell-id = <0x1800>; | |
| label = "fab-ovnoc"; | |
| }; | |
| slv-qdss-stm { | |
| qcom,buswidth = <0x08>; | |
| qcom,slavep = <0x0c>; | |
| qcom,slv-hw-id = <0x1e>; | |
| cell-id = <0x24c>; | |
| label = "slv-qdss-stm"; | |
| qcom,tier = <0x02>; | |
| }; | |
| mas-qdss-bam { | |
| qcom,masterp = <0x01>; | |
| qcom,qport = <0x01>; | |
| qcom,mode = "Fixed"; | |
| qcom,mas-hw-id = <0x13>; | |
| cell-id = <0x35>; | |
| label = "mas-qdss-bam"; | |
| qcom,tier = <0x02>; | |
| }; | |
| mas-ocmem-dma { | |
| qcom,masterp = <0x09>; | |
| qcom,qport = <0x07>; | |
| qcom,mode = "Fixed"; | |
| qcom,mas-hw-id = <0x1c>; | |
| cell-id = <0x3a>; | |
| label = "mas-ocmem-dma"; | |
| qcom,tier = <0x02>; | |
| }; | |
| mas-snoc-cfg { | |
| qcom,masterp = <0x02>; | |
| qcom,mas-hw-id = <0x14>; | |
| cell-id = <0x36>; | |
| label = "mas-snoc-cfg"; | |
| qcom,tier = <0x02>; | |
| }; | |
| }; | |
| funnel@fc364000 { | |
| reg-names = "funnel-base"; | |
| coresight-nr-inports = <0x08>; | |
| coresight-id = <0x08>; | |
| coresight-child-list = <0x2f>; | |
| coresight-outports = <0x00>; | |
| coresight-child-ports = <0x01>; | |
| compatible = "arm,coresight-funnel"; | |
| reg = <0xfc364000 0x1000>; | |
| coresight-name = "coresight-funnel-mmss"; | |
| }; | |
| mdm_sharedmem { | |
| reg-names = "rfsa_mdm"; | |
| compatible = "qcom,sharedmem-uio"; | |
| reg = <0xfd60000 0x20000>; | |
| }; | |
| qcom,iommu@fd928000 { | |
| qcom,iommu-pmu-event-classes = <0x00 0x01 0x08 0x09 0x0a 0x10 0x11 0x12 0x80 0x81 0x82 0x83 0x90 0x91 0x92 0xb0 0xb1>; | |
| qcom,iommu-secure-id = <0x01>; | |
| qcom,msm-bus,vectors-KBps = <0x16 0x200 0x00 0x00 0x16 0x200 0x00 0x3e8>; | |
| qcom,iommu-pmu-ngroups = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| vdd-supply = <0x0f>; | |
| qcom,iommu-bfb-data = <0xffffffff 0x00 0x04 0x10 0x00 0x00 0x13 0x17 0x00 0x13 0x23 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; | |
| reg-names = "iommu_base"; | |
| interrupts = <0x00 0x49 0x00>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| ranges; | |
| status = "ok"; | |
| #address-cells = <0x01>; | |
| qcom,iommu-bfb-regs = <0x204c 0x2050 0x2514 0x2540 0x256c 0x20ac 0x215c 0x220c 0x2314 0x2394 0x2414 0x2008 0x200c 0x2010 0x2014 0x2018 0x201c 0x2020>; | |
| #size-cells = <0x01>; | |
| label = "mdp_iommu"; | |
| compatible = "qcom,msm-smmu-v1"; | |
| qcom,iommu-pmu-ncounters = <0x08>; | |
| reg = <0xfd928000 0x10000>; | |
| qcom,msm-bus,name = "mdp_ebi"; | |
| qcom,iommu-enable-halt; | |
| qcom,iommu-ctx@fd930000 { | |
| interrupts = <0x00 0x2f 0x00>; | |
| qcom,iommu-ctx-sids = <0x00>; | |
| label = "mdp_0"; | |
| compatible = "qcom,msm-smmu-v1-ctx"; | |
| reg = <0xfd930000 0x1000>; | |
| }; | |
| qcom,iommu-ctx@fd932000 { | |
| interrupts = <0x00 0x2f 0x00 0x00 0x2e 0x00>; | |
| qcom,secure-context; | |
| qcom,iommu-ctx-sids; | |
| label = "mdp_2"; | |
| compatible = "qcom,msm-smmu-v1-ctx"; | |
| reg = <0xfd932000 0x1000>; | |
| }; | |
| qcom,iommu-ctx@fd931000 { | |
| interrupts = <0x00 0x2f 0x00 0x00 0x2e 0x00>; | |
| qcom,secure-context; | |
| qcom,iommu-ctx-sids = <0x01>; | |
| label = "mdp_1"; | |
| compatible = "qcom,msm-smmu-v1-ctx"; | |
| reg = <0xfd931000 0x1000>; | |
| }; | |
| }; | |
| funnel@fc319000 { | |
| reg-names = "funnel-base"; | |
| coresight-nr-inports = <0x08>; | |
| coresight-id = <0x05>; | |
| coresight-child-list = <0x2e>; | |
| coresight-outports = <0x00>; | |
| coresight-child-ports = <0x00>; | |
| compatible = "arm,coresight-funnel"; | |
| phandle = <0x31>; | |
| reg = <0xfc319000 0x1000>; | |
| linux,phandle = <0x31>; | |
| coresight-name = "coresight-funnel-in0"; | |
| }; | |
| i2c@f9925000 { | |
| qcom,sda-gpio = <0x08 0x0a 0x00>; | |
| qcom,i2c-bus-freq = <0x61a80>; | |
| qcom,scl-gpio = <0x08 0x0b 0x00>; | |
| reg-names = "qup_phys_addr"; | |
| interrupts = <0x00 0x61 0x00>; | |
| qcom,master-id = <0x56>; | |
| status = "ok"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| cell-index = <0x03>; | |
| qcom,i2c-src-freq = <0x124f800>; | |
| compatible = "qcom,i2c-qup"; | |
| reg = <0xf9925000 0x1000>; | |
| interrupt-names = "qup_err_intr"; | |
| tps65132@3e { | |
| gpios = <0x08 0x1f 0x00 0x08 0x21 0x00>; | |
| bias-delay-us = <0x7d0>; | |
| active-dis; | |
| compatible = "ti,tps65132"; | |
| reg = <0x3e>; | |
| regulator { | |
| regulator-max-microvolt = <0x5b8d80>; | |
| startup-delay-us = <0x2710>; | |
| regulator-name = "tps65132"; | |
| regulator-min-microvolt = "\0=\t"; | |
| regulator-boot-on; | |
| phandle = <0x24>; | |
| linux,phandle = <0x24>; | |
| }; | |
| }; | |
| tpa6165xx@40 { | |
| gpios = <0x08 0x04 0x00>; | |
| ti,tpa6165-jack-detect-config = <0xc0>; | |
| hs_det_micvdd-supply = <0x29>; | |
| interrupts = <0x04 0x02>; | |
| interrupt-parent = <0x08>; | |
| compatible = "ti,tpa6165"; | |
| hs_det_vdd-supply = <0x0b>; | |
| reg = <0x40>; | |
| }; | |
| tmp108@48 { | |
| gpios = <0x08 0x0d 0x00>; | |
| compatible = "ti,tmp108"; | |
| reg = <0x48>; | |
| }; | |
| }; | |
| etm@fc33f000 { | |
| reg-names = "etm-base"; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x0d>; | |
| coresight-child-list = <0x30>; | |
| coresight-outports = <0x00>; | |
| coresight-child-ports = <0x03>; | |
| qcom,round-robin; | |
| compatible = "arm,coresight-etm"; | |
| reg = <0xfc33f000 0x1000>; | |
| coresight-name = "coresight-etm3"; | |
| }; | |
| qcom,sdcc@f98a4000 { | |
| qcom,bus-width = <0x04>; | |
| qcom,msm-bus,vectors-KBps = <0x51 0x200 0x00 0x00 0x51 0x200 0x640 0xc80 0x51 0x200 0x13880 0x27100 0x51 0x200 0x186a0 0x30d40 0x51 0x200 0x30d40 0x61a80 0x51 0x200 0x61a80 0xc3500 0x51 0x200 0x61a80 0xc3500 0x51 0x200 0x1f4000 0x3e8000>; | |
| qcom,msm-bus,num-cases = <0x08>; | |
| reg-names = "core_mem\0dml_mem\0bam_mem"; | |
| interrupts = <0x00 0x7d 0x00 0x00 0xdc 0x00>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,bus-bw-vectors-bps = <0x00 0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100 0xbebc200 0xffffffff>; | |
| status = "disabled"; | |
| cell-index = <0x02>; | |
| compatible = "qcom,msm-sdcc"; | |
| reg = <0xf98a4000 0x800 0xf98a4800 0x100 0xf9884000 0x7000>; | |
| qcom,msm-bus,name = "sdcc2"; | |
| interrupt-names = "core_irq\0bam_irq"; | |
| }; | |
| hsic@f9a00000 { | |
| hsic_vdd_dig-supply = <0x1c>; | |
| qcom,phy-susp-sof-workaround; | |
| qcom,msm-bus,vectors-KBps = <0x55 0x200 0x00 0x00 0x55 0x200 0x9c40 0x27100>; | |
| hsic,data-gpio = <0x08 0x74 0x00>; | |
| HSIC_GDSC-supply = <0x3f>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| #interrupt-cells = <0x01>; | |
| interrupts = <0x00 0x01 0x02>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| interrupt-map = <0x00 0x01 0x00 0x88 0x00 0x01 0x01 0x00 0x94 0x00 0x02 0x08 0x73 0x08>; | |
| interrupt-parent = <0x3e>; | |
| status = "disabled"; | |
| #address-cells = <0x00>; | |
| hsic,strobe-gpio = <0x08 0x73 0x00>; | |
| hsic,ignore-cal-pad-config; | |
| hsic,vdd-voltage-level = <0x01 0x05 0x07>; | |
| interrupt-map-mask = <0xffffffff>; | |
| compatible = "qcom,hsic-host"; | |
| hsic,data-pad-offset = <0x2054>; | |
| phandle = <0x3e>; | |
| reg = <0xf9a00000 0x400>; | |
| qcom,msm-bus,name = "hsic"; | |
| interrupt-names = "core_irq\0async_irq\0wakeup"; | |
| linux,phandle = <0x3e>; | |
| hsic,strobe-pad-offset = <0x2050>; | |
| }; | |
| qcom,smem@fa00000 { | |
| reg-names = "smem\0irq-reg-base\0aux-mem1"; | |
| compatible = "qcom,smem"; | |
| reg = <0xfa00000 0x100000 0xf9011000 0x1000 0xfc428000 0x4000>; | |
| qcom,smsm-wcnss { | |
| interrupts = <0x00 0x90 0x01>; | |
| qcom,smsm-edge = <0x06>; | |
| compatible = "qcom,smsm"; | |
| qcom,smsm-irq-offset = <0x08>; | |
| qcom,smsm-irq-bitmask = <0x80000>; | |
| }; | |
| qcom,smsm-adsp { | |
| interrupts = <0x00 0x9d 0x01>; | |
| qcom,smsm-edge = <0x01>; | |
| compatible = "qcom,smsm"; | |
| qcom,smsm-irq-offset = <0x08>; | |
| qcom,smsm-irq-bitmask = <0x200>; | |
| }; | |
| qcom,smsm-modem { | |
| interrupts = <0x00 0x1a 0x01>; | |
| qcom,smsm-edge = <0x00>; | |
| compatible = "qcom,smsm"; | |
| qcom,smsm-irq-offset = <0x08>; | |
| qcom,smsm-irq-bitmask = <0x2000>; | |
| }; | |
| qcom,smd-wcnss { | |
| qcom,smd-irq-offset = <0x08>; | |
| interrupts = <0x00 0x8e 0x01>; | |
| qcom,pil-string = "wcnss"; | |
| qcom,smd-irq-bitmask = <0x20000>; | |
| compatible = "qcom,smd"; | |
| qcom,smd-edge = <0x06>; | |
| }; | |
| qcom,smd-adsp { | |
| qcom,smd-irq-offset = <0x08>; | |
| interrupts = <0x00 0x9c 0x01>; | |
| qcom,pil-string = "adsp"; | |
| qcom,smd-irq-bitmask = <0x100>; | |
| compatible = "qcom,smd"; | |
| qcom,smd-edge = <0x01>; | |
| }; | |
| qcom,smd-rpm { | |
| qcom,smd-irq-offset = <0x08>; | |
| interrupts = <0x00 0xa8 0x01>; | |
| qcom,smd-irq-bitmask = <0x01>; | |
| qcom,irq-no-suspend; | |
| compatible = "qcom,smd"; | |
| qcom,smd-edge = <0x0f>; | |
| }; | |
| qcom,smd-modem { | |
| qcom,smd-irq-offset = <0x08>; | |
| interrupts = <0x00 0x19 0x01>; | |
| qcom,pil-string = "modem"; | |
| qcom,smd-irq-bitmask = <0x1000>; | |
| compatible = "qcom,smd"; | |
| qcom,smd-edge = <0x00>; | |
| }; | |
| }; | |
| qcom,ipc-spinlock@fd484000 { | |
| compatible = "qcom,ipc-spinlock-sfpb"; | |
| qcom,num-locks = <0x08>; | |
| reg = <0xfd484000 0x400>; | |
| }; | |
| jtagmm@fc33e000 { | |
| reg-names = "etm-base\0debug-base"; | |
| compatible = "qcom,jtag-mm"; | |
| reg = <0xfc33e000 0x1000 0xfc334000 0x1000>; | |
| }; | |
| qcom,smp2pgpio_test_smp2p_4_in { | |
| gpios = <0x19 0x00 0x00>; | |
| compatible = "qcom,smp2pgpio_test_smp2p_4_in"; | |
| }; | |
| qcom,sps@f9984000 { | |
| interrupts = <0x00 0x5e 0x00>; | |
| compatible = "qcom,msm_sps"; | |
| reg = <0xf9984000 0x15000 0xf9999000 0xb000>; | |
| }; | |
| qcom,clock-a7@f9011050 { | |
| qcom,speed5-bin-v2 = <0x00 0x00 0x16e36000 0x02 0x2eebb800 0x04 0x538ab800 0x0a>; | |
| qcom,speed4-bin-v2 = <0x00 0x00 0x16e36000 0x02 0x2eebb800 0x04 0x538ab800 0x0a>; | |
| qcom,speed6-bin-v2 = <0x00 0x00 0x16e36000 0x02 0x2eebb800 0x04 0x46f41000 0x07>; | |
| qcom,speed1-bin-v2 = <0x00 0x00 0x16e36000 0x02 0x2eebb800 0x04 0x3b826000 0x05 0x413b3800 0x06 0x46f41000 0x07 0x4dd1e000 0x08 0x501bd000 0x09 0x538ab800 0x0a 0x59439000 0x0b 0x5efc6800 0x0c>; | |
| qcom,speed7-bin-v2 = <0x00 0x00 0x16e36000 0x02 0x2eebb800 0x04 0x538ab800 0x0a>; | |
| reg-names = "rcg-base\0efuse"; | |
| compatible = "qcom,clock-a7-8226"; | |
| qcom,speed0-bin-v0 = <0x00 0x00 0x16e36000 0x02 0x2eebb800 0x04 0x46f41000 0x07>; | |
| clock-names = "clk-4\0clk-5"; | |
| qcom,speed2-bin-v2 = <0x00 0x00 0x16e36000 0x02 0x2eebb800 0x04 0x538ab800 0x0a>; | |
| reg = <0xf9011050 0x08 0xfc4b80b0 0x08>; | |
| cpu-vdd-supply = <0x51>; | |
| qcom,speed0-bin-v2 = <0x00 0x00 0x16e36000 0x02 0x2eebb800 0x04 0x46f41000 0x07>; | |
| }; | |
| qcom,bam_dmux@fc834000 { | |
| interrupts = <0x00 0x1d 0x01>; | |
| compatible = "qcom,bam_dmux"; | |
| reg = <0xfc834000 0x7000>; | |
| }; | |
| qcom,gdsc@fd8c35a4 { | |
| regulator-name = "gdsc_jpeg"; | |
| status = "ok"; | |
| compatible = "qcom,gdsc"; | |
| phandle = <0x07>; | |
| qcom,clock-names = "core_clk"; | |
| reg = <0xfd8c35a4 0x04>; | |
| linux,phandle = <0x07>; | |
| }; | |
| qcom,qcrypto@fd404000 { | |
| qcom,msm-bus,vectors-KBps = <0x37 0x200 0x00 0x00 0x37 0x200 0x3c0f00 0x60180>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| reg-names = "crypto-base\0crypto-bam-base"; | |
| interrupts = <0x00 0xcf 0x00>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,bam-pipe-pair = <0x02>; | |
| qcom,ce-hw-shared; | |
| compatible = "qcom,qcrypto"; | |
| qcom,ce-hw-instance = <0x00>; | |
| qcom,msm-bus,active-only = <0x00>; | |
| reg = <0xfd400000 0x20000 0xfd404000 0x8000>; | |
| qcom,msm-bus,name = "qcrypto-noc"; | |
| }; | |
| qcom,iommu@fdb10000 { | |
| qcom,iommu-pmu-event-classes = <0x00 0x01 0x08 0x09 0x0a 0x10 0x11 0x12 0x80 0x81 0x82 0x83 0x90 0x91 0x92 0xb0 0xb1>; | |
| qcom,msm-bus,vectors-KBps = <0x1a 0x200 0x00 0x00 0x1a 0x200 0x00 0x3e8>; | |
| qcom,iommu-pmu-ngroups = <0x01>; | |
| qcom,alt-vdd-supply = <0x12>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| vdd-supply = <0x11>; | |
| qcom,iommu-bfb-data = <0x03 0x00 0x04 0x10 0x00 0x00 0x01 0x11 0x00 0x01 0x41 0x00>; | |
| qcom,needs-alt-core-clk; | |
| reg-names = "iommu_base"; | |
| interrupts = <0x00 0x26 0x00>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| ranges; | |
| status = "ok"; | |
| #address-cells = <0x01>; | |
| qcom,iommu-bfb-regs = <0x204c 0x2050 0x2514 0x2540 0x256c 0x20ac 0x215c 0x220c 0x2314 0x2394 0x2414 0x2008>; | |
| #size-cells = <0x01>; | |
| label = "kgsl_iommu"; | |
| compatible = "qcom,msm-smmu-v1"; | |
| qcom,iommu-pmu-ncounters = <0x08>; | |
| phandle = <0x1b>; | |
| reg = <0xfdb10000 0x10000>; | |
| qcom,msm-bus,name = "kgsl_ebi"; | |
| qcom,iommu-enable-halt; | |
| linux,phandle = <0x1b>; | |
| qcom,iommu-ctx@fdb18000 { | |
| interrupts = <0x00 0xf1 0x00>; | |
| qcom,iommu-ctx-sids = <0x00>; | |
| label = "gfx3d_user"; | |
| compatible = "qcom,msm-smmu-v1-ctx"; | |
| reg = <0xfdb18000 0x1000>; | |
| }; | |
| qcom,iommu-ctx@fdb1a000 { | |
| interrupts = <0x00 0xf1 0x00>; | |
| qcom,iommu-ctx-sids = <0x02>; | |
| label = "gfx3d_spare"; | |
| compatible = "qcom,msm-smmu-v1-ctx"; | |
| reg = <0xfdb1a000 0x1000>; | |
| }; | |
| qcom,iommu-ctx@fdb19000 { | |
| interrupts = <0x00 0xf1 0x00>; | |
| qcom,iommu-ctx-sids = <0x01>; | |
| label = "gfx3d_priv"; | |
| compatible = "qcom,msm-smmu-v1-ctx"; | |
| reg = <0xfdb19000 0x1000>; | |
| }; | |
| }; | |
| cti@fc340000 { | |
| reg-names = "cti-base"; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x1c>; | |
| compatible = "arm,coresight-cti"; | |
| reg = <0xfc340000 0x1000>; | |
| coresight-name = "coresight-cti-l2"; | |
| }; | |
| qcom,smp2pgpio-rdbg-2-out { | |
| gpio-controller; | |
| #interrupt-cells = <0x02>; | |
| #gpio-cells = <0x02>; | |
| qcom,entry-name = "rdbg"; | |
| compatible = "qcom,smp2pgpio"; | |
| interrupt-controller; | |
| qcom,remote-pid = <0x02>; | |
| phandle = <0x35>; | |
| linux,phandle = <0x35>; | |
| }; | |
| qcom,venus@fdce0000 { | |
| vdd-supply = <0x10>; | |
| reg-names = "wrapper_base\0vbif_base"; | |
| compatible = "qcom,pil-venus"; | |
| reg = <0xfdce0000 0x4000 0xfdc80000 0x400>; | |
| qcom,firmware-name = "venus"; | |
| }; | |
| usr_reset_warning { | |
| gpios = <0x08 0x45 0x00>; | |
| compatible = "mmi,usr-reset-warning"; | |
| }; | |
| qcom,smp2pgpio-smp2p-2-out { | |
| gpio-controller; | |
| #interrupt-cells = <0x02>; | |
| #gpio-cells = <0x02>; | |
| qcom,entry-name = "smp2p"; | |
| compatible = "qcom,smp2pgpio"; | |
| interrupt-controller; | |
| qcom,remote-pid = <0x02>; | |
| phandle = <0x18>; | |
| linux,phandle = <0x18>; | |
| }; | |
| qcom,qseecom@d980000 { | |
| qcom,msm-bus,vectors-KBps = <0x37 0x200 0x00 0x00 0x37 0x200 0x3c0f00 0x60180 0x37 0x200 0x3c0f00 0x60180 0x37 0x200 0x3c0f00 0x60180>; | |
| qcom,msm-bus,num-cases = <0x04>; | |
| reg-names = "secapp-region"; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,disk-encrypt-pipe-pair = <0x02>; | |
| compatible = "qcom,qseecom"; | |
| qcom,msm-bus,active-only = <0x00>; | |
| qcom,qsee-ce-hw-instance = <0x00>; | |
| reg = <0xd980000 0x256000>; | |
| qcom,msm-bus,name = "qseecom-noc"; | |
| qcom,hlos-ce-hw-instance = <0x00>; | |
| }; | |
| i2c@f9924000 { | |
| qcom,i2c-bus-freq = <0x186a0>; | |
| reg-names = "qup_phys_addr"; | |
| interrupts = <0x00 0x60 0x00>; | |
| status = "ok"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| cell-index = <0x02>; | |
| compatible = "qcom,i2c-qup"; | |
| reg = <0xf9924000 0x1000>; | |
| interrupt-names = "qup_err_intr"; | |
| ct406@39 { | |
| ams,prox-covered-offset = <0x96>; | |
| gpios = <0x08 0x41 0x00>; | |
| ams,prox-pulse-count = <0x04>; | |
| vdd-supply = <0x0d>; | |
| interrupts = <0x41 0x02>; | |
| interrupt-parent = <0x08>; | |
| ams,ink_type = <0x01>; | |
| ams,prox-offset = <0x00>; | |
| compatible = "ams,ct406"; | |
| ams,prox-recalibrate-offset = <0x46>; | |
| reg = <0x39>; | |
| ams,prox-samples-for-noise-floor = <0x05>; | |
| ams,prox-uncovered-offset = <0x6e>; | |
| }; | |
| lis3dh@19 { | |
| stm,duration = <0x01>; | |
| stm,threshold = <0x20>; | |
| gpios = <0x08 0x3f 0x00>; | |
| stm,poll-interval = <0xc8>; | |
| stm,min-interval = <0x01>; | |
| vdd-supply = <0x0d>; | |
| compatible = "stm,lis3dh"; | |
| stm,g-range = <0x08>; | |
| reg = <0x19>; | |
| }; | |
| ak8963@0c { | |
| akm,layout = <0x06>; | |
| akm,gpio-rst = <0x08 0x3e 0x00>; | |
| vdd-supply = <0x0d>; | |
| interrupts = <0x42 0x02>; | |
| interrupt-parent = <0x08>; | |
| akm,outbit = <0x01>; | |
| compatible = "akm,akm8963"; | |
| reg = <0x0c>; | |
| akm,gpio-irq = <0x08 0x42 0x00>; | |
| }; | |
| }; | |
| qcom,smp2pgpio_test_smp2p_2_in { | |
| gpios = <0x17 0x00 0x00>; | |
| compatible = "qcom,smp2pgpio_test_smp2p_2_in"; | |
| }; | |
| msm-mmss-noc@fc478000 { | |
| qcom,hw-sel = "NoC"; | |
| qcom,qos-freq = <0x12c0>; | |
| qcom,fabclk-dual = "bus_clk"; | |
| qcom,rpm-en; | |
| cell-id = <0x800>; | |
| qcom,ntieredslaves = <0x00>; | |
| qcom,fabclk-active = "bus_a_clk"; | |
| label = "msm_mmss_noc"; | |
| compatible = "msm-bus-fabric"; | |
| reg = <0xfc478000 0x4000>; | |
| mas-jpeg { | |
| qcom,hw-sel = "NoC"; | |
| qcom,masterp = <0x04>; | |
| qcom,qport = <0x00>; | |
| qcom,mode = "Bypass"; | |
| qcom,ws = <0x2710>; | |
| qcom,perm-mode = "Bypass"; | |
| qcom,mas-hw-id = <0x07>; | |
| cell-id = <0x3e>; | |
| label = "mas-jpeg"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-venus-cfg { | |
| qcom,hw-sel = "NoC"; | |
| qcom,buswidth = <0x10>; | |
| qcom,slavep = <0x08>; | |
| qcom,slv-hw-id = <0x0a>; | |
| cell-id = <0x254>; | |
| label = "slv-venus-cfg"; | |
| qcom,tier = <0x02>; | |
| }; | |
| mas-video-p0 { | |
| qcom,hw-sel = "NoC"; | |
| qcom,masterp = <0x06>; | |
| qcom,qport = <0x04>; | |
| qcom,mode = "Bypass"; | |
| qcom,ws = <0x2710>; | |
| qcom,perm-mode = "Bypass"; | |
| qcom,mas-hw-id = <0x09>; | |
| cell-id = <0x3f>; | |
| label = "mas-video-p0"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-mmss-clk-xpu-cfg { | |
| qcom,hw-sel = "NoC"; | |
| qcom,buswidth = <0x10>; | |
| qcom,slavep = <0x0c>; | |
| qcom,slv-hw-id = <0x0d>; | |
| cell-id = <0x258>; | |
| label = "slv-mmss-clk-xpu-cfg"; | |
| qcom,tier = <0x02>; | |
| }; | |
| mas-mdp-port0 { | |
| qcom,hw-sel = "NoC"; | |
| qcom,masterp = <0x05>; | |
| qcom,qport = <0x01>; | |
| qcom,mode = "Bypass"; | |
| qcom,ws = <0x2710>; | |
| qcom,perm-mode = "Bypass"; | |
| qcom,mas-hw-id = <0x08>; | |
| cell-id = <0x16>; | |
| label = "mas-mdp-port0"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-gfx3d-cfg { | |
| qcom,hw-sel = "NoC"; | |
| qcom,buswidth = <0x10>; | |
| qcom,slavep = <0x09>; | |
| qcom,slv-hw-id = <0x0b>; | |
| cell-id = <0x256>; | |
| label = "slv-gfx3d-cfg"; | |
| qcom,tier = <0x02>; | |
| }; | |
| fab-bimc { | |
| qcom,hw-sel = "NoC"; | |
| qcom,gateway; | |
| qcom,buswidth = <0x10>; | |
| qcom,slavep = <0x10>; | |
| qcom,slv-hw-id = <0x10>; | |
| cell-id = <0x00>; | |
| label = "fab-bimc"; | |
| }; | |
| slv-mnoc-mpu-cfg { | |
| qcom,hw-sel = "NoC"; | |
| qcom,buswidth = <0x10>; | |
| qcom,slavep = <0x0d>; | |
| qcom,slv-hw-id = <0x0e>; | |
| cell-id = <0x259>; | |
| label = "slv-mnoc-mpu-cfg"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-cpr-xpu-cfg { | |
| qcom,hw-sel = "NoC"; | |
| qcom,buswidth = <0x10>; | |
| qcom,slavep = <0x04>; | |
| qcom,slv-hw-id = <0x07>; | |
| cell-id = <0x251>; | |
| label = "slv-cpr-xpu-cfg"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-mmss-clk-cfg { | |
| qcom,hw-sel = "NoC"; | |
| qcom,buswidth = <0x10>; | |
| qcom,slavep = <0x0b>; | |
| qcom,slv-hw-id = <0x0c>; | |
| cell-id = <0x257>; | |
| label = "slv-mmss-clk-cfg"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-service-mnoc { | |
| qcom,hw-sel = "NoC"; | |
| qcom,buswidth = <0x10>; | |
| qcom,slavep = <0x12>; | |
| qcom,slv-hw-id = <0x11>; | |
| cell-id = <0x25b>; | |
| label = "slv-service-mnoc"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-camera-cfg { | |
| qcom,hw-sel = "NoC"; | |
| qcom,buswidth = <0x10>; | |
| qcom,slavep = <0x00>; | |
| qcom,slv-hw-id = <0x03>; | |
| cell-id = <0x24d>; | |
| label = "slv-camera-cfg"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-ocmem-cfg { | |
| qcom,hw-sel = "NoC"; | |
| qcom,buswidth = <0x10>; | |
| qcom,slavep = <0x02>; | |
| qcom,slv-hw-id = <0x05>; | |
| cell-id = <0x24f>; | |
| label = "slv-ocmem-cfg"; | |
| qcom,tier = <0x02>; | |
| }; | |
| mas-vfe { | |
| qcom,hw-sel = "NoC"; | |
| qcom,masterp = <0x07>; | |
| qcom,qport = <0x06>; | |
| qcom,mode = "Bypass"; | |
| qcom,ws = <0x2710>; | |
| qcom,perm-mode = "Bypass"; | |
| qcom,mas-hw-id = <0x0b>; | |
| cell-id = <0x1d>; | |
| label = "mas-vfe"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-cpr-cfg { | |
| qcom,hw-sel = "NoC"; | |
| qcom,buswidth = <0x10>; | |
| qcom,slavep = <0x03>; | |
| qcom,slv-hw-id = <0x06>; | |
| cell-id = <0x250>; | |
| label = "slv-cpr-cfg"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-display-cfg { | |
| qcom,hw-sel = "NoC"; | |
| qcom,buswidth = <0x10>; | |
| qcom,slavep = <0x01>; | |
| qcom,slv-hw-id = <0x04>; | |
| cell-id = <0x24e>; | |
| label = "slv-display-cfg"; | |
| qcom,tier = <0x02>; | |
| }; | |
| fab-cnoc { | |
| qcom,hw-sel = "RPM"; | |
| qcom,masterp = <0x00 0x01>; | |
| qcom,gateway; | |
| qcom,buswidth = <0x10>; | |
| qcom,mas-hw-id = <0x04>; | |
| cell-id = <0x1400>; | |
| label = "fab-cnoc"; | |
| }; | |
| slv-misc-xpu-cfg { | |
| qcom,hw-sel = "NoC"; | |
| qcom,buswidth = <0x10>; | |
| qcom,slavep = <0x07>; | |
| qcom,slv-hw-id = <0x09>; | |
| cell-id = <0x253>; | |
| label = "slv-misc-xpu-cfg"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-misc-cfg { | |
| qcom,hw-sel = "NoC"; | |
| qcom,buswidth = <0x10>; | |
| qcom,slavep = <0x06>; | |
| qcom,slv-hw-id = <0x08>; | |
| cell-id = <0x252>; | |
| label = "slv-misc-cfg"; | |
| qcom,tier = <0x02>; | |
| }; | |
| slv-onoc-mpu-cfg { | |
| qcom,hw-sel = "NoC"; | |
| qcom,buswidth = <0x10>; | |
| qcom,slavep = <0x0e>; | |
| qcom,slv-hw-id = <0x0f>; | |
| cell-id = <0x25a>; | |
| label = "slv-onoc-mpu-cfg"; | |
| qcom,tier = <0x02>; | |
| }; | |
| mas-gfx3d { | |
| qcom,hw-sel = "NoC"; | |
| qcom,masterp = <0x02>; | |
| qcom,qport = <0x02>; | |
| qcom,mode = "Bypass"; | |
| qcom,ws = <0x2710>; | |
| qcom,perm-mode = "Bypass"; | |
| qcom,mas-hw-id = <0x06>; | |
| cell-id = <0x1a>; | |
| label = "mas-gfx3d"; | |
| qcom,tier = <0x02>; | |
| }; | |
| }; | |
| qcom,pm-8x60@fe805664 { | |
| qcom,synced-clocks; | |
| qcom,pc-resets-timer; | |
| qcom,cpus-as-clocks; | |
| qcom,lpm-levels = <0x5b>; | |
| qcom,use-sync-timer; | |
| compatible = "qcom,pm-8x60"; | |
| reg = <0xfe805664 0x40>; | |
| qcom,pc-mode = "tz_l2_int"; | |
| }; | |
| cti@fc310000 { | |
| reg-names = "cti-base"; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x1b>; | |
| compatible = "arm,coresight-cti"; | |
| phandle = <0x27>; | |
| reg = <0xfc310000 0x1000>; | |
| linux,phandle = <0x27>; | |
| coresight-name = "coresight-cti8"; | |
| }; | |
| qcom,msm-rtb { | |
| qcom,memory-reservation-size = <0x100000>; | |
| qcom,memory-reservation-type = "EBI1"; | |
| compatible = "qcom,msm-rtb"; | |
| }; | |
| qcom,smp2pgpio-smp2p-7-in { | |
| gpio-controller; | |
| #interrupt-cells = <0x02>; | |
| qcom,is-inbound; | |
| #gpio-cells = <0x02>; | |
| qcom,entry-name = "smp2p"; | |
| compatible = "qcom,smp2pgpio"; | |
| interrupt-controller; | |
| qcom,remote-pid = <0x07>; | |
| phandle = <0x13>; | |
| linux,phandle = <0x13>; | |
| }; | |
| qcom,smp2pgpio_test_smp2p_1_in { | |
| gpios = <0x15 0x00 0x00>; | |
| compatible = "qcom,smp2pgpio_test_smp2p_1_in"; | |
| }; | |
| qcom,csid@fda08000 { | |
| qcom,csi-vdd-voltage = <0x124f80>; | |
| reg-names = "csid"; | |
| interrupts = <0x00 0x33 0x00>; | |
| qcom,mipi-csi-vdd-supply = <0x05>; | |
| cell-index = <0x00>; | |
| compatible = "qcom,csid"; | |
| reg = <0xfda08000 0x100>; | |
| interrupt-names = "csid"; | |
| }; | |
| interrupt-controller@f9000000 { | |
| #interrupt-cells = <0x03>; | |
| compatible = "qcom,msm-qgic2"; | |
| interrupt-controller; | |
| phandle = <0x01>; | |
| reg = <0xf9000000 0x1000 0xf9002000 0x1000>; | |
| linux,phandle = <0x01>; | |
| }; | |
| cti@fc348000 { | |
| reg-names = "cti-base"; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x21>; | |
| compatible = "arm,coresight-cti"; | |
| reg = <0xfc348000 0x1000>; | |
| coresight-name = "coresight-cti-video-cpu0"; | |
| }; | |
| i2c@f9927000 { | |
| qcom,sda-gpio = <0x08 0x12 0x00>; | |
| qcom,i2c-bus-freq = <0x5dc00>; | |
| qcom,scl-gpio = <0x08 0x13 0x00>; | |
| reg-names = "qup_phys_addr"; | |
| interrupts = <0x00 0x63 0x00>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| cell-index = <0x05>; | |
| qcom,i2c-src-freq = <0x124f800>; | |
| compatible = "qcom,i2c-qup"; | |
| reg = <0xf9927000 0x1000>; | |
| interrupt-names = "qup_err_intr"; | |
| cyttsp3_i2c@3b { | |
| vdd-supply = <0x0d>; | |
| interrupts = <0x11 0x00>; | |
| vcc_i2c-supply = <0x50>; | |
| interrupt-parent = <0x08>; | |
| status = "disabled"; | |
| compatible = "cyttsp3,i2c"; | |
| reg = <0x3b>; | |
| }; | |
| synaptics_dsx_i2c@20 { | |
| gpios = <0x08 0x11 0x00 0x08 0x10 0x00>; | |
| touch_vdd-supply = <0x22>; | |
| interrupts = <0x11 0x00>; | |
| interrupt-parent = <0x08>; | |
| synaptics,normal-mode = <0x01>; | |
| compatible = "synaptics,synaptics_dsx_i2c"; | |
| reg = <0x20>; | |
| synaptics,gpio-config; | |
| }; | |
| aps_ts@34 { | |
| aps_ts,high-speed-isp; | |
| gpios = <0x08 0x11 0x00 0x08 0x10 0x00>; | |
| interrupts = <0x11 0x00>; | |
| interrupt-parent = <0x08>; | |
| compatible = "melfas-aps,aps_ts"; | |
| aps_ts,default-product-id = "Falc"; | |
| reg = <0x34>; | |
| }; | |
| }; | |
| qcom,gdsc@fc401ac4 { | |
| regulator-name = "gdsc_pcie_0"; | |
| status = "disabled"; | |
| compatible = "qcom,gdsc"; | |
| reg = <0xfc401ac4 0x04>; | |
| }; | |
| qcom,wfd { | |
| compatible = "qcom,msm-wfd"; | |
| }; | |
| qti,msm-pcm { | |
| compatible = "qti,msm-pcm-dsp"; | |
| qti,msm-pcm-dsp-id = <0x00>; | |
| }; | |
| cti@fc30e000 { | |
| reg-names = "cti-base"; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x19>; | |
| compatible = "arm,coresight-cti"; | |
| reg = <0xfc30e000 0x1000>; | |
| coresight-name = "coresight-cti6"; | |
| }; | |
| qcom,spm@f90a9000 { | |
| qcom,core-id = <0x02>; | |
| qcom,saw2-cfg = <0x00>; | |
| qcom,saw2-spm-ctl = <0x08>; | |
| qcom,saw2-spm-cmd-wfi = [60 03 60 0b 0f]; | |
| qcom,saw2-spm-dly = <0x3c102800>; | |
| qcom,saw2-spm-cmd-spc = <0x20108030 0x905b6003 0x603b7676 0xb945b80 0x1026300f>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| compatible = "qcom,spm-v2"; | |
| qcom,saw2-spm-cmd-pc = <0x20108030 0x905b6003 0x603b7676 0xb945b80 0x1026300f>; | |
| reg = <0xf90a9000 0x1000>; | |
| qcom,saw2-ver-reg = <0xfd0>; | |
| }; | |
| qcom,msm-imem@fe805000 { | |
| compatible = "qcom,msm-imem"; | |
| reg = <0xfe805000 0x1000>; | |
| }; | |
| qcom,jpeg@fda1c000 { | |
| vdd-supply = <0x07>; | |
| reg-names = "jpeg"; | |
| interrupts = <0x00 0x3b 0x00>; | |
| cell-index = <0x00>; | |
| compatible = "qcom,jpeg"; | |
| reg = <0xfda1c000 0x400>; | |
| interrupt-names = "jpeg"; | |
| }; | |
| qcom,smp2pgpio-ssr-smp2p-4-out { | |
| gpio-controller; | |
| #interrupt-cells = <0x02>; | |
| #gpio-cells = <0x02>; | |
| qcom,entry-name = "master-kernel"; | |
| compatible = "qcom,smp2pgpio"; | |
| interrupt-controller; | |
| qcom,remote-pid = <0x04>; | |
| phandle = <0x53>; | |
| linux,phandle = <0x53>; | |
| }; | |
| qcom,smp2p-wcnss { | |
| qcom,irq-bitmask = <0x40000>; | |
| interrupts = <0x00 0x8f 0x01>; | |
| compatible = "qcom,smp2p"; | |
| qcom,remote-pid = <0x04>; | |
| reg = <0xf9011008 0x04>; | |
| }; | |
| qcom,pm-boot { | |
| qcom,mode = "tz"; | |
| compatible = "qcom,pm-boot"; | |
| }; | |
| qcom,gdsc@fd8c1024 { | |
| regulator-name = "gdsc_venus"; | |
| status = "ok"; | |
| compatible = "qcom,gdsc"; | |
| phandle = <0x10>; | |
| qcom,clock-names = "core_clk"; | |
| reg = <0xfd8c1024 0x04>; | |
| linux,phandle = <0x10>; | |
| }; | |
| }; | |
| memory { | |
| device_type = "memory"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| reg = <0x00 0x20000000 0x20000000 0x20000000>; | |
| secure_region { | |
| linux,contiguous-region; | |
| label = "secure_mem"; | |
| phandle = <0x02>; | |
| reg = <0x00 0x4600000>; | |
| linux,phandle = <0x02>; | |
| }; | |
| qsecom_region { | |
| linux,contiguous-region; | |
| label = "qsecom_mem"; | |
| phandle = <0x04>; | |
| reg = <0x00 0x400000>; | |
| linux,phandle = <0x04>; | |
| }; | |
| adsp_region { | |
| linux,contiguous-region; | |
| label = "adsp_mem"; | |
| phandle = <0x03>; | |
| reg = <0x00 0x2a00000>; | |
| linux,phandle = <0x03>; | |
| }; | |
| }; | |
| chosen { | |
| mmi,panel_ver = <0x00 0x186c2>; | |
| linux,serialhigh = <0x133f0e02>; | |
| mmi,msm_hw = "MSM8226 CS"; | |
| mmi,prod_id = <0x46>; | |
| mmi,display_auto_detect = <0x00>; | |
| bootargs = "console=null androidboot.hardware=qcom user_debug=31 msm_rtb.filter=0x37 vmalloc=400M utags.blkdev=/dev/block/platform/msm_sdcc.1/by-name/utags androidboot.emmc=true androidboot.serialno=0123456789 androidboot.baseband=msm androidboot.mode=normal androidboot.device=falcon androidboot.hwrev=0x83C0 androidboot.radio=0x1 androidboot.powerup_reason=0x00004000 bootreason=reboot androidboot.write_protect=0 restart.download_mode=0 androidboot.fsg-id= androidboot.secure_hardware=1 androidboot.cid=0x7 androidboot.bootloader=0x411A androidboot.carrier= mdss_mdp.panel=1:dsi:0:qcom,mdss_dsi_mot_cmi_720p_video_v2"; | |
| mmi,panel_name = "mipi_mot_video_cmi_hd_450"; | |
| mmi,panel_vendor_id = <0xd501>; | |
| mmi,powerup_reason = <0x4000>; | |
| linux,seriallow = <0xf000000>; | |
| linux,initrd-start = <0x2000000>; | |
| mmi,reserve = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; | |
| linux,initrd-end = <0x20afeb5>; | |
| linux,hwrev = <0x83c0>; | |
| mmi,mbmversion = <0x411a>; | |
| mmi,bl_sigs { | |
| 4 = "aboot.git=MBM-NG-V41.1A-0-g80481ae"; | |
| 2 = "rpm.git=MBM-NG-V41.1A-0-g8b7736e"; | |
| 0 = "sdi.git=MBM-NG-V41.1A-0-gdc5aeaf"; | |
| 1 = "sbl1.git=MBM-NG-V41.1A-0-g199f3c5"; | |
| mmi,reserve = <0x00 0x00 0x00 0x00 0x00>; | |
| 3 = "tz.git=MBM-NG-V41.1A-0-g99c1a7c"; | |
| }; | |
| }; | |
| aliases { | |
| sdhc3 = "/soc/sdhci@f9864900"; | |
| spi0 = "/soc/spi@f9923000"; | |
| sdhc1 = "/soc/sdhci@f9824900"; | |
| sdhc2 = "/soc/sdhci@f98a4900"; | |
| }; | |
| qcom,camera-led-flash { | |
| qcom,flash-type = <0x01>; | |
| cell-index = <0x00>; | |
| qcom,flash-source = <0x5c>; | |
| compatible = "qcom,camera-led-flash"; | |
| phandle = <0x0a>; | |
| qcom,torch-source = <0x5d>; | |
| linux,phandle = <0x0a>; | |
| }; | |
| }; |
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