Created
August 1, 2024 18:42
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lscpu | |
Architecture: x86_64 | |
CPU op-mode(s): 32-bit, 64-bit | |
Address sizes: 39 bits physical, 48 bits virtual | |
Byte Order: Little Endian | |
CPU(s): 12 | |
On-line CPU(s) list: 0-11 | |
Vendor ID: GenuineIntel | |
Model name: Intel(R) Core(TM) i7-8700 CPU @ 3.20GHz | |
CPU family: 6 | |
Model: 158 | |
Thread(s) per core: 2 | |
Core(s) per socket: 6 | |
Socket(s): 1 | |
Stepping: 10 | |
CPU max MHz: 4600.0000 | |
CPU min MHz: 800.0000 | |
BogoMIPS: 6399.96 | |
Flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss h | |
t tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_ts | |
c cpuid aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid sse4_ | |
1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault | |
epb invpcid_single pti ssbd ibrs ibpb stibp tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust b | |
mi1 avx2 smep bmi2 erms invpcid mpx rdseed adx smap clflushopt intel_pt xsaveopt xsavec xgetbv1 xsaves dtherm i | |
da arat pln pts hwp hwp_notify hwp_act_window hwp_epp md_clear flush_l1d arch_capabilities | |
Virtualization features: | |
Virtualization: VT-x | |
Caches (sum of all): | |
L1d: 192 KiB (6 instances) | |
L1i: 192 KiB (6 instances) | |
L2: 1.5 MiB (6 instances) | |
L3: 12 MiB (1 instance) | |
NUMA: | |
NUMA node(s): 1 | |
NUMA node0 CPU(s): 0-11 | |
Vulnerabilities: | |
Gather data sampling: Mitigation; Microcode | |
Itlb multihit: KVM: Mitigation: VMX disabled | |
L1tf: Mitigation; PTE Inversion; VMX conditional cache flushes, SMT vulnerable | |
Mds: Mitigation; Clear CPU buffers; SMT vulnerable | |
Meltdown: Mitigation; PTI | |
Mmio stale data: Mitigation; Clear CPU buffers; SMT vulnerable | |
Reg file data sampling: Not affected | |
Retbleed: Mitigation; IBRS | |
Spec rstack overflow: Not affected | |
Spec store bypass: Mitigation; Speculative Store Bypass disabled via prctl and seccomp | |
Spectre v1: Mitigation; usercopy/swapgs barriers and __user pointer sanitization | |
Spectre v2: Mitigation; IBRS; IBPB conditional; STIBP conditional; RSB filling; PBRSB-eIBRS Not affected; BHI Not affected | |
Srbds: Mitigation; Microcode | |
Tsx async abort: Mitigation; TSX disabled |
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